2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Samsung Exynos 5 Pad Control
29 * Chapter 4, Exynos 5 Dual User's Manual Public Rev 1.00
31 #ifdef USB_GLOBAL_INCLUDE_FILE
32 #include USB_GLOBAL_INCLUDE_FILE
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
44 #include <sys/timeet.h>
45 #include <sys/timetc.h>
46 #include <sys/watchdog.h>
47 #include <sys/mutex.h>
50 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57 #include <machine/intr.h>
62 #include <arm/samsung/exynos/exynos5_combiner.h>
63 #include <arm/samsung/exynos/exynos5_pad.h>
65 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
66 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
68 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
81 #define READ4(_sc, _port, _reg) \
82 bus_space_read_4(_sc->bst[_port], _sc->bsh[_port], _reg)
83 #define WRITE4(_sc, _port, _reg, _val) \
84 bus_space_write_4(_sc->bst[_port], _sc->bsh[_port], _reg, _val)
89 static device_t pad_get_bus(device_t);
90 static int pad_pin_max(device_t, int *);
91 static int pad_pin_getcaps(device_t, uint32_t, uint32_t *);
92 static int pad_pin_getname(device_t, uint32_t, char *);
93 static int pad_pin_getflags(device_t, uint32_t, uint32_t *);
94 static int pad_pin_setflags(device_t, uint32_t, uint32_t);
95 static int pad_pin_set(device_t, uint32_t, unsigned int);
96 static int pad_pin_get(device_t, uint32_t, unsigned int *);
97 static int pad_pin_toggle(device_t, uint32_t pin);
105 uint32_t ext_flt_con;
111 struct resource *res[MAX_PORTS * 2];
112 bus_space_tag_t bst[MAX_PORTS];
113 bus_space_handle_t bsh[MAX_PORTS];
116 struct gpio_pin gpio_pins[MAX_NGPIO];
117 void *gpio_ih[MAX_PORTS];
121 struct resource_spec *pad_spec;
122 struct gpio_bank *gpio_map;
123 struct interrupt_entry *interrupt_table;
127 struct pad_softc *gpio_sc;
129 static struct resource_spec pad_spec_5250[] = {
130 { SYS_RES_MEMORY, 0, RF_ACTIVE },
131 { SYS_RES_MEMORY, 1, RF_ACTIVE },
132 { SYS_RES_MEMORY, 2, RF_ACTIVE },
133 { SYS_RES_MEMORY, 3, RF_ACTIVE },
134 { SYS_RES_IRQ, 0, RF_ACTIVE },
135 { SYS_RES_IRQ, 1, RF_ACTIVE },
136 { SYS_RES_IRQ, 2, RF_ACTIVE },
137 { SYS_RES_IRQ, 3, RF_ACTIVE },
141 static struct resource_spec pad_spec_5420[] = {
142 { SYS_RES_MEMORY, 0, RF_ACTIVE },
143 { SYS_RES_MEMORY, 1, RF_ACTIVE },
144 { SYS_RES_MEMORY, 2, RF_ACTIVE },
145 { SYS_RES_MEMORY, 3, RF_ACTIVE },
146 { SYS_RES_MEMORY, 4, RF_ACTIVE },
147 { SYS_RES_IRQ, 0, RF_ACTIVE },
148 { SYS_RES_IRQ, 1, RF_ACTIVE },
149 { SYS_RES_IRQ, 2, RF_ACTIVE },
150 { SYS_RES_IRQ, 3, RF_ACTIVE },
151 { SYS_RES_IRQ, 4, RF_ACTIVE },
155 static struct ofw_compat_data compat_data[] = {
156 {"samsung,exynos5420-padctrl", EXYNOS5420},
157 {"samsung,exynos5250-padctrl", EXYNOS5250},
167 static struct pad_intr intr_map[MAX_NGPIO];
169 struct interrupt_entry {
171 char *combiner_source_name;
174 struct interrupt_entry interrupt_table_5250[N_EXT_INTS] = {
193 struct interrupt_entry interrupt_table_5420[N_EXT_INTS] = {
213 * 253 multi-functional input/output ports
216 static struct gpio_bank gpio_map_5250[] = {
218 { "gpa0", 0, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
219 { "gpa1", 0, 0x020, 6, 0x704, 0x808, 0x904, 0xA04 },
220 { "gpa2", 0, 0x040, 8, 0x708, 0x810, 0x908, 0xA08 },
221 { "gpb0", 0, 0x060, 5, 0x70C, 0x818, 0x90C, 0xA0C },
222 { "gpb1", 0, 0x080, 5, 0x710, 0x820, 0x910, 0xA10 },
223 { "gpb2", 0, 0x0A0, 4, 0x714, 0x828, 0x914, 0xA14 },
224 { "gpb3", 0, 0x0C0, 4, 0x718, 0x830, 0x918, 0xA18 },
225 { "gpc0", 0, 0x0E0, 7, 0x71C, 0x838, 0x91C, 0xA1C },
226 { "gpc1", 0, 0x100, 4, 0x720, 0x840, 0x920, 0xA20 },
227 { "gpc2", 0, 0x120, 7, 0x724, 0x848, 0x924, 0xA24 },
228 { "gpc3", 0, 0x140, 7, 0x728, 0x850, 0x928, 0xA28 },
229 { "gpd0", 0, 0x160, 4, 0x72C, 0x858, 0x92C, 0xA2C },
230 { "gpd1", 0, 0x180, 8, 0x730, 0x860, 0x930, 0xA30 },
231 { "gpy0", 0, 0x1A0, 6, 0, 0, 0, 0 },
232 { "gpy1", 0, 0x1C0, 4, 0, 0, 0, 0 },
233 { "gpy2", 0, 0x1E0, 6, 0, 0, 0, 0 },
234 { "gpy3", 0, 0x200, 8, 0, 0, 0, 0 },
235 { "gpy4", 0, 0x220, 8, 0, 0, 0, 0 },
236 { "gpy5", 0, 0x240, 8, 0, 0, 0, 0 },
237 { "gpy6", 0, 0x260, 8, 0, 0, 0, 0 },
238 { "gpc4", 0, 0x2E0, 7, 0x734, 0x868, 0x934, 0xA34 },
241 { "gpx0", 0, 0xC00, 8, 0xE00, 0xE80, 0xF00, 0xF40 },
242 { "gpx1", 0, 0xC20, 8, 0xE04, 0xE88, 0xF04, 0xF44 },
243 { "gpx2", 0, 0xC40, 8, 0xE08, 0xE90, 0xF08, 0xF48 },
244 { "gpx3", 0, 0xC60, 8, 0xE0C, 0xE98, 0xF0C, 0xF4C },
246 { "gpe0", 1, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
247 { "gpe1", 1, 0x020, 2, 0x704, 0x808, 0x904, 0xA04 },
248 { "gpf0", 1, 0x040, 4, 0x708, 0x810, 0x908, 0xA08 },
249 { "gpf1", 1, 0x060, 4, 0x70C, 0x818, 0x90C, 0xA0C },
250 { "gpg0", 1, 0x080, 8, 0x710, 0x820, 0x910, 0xA10 },
251 { "gpg1", 1, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 },
252 { "gpg2", 1, 0x0C0, 2, 0x718, 0x830, 0x918, 0xA18 },
253 { "gph0", 1, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C },
254 { "gph1", 1, 0x100, 8, 0x720, 0x840, 0x920, 0xA20 },
256 { "gpv0", 2, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
257 { "gpv1", 2, 0x020, 8, 0x704, 0x808, 0x904, 0xA04 },
258 { "gpv2", 2, 0x060, 8, 0x708, 0x810, 0x908, 0xA08 },
259 { "gpv3", 2, 0x080, 8, 0x70C, 0x818, 0x90C, 0xA0C },
260 { "gpv4", 2, 0x0C0, 2, 0x710, 0x820, 0x910, 0xA10 },
262 { "gpz", 3, 0x000, 7, 0x700, 0x800, 0x900, 0xA00 },
264 { NULL, -1, -1, -1, -1, -1, -1, -1 },
267 static struct gpio_bank gpio_map_5420[] = {
269 { "gpy7", 0, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
270 { "gpx0", 0, 0xC00, 8, 0x704, 0xE80, 0xF00, 0xF40 },
271 { "gpx1", 0, 0xC20, 8, 0x708, 0xE88, 0xF04, 0xF44 },
272 { "gpx2", 0, 0xC40, 8, 0x70C, 0xE90, 0xF08, 0xF48 },
273 { "gpx3", 0, 0xC60, 8, 0x710, 0xE98, 0xF0C, 0xF4C },
276 { "gpc0", 1, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
277 { "gpc1", 1, 0x020, 8, 0x704, 0x808, 0x904, 0xA04 },
278 { "gpc2", 1, 0x040, 7, 0x708, 0x810, 0x908, 0xA08 },
279 { "gpc3", 1, 0x060, 4, 0x70C, 0x818, 0x90C, 0xA0C },
280 { "gpc4", 1, 0x080, 2, 0x710, 0x820, 0x910, 0xA10 },
281 { "gpd1", 1, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 },
282 { "gpy0", 1, 0x0C0, 6, 0x718, 0x830, 0x918, 0xA18 },
283 { "gpy1", 1, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C },
284 { "gpy2", 1, 0x100, 6, 0x720, 0x840, 0x920, 0xA20 },
285 { "gpy3", 1, 0x120, 8, 0x724, 0x848, 0x924, 0xA24 },
286 { "gpy4", 1, 0x140, 8, 0x728, 0x850, 0x928, 0xA28 },
287 { "gpy5", 1, 0x160, 8, 0x72C, 0x858, 0x92C, 0xA2C },
288 { "gpy6", 1, 0x180, 8, 0x730, 0x860, 0x930, 0xA30 },
291 { "gpe0", 2, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
292 { "gpe1", 2, 0x020, 2, 0x704, 0x808, 0x904, 0xA04 },
293 { "gpf0", 2, 0x040, 6, 0x708, 0x810, 0x908, 0xA08 },
294 { "gpf1", 2, 0x060, 8, 0x70C, 0x818, 0x90C, 0xA0C },
295 { "gpg0", 2, 0x080, 8, 0x710, 0x820, 0x910, 0xA10 },
296 { "gpg1", 2, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 },
297 { "gpg2", 2, 0x0C0, 2, 0x718, 0x830, 0x918, 0xA18 },
298 { "gpj4", 2, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C },
301 { "gpa0", 3, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
302 { "gpa1", 3, 0x020, 6, 0x704, 0x808, 0x904, 0xA04 },
303 { "gpa2", 3, 0x040, 8, 0x708, 0x810, 0x908, 0xA08 },
304 { "gpb0", 3, 0x060, 5, 0x70C, 0x818, 0x90C, 0xA0C },
305 { "gpb1", 3, 0x080, 5, 0x710, 0x820, 0x910, 0xA10 },
306 { "gpb2", 3, 0x0A0, 4, 0x714, 0x828, 0x914, 0xA14 },
307 { "gpb3", 3, 0x0C0, 8, 0x718, 0x830, 0x918, 0xA18 },
308 { "gpb4", 3, 0x0E0, 2, 0x71C, 0x838, 0x91C, 0xA1C },
309 { "gph0", 3, 0x100, 8, 0x720, 0x840, 0x920, 0xA20 },
312 { "gpz", 4, 0x000, 7, 0x700, 0x800, 0x900, 0xA00 },
314 { NULL, -1, -1, -1, -1, -1, -1, -1 },
318 get_bank(struct pad_softc *sc, int gpio_number,
319 struct gpio_bank *bank, int *pin_shift)
326 for (i = 0; sc->gpio_map[i].ngpio != -1; i++) {
327 ngpio = sc->gpio_map[i].ngpio;
329 if ((n + ngpio) > gpio_number) {
330 *bank = sc->gpio_map[i];
331 *pin_shift = (gpio_number - n);
344 struct port_softc *sc;
348 return (FILTER_HANDLED);
354 struct pad_softc *sc;
366 for (i = 0; sc->gpio_map[i].ngpio != -1; i++) {
368 ngpio = sc->gpio_map[i].ngpio;
370 if (sc->gpio_map[i].pend == 0) {
375 reg = READ4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend);
377 for (j = 0; j < ngpio; j++) {
378 if (reg & (1 << j)) {
382 if (intr_map[k].enabled == 1) {
384 ih_user = intr_map[k].ih_user;
392 WRITE4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend, reg);
400 pad_setup_intr(int gpio_number, void (*ih)(void *), void *ih_user)
402 struct interrupt_entry *entry;
403 struct pad_intr *pad_irq;
404 struct gpio_bank bank;
405 struct pad_softc *sc;
413 device_printf(sc->dev, "Error: pad is not attached\n");
417 if (get_bank(sc, gpio_number, &bank, &pin_shift) != 0)
421 for (i = 0; i < N_EXT_INTS; i++)
422 if (sc->interrupt_table[i].gpio_number == gpio_number)
423 entry = &(sc->interrupt_table[i]);
426 device_printf(sc->dev, "Cant find interrupt source for %d\n",
432 printf("Request interrupt name %s\n", entry->combiner_source_name);
435 pad_irq = &intr_map[gpio_number];
436 pad_irq->enabled = 1;
438 pad_irq->ih_user = ih_user;
440 /* Setup port as external interrupt source */
441 reg = READ4(sc, bank.port, bank.con);
442 reg |= (0xf << (pin_shift * 4));
444 printf("writing 0x%08x to 0x%08x\n", reg, bank.con);
446 WRITE4(sc, bank.port, bank.con, reg);
449 * Configure interrupt pin
451 * 0x0 = Sets Low level
452 * 0x1 = Sets High level
453 * 0x2 = Triggers Falling edge
454 * 0x3 = Triggers Rising edge
455 * 0x4 = Triggers Both edge
457 * TODO: add parameter. For now configure as 0x0
459 reg = READ4(sc, bank.port, bank.ext_con);
460 reg &= ~(0x7 << (pin_shift * 4));
461 WRITE4(sc, bank.port, bank.ext_con, reg);
464 reg = READ4(sc, bank.port, bank.mask);
465 reg &= ~(1 << pin_shift);
466 WRITE4(sc, bank.port, bank.mask, reg);
468 combiner_setup_intr(entry->combiner_source_name, ext_intr, sc);
474 pad_probe(device_t dev)
477 if (!ofw_bus_status_okay(dev))
480 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
481 device_set_desc(dev, "Exynos Pad Control");
482 return (BUS_PROBE_DEFAULT);
489 pad_attach(device_t dev)
491 struct gpio_bank bank;
492 struct pad_softc *sc;
497 sc = device_get_softc(dev);
499 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
501 sc->model = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
504 sc->pad_spec = pad_spec_5250;
505 sc->gpio_map = gpio_map_5250;
506 sc->interrupt_table = interrupt_table_5250;
507 sc->gpio_npins = 253;
511 sc->pad_spec = pad_spec_5420;
512 sc->gpio_map = gpio_map_5420;
513 sc->interrupt_table = interrupt_table_5420;
514 sc->gpio_npins = 232;
521 if (bus_alloc_resources(dev, sc->pad_spec, sc->res)) {
522 device_printf(dev, "could not allocate resources\n");
526 /* Memory interface */
528 for (i = 0; i < sc->nports; i++) {
529 sc->bst[i] = rman_get_bustag(sc->res[i]);
530 sc->bsh[i] = rman_get_bushandle(sc->res[i]);
537 for (i = 0; i < sc->nports; i++) {
538 if ((bus_setup_intr(dev, sc->res[sc->nports + i],
539 INTR_TYPE_BIO | INTR_MPSAFE, port_intr,
540 NULL, sc, &sc->gpio_ih[i]))) {
542 "ERROR: Unable to register interrupt handler\n");
547 for (i = 0; i < sc->gpio_npins; i++) {
548 sc->gpio_pins[i].gp_pin = i;
549 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
551 if (get_bank(sc, i, &bank, &pin_shift) != 0)
556 reg = READ4(sc, bank.port, bank.con);
557 if (reg & (PIN_OUT << pin_shift))
558 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
560 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
562 /* TODO: add other pin statuses */
564 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
565 "pad%d.%d", device_get_unit(dev), i);
567 sc->busdev = gpiobus_attach_bus(dev);
568 if (sc->busdev == NULL)
574 for (i = 0; i < sc->nports; i++) {
576 bus_teardown_intr(dev, sc->res[sc->nports + i],
579 bus_release_resources(dev, sc->pad_spec, sc->res);
580 mtx_destroy(&sc->sc_mtx);
586 pad_get_bus(device_t dev)
588 struct pad_softc *sc;
590 sc = device_get_softc(dev);
596 pad_pin_max(device_t dev, int *maxpin)
598 struct pad_softc *sc;
600 sc = device_get_softc(dev);
602 *maxpin = sc->gpio_npins - 1;
607 pad_pin_getname(device_t dev, uint32_t pin, char *name)
609 struct pad_softc *sc;
612 sc = device_get_softc(dev);
613 for (i = 0; i < sc->gpio_npins; i++) {
614 if (sc->gpio_pins[i].gp_pin == pin)
618 if (i >= sc->gpio_npins)
622 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
629 pad_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
631 struct pad_softc *sc;
634 sc = device_get_softc(dev);
635 for (i = 0; i < sc->gpio_npins; i++) {
636 if (sc->gpio_pins[i].gp_pin == pin)
640 if (i >= sc->gpio_npins)
644 *caps = sc->gpio_pins[i].gp_caps;
651 pad_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
653 struct pad_softc *sc;
656 sc = device_get_softc(dev);
657 for (i = 0; i < sc->gpio_npins; i++) {
658 if (sc->gpio_pins[i].gp_pin == pin)
662 if (i >= sc->gpio_npins)
666 *flags = sc->gpio_pins[i].gp_flags;
673 pad_pin_get(device_t dev, uint32_t pin, unsigned int *val)
675 struct gpio_bank bank;
676 struct pad_softc *sc;
680 sc = device_get_softc(dev);
681 for (i = 0; i < sc->gpio_npins; i++) {
682 if (sc->gpio_pins[i].gp_pin == pin)
686 if (i >= sc->gpio_npins)
689 if (get_bank(sc, pin, &bank, &pin_shift) != 0)
693 if (READ4(sc, bank.port, bank.con + 0x4) & (1 << pin_shift))
703 pad_pin_toggle(device_t dev, uint32_t pin)
705 struct gpio_bank bank;
706 struct pad_softc *sc;
711 sc = device_get_softc(dev);
712 for (i = 0; i < sc->gpio_npins; i++) {
713 if (sc->gpio_pins[i].gp_pin == pin)
717 if (i >= sc->gpio_npins)
720 if (get_bank(sc, pin, &bank, &pin_shift) != 0)
724 reg = READ4(sc, bank.port, bank.con + 0x4);
725 if (reg & (1 << pin_shift))
726 reg &= ~(1 << pin_shift);
728 reg |= (1 << pin_shift);
729 WRITE4(sc, bank.port, bank.con + 0x4, reg);
737 pad_pin_configure(struct pad_softc *sc, struct gpio_pin *pin,
740 struct gpio_bank bank;
747 * Manage input/output
749 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
750 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
752 if (get_bank(sc, pin->gp_pin, &bank, &pin_shift) != 0)
758 printf("bank is 0x%08x pin_shift %d\n", bank.con, pin_shift);
761 if (flags & GPIO_PIN_OUTPUT) {
762 pin->gp_flags |= GPIO_PIN_OUTPUT;
763 reg = READ4(sc, bank.port, bank.con);
764 reg &= ~(0xf << pin_shift);
765 reg |= (PIN_OUT << pin_shift);
766 WRITE4(sc, bank.port, bank.con, reg);
768 pin->gp_flags |= GPIO_PIN_INPUT;
769 reg = READ4(sc, bank.port, bank.con);
770 reg &= ~(0xf << pin_shift);
771 WRITE4(sc, bank.port, bank.con, reg);
780 pad_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
782 struct pad_softc *sc;
785 sc = device_get_softc(dev);
786 for (i = 0; i < sc->gpio_npins; i++) {
787 if (sc->gpio_pins[i].gp_pin == pin)
791 if (i >= sc->gpio_npins)
794 pad_pin_configure(sc, &sc->gpio_pins[i], flags);
800 pad_pin_set(device_t dev, uint32_t pin, unsigned int value)
802 struct pad_softc *sc;
803 struct gpio_bank bank;
808 sc = device_get_softc(dev);
809 for (i = 0; i < sc->gpio_npins; i++) {
810 if (sc->gpio_pins[i].gp_pin == pin)
814 if (i >= sc->gpio_npins)
817 if (get_bank(sc, pin, &bank, &pin_shift) != 0)
821 reg = READ4(sc, bank.port, bank.con + 0x4);
822 reg &= ~(PIN_OUT << pin_shift);
824 reg |= (PIN_OUT << pin_shift);
825 WRITE4(sc, bank.port, bank.con + 0x4, reg);
831 static device_method_t pad_methods[] = {
832 DEVMETHOD(device_probe, pad_probe),
833 DEVMETHOD(device_attach, pad_attach),
836 DEVMETHOD(gpio_get_bus, pad_get_bus),
837 DEVMETHOD(gpio_pin_max, pad_pin_max),
838 DEVMETHOD(gpio_pin_getname, pad_pin_getname),
839 DEVMETHOD(gpio_pin_getcaps, pad_pin_getcaps),
840 DEVMETHOD(gpio_pin_getflags, pad_pin_getflags),
841 DEVMETHOD(gpio_pin_get, pad_pin_get),
842 DEVMETHOD(gpio_pin_toggle, pad_pin_toggle),
843 DEVMETHOD(gpio_pin_setflags, pad_pin_setflags),
844 DEVMETHOD(gpio_pin_set, pad_pin_set),
848 static driver_t pad_driver = {
851 sizeof(struct pad_softc),
854 static devclass_t pad_devclass;
856 DRIVER_MODULE(pad, simplebus, pad_driver, pad_devclass, 0, 0);