2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Based on OMAP3 INTC code by Ben Gray
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/module.h>
40 #include <machine/bus.h>
41 #include <machine/intr.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #define INTC_REVISION 0x00
49 #define INTC_SYSCONFIG 0x10
50 #define INTC_SYSSTATUS 0x14
51 #define INTC_SIR_IRQ 0x40
52 #define INTC_CONTROL 0x48
53 #define INTC_THRESHOLD 0x68
54 #define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))
55 #define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))
56 #define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))
57 #define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))
59 struct ti_aintc_softc {
61 struct resource * aintc_res[3];
62 bus_space_tag_t aintc_bst;
63 bus_space_handle_t aintc_bsh;
67 static struct resource_spec ti_aintc_spec[] = {
68 { SYS_RES_MEMORY, 0, RF_ACTIVE },
72 static struct ti_aintc_softc *ti_aintc_sc = NULL;
74 #define aintc_read_4(_sc, reg) \
75 bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg))
76 #define aintc_write_4(_sc, reg, val) \
77 bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))
79 /* List of compatible strings for FDT tree */
80 static struct ofw_compat_data compat_data[] = {
81 {"ti,am33xx-intc", 1},
87 aintc_post_filter(void *arg)
90 arm_irq_memory_barrier(0);
91 aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */
95 ti_aintc_probe(device_t dev)
97 if (!ofw_bus_status_okay(dev))
100 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
103 device_set_desc(dev, "TI AINTC Interrupt Controller");
104 return (BUS_PROBE_DEFAULT);
108 ti_aintc_attach(device_t dev)
110 struct ti_aintc_softc *sc = device_get_softc(dev);
118 if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) {
119 device_printf(dev, "could not allocate resources\n");
123 sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]);
124 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]);
128 x = aintc_read_4(sc, INTC_REVISION);
129 device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF);
132 aintc_write_4(sc, INTC_SYSCONFIG, 2);
134 /* Wait for reset to complete */
135 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));
137 /*Set Priority Threshold */
138 aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
140 arm_post_filter = aintc_post_filter;
145 static device_method_t ti_aintc_methods[] = {
146 DEVMETHOD(device_probe, ti_aintc_probe),
147 DEVMETHOD(device_attach, ti_aintc_attach),
151 static driver_t ti_aintc_driver = {
154 sizeof(struct ti_aintc_softc),
157 static devclass_t ti_aintc_devclass;
159 EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,
160 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
163 arm_get_next_irq(int last_irq)
165 struct ti_aintc_softc *sc = ti_aintc_sc;
168 /* Get the next active interrupt */
169 active_irq = aintc_read_4(sc, INTC_SIR_IRQ);
171 /* Check for spurious interrupt */
172 if ((active_irq & 0xffffff80)) {
173 device_printf(sc->sc_dev,
174 "Spurious interrupt detected (0x%08x)\n", active_irq);
175 aintc_write_4(sc, INTC_SIR_IRQ, 0);
179 if (active_irq != last_irq)
186 arm_mask_irq(uintptr_t nb)
188 struct ti_aintc_softc *sc = ti_aintc_sc;
190 aintc_write_4(sc, INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F)));
191 aintc_write_4(sc, INTC_CONTROL, 1); /* EOI */
195 arm_unmask_irq(uintptr_t nb)
197 struct ti_aintc_softc *sc = ti_aintc_sc;
199 arm_irq_memory_barrier(nb);
200 aintc_write_4(sc, INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));