sys/arm/ti/am335x/am335x_ehrpwm.c

   1 /*-
   2  * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/kernel.h>
  34 #include <sys/limits.h>
  35 #include <sys/lock.h>
  36 #include <sys/module.h>
  37 #include <sys/mutex.h>
  38 #include <sys/resource.h>
  39 #include <sys/rman.h>
  40 #include <sys/sysctl.h>
  41
  42 #include <machine/bus.h>
  43
  44 #include <dev/ofw/openfirm.h>
  45 #include <dev/ofw/ofw_bus.h>
  46 #include <dev/ofw/ofw_bus_subr.h>
  47
  48 #include "pwmbus_if.h"
  49
  50 #include "am335x_pwm.h"
  51
  52 /*******************************************************************************
  53  * Enhanced resolution PWM driver.  Many of the advanced featues of the hardware
  54  * are not supported by this driver.  What is implemented here is simple
  55  * variable-duty-cycle PWM output.
  56  *
  57  * Note that this driver was historically configured using a set of sysctl
  58  * variables/procs, and later gained support for the PWM(9) API.  The sysctl
  59  * code is still present to support existing apps, but that interface is
  60  * considered deprecated.
  61  *
  62  * An important caveat is that the original sysctl interface and the new PWM API
  63  * cannot both be used at once.  If both interfaces are used to change
  64  * configuration, it's quite likely you won't get the expected results.  Also,
  65  * reading the sysctl values after configuring via PWM will not return the right
  66  * results.
  67  ******************************************************************************/
  68
  69 /* In ticks */
  70 #define DEFAULT_PWM_PERIOD      1000
  71 #define PWM_CLOCK               100000000UL
  72
  73 #define NS_PER_SEC              1000000000
  74
  75 #define PWM_LOCK(_sc)           mtx_lock(&(_sc)->sc_mtx)
  76 #define PWM_UNLOCK(_sc)         mtx_unlock(&(_sc)->sc_mtx)
  77 #define PWM_LOCK_ASSERT(_sc)    mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
  78 #define PWM_LOCK_INIT(_sc)      mtx_init(&(_sc)->sc_mtx, \
  79     device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF)
  80 #define PWM_LOCK_DESTROY(_sc)   mtx_destroy(&(_sc)->sc_mtx)
  81
  82 #define EPWM_READ2(_sc, reg)    bus_read_2((_sc)->sc_mem_res, reg)
  83 #define EPWM_WRITE2(_sc, reg, value)    \
  84     bus_write_2((_sc)->sc_mem_res, reg, value)
  85
  86 #define EPWM_TBCTL              0x00
  87 #define         TBCTL_FREERUN           (2 << 14)
  88 #define         TBCTL_PHDIR_UP          (1 << 13)
  89 #define         TBCTL_PHDIR_DOWN        (0 << 13)
  90 #define         TBCTL_CLKDIV(x)         ((x) << 10)
  91 #define         TBCTL_CLKDIV_MASK       (3 << 10)
  92 #define         TBCTL_HSPCLKDIV(x)      ((x) << 7)
  93 #define         TBCTL_HSPCLKDIV_MASK    (3 << 7)
  94 #define         TBCTL_SYNCOSEL_DISABLED (3 << 4)
  95 #define         TBCTL_PRDLD_SHADOW      (0 << 3)
  96 #define         TBCTL_PRDLD_IMMEDIATE   (0 << 3)
  97 #define         TBCTL_PHSEN_ENABLED     (1 << 2)
  98 #define         TBCTL_PHSEN_DISABLED    (0 << 2)
  99 #define         TBCTL_CTRMODE_MASK      (3)
 100 #define         TBCTL_CTRMODE_UP        (0 << 0)
 101 #define         TBCTL_CTRMODE_DOWN      (1 << 0)
 102 #define         TBCTL_CTRMODE_UPDOWN    (2 << 0)
 103 #define         TBCTL_CTRMODE_FREEZE    (3 << 0)
 104
 105 #define EPWM_TBSTS              0x02
 106 #define EPWM_TBPHSHR            0x04
 107 #define EPWM_TBPHS              0x06
 108 #define EPWM_TBCNT              0x08
 109 #define EPWM_TBPRD              0x0a
 110 /* Counter-compare */
 111 #define EPWM_CMPCTL             0x0e
 112 #define         CMPCTL_SHDWBMODE_SHADOW         (1 << 6)
 113 #define         CMPCTL_SHDWBMODE_IMMEDIATE      (0 << 6)
 114 #define         CMPCTL_SHDWAMODE_SHADOW         (1 << 4)
 115 #define         CMPCTL_SHDWAMODE_IMMEDIATE      (0 << 4)
 116 #define         CMPCTL_LOADBMODE_ZERO           (0 << 2)
 117 #define         CMPCTL_LOADBMODE_PRD            (1 << 2)
 118 #define         CMPCTL_LOADBMODE_EITHER         (2 << 2)
 119 #define         CMPCTL_LOADBMODE_FREEZE         (3 << 2)
 120 #define         CMPCTL_LOADAMODE_ZERO           (0 << 0)
 121 #define         CMPCTL_LOADAMODE_PRD            (1 << 0)
 122 #define         CMPCTL_LOADAMODE_EITHER         (2 << 0)
 123 #define         CMPCTL_LOADAMODE_FREEZE         (3 << 0)
 124 #define EPWM_CMPAHR             0x10
 125 #define EPWM_CMPA               0x12
 126 #define EPWM_CMPB               0x14
 127 /* CMPCTL_LOADAMODE_ZERO */
 128 #define EPWM_AQCTLA             0x16
 129 #define EPWM_AQCTLB             0x18
 130 #define         AQCTL_CBU_NONE          (0 << 8)
 131 #define         AQCTL_CBU_CLEAR         (1 << 8)
 132 #define         AQCTL_CBU_SET           (2 << 8)
 133 #define         AQCTL_CBU_TOGGLE        (3 << 8)
 134 #define         AQCTL_CAU_NONE          (0 << 4)
 135 #define         AQCTL_CAU_CLEAR         (1 << 4)
 136 #define         AQCTL_CAU_SET           (2 << 4)
 137 #define         AQCTL_CAU_TOGGLE        (3 << 4)
 138 #define         AQCTL_ZRO_NONE          (0 << 0)
 139 #define         AQCTL_ZRO_CLEAR         (1 << 0)
 140 #define         AQCTL_ZRO_SET           (2 << 0)
 141 #define         AQCTL_ZRO_TOGGLE        (3 << 0)
 142 #define EPWM_AQSFRC             0x1a
 143 #define EPWM_AQCSFRC            0x1c
 144 #define         AQCSFRC_OFF             0
 145 #define         AQCSFRC_LO              1
 146 #define         AQCSFRC_HI              2
 147 #define         AQCSFRC_MASK            3
 148 #define         AQCSFRC(chan, hilo)     ((hilo) << (2 * chan))
 149
 150 /* Trip-Zone module */
 151 #define EPWM_TZCTL              0x28
 152 #define EPWM_TZFLG              0x2C
 153 /* High-Resolution PWM */
 154 #define EPWM_HRCTL              0x40
 155 #define         HRCTL_DELMODE_BOTH      3
 156 #define         HRCTL_DELMODE_FALL      2
 157 #define         HRCTL_DELMODE_RISE      1
 158
 159 static device_probe_t am335x_ehrpwm_probe;
 160 static device_attach_t am335x_ehrpwm_attach;
 161 static device_detach_t am335x_ehrpwm_detach;
 162
 163 static int am335x_ehrpwm_clkdiv[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
 164
 165 struct ehrpwm_channel {
 166         u_int   duty;           /* on duration, in ns */
 167         bool    enabled;        /* channel enabled? */
 168         bool    inverted;       /* signal inverted? */
 169 };
 170 #define NUM_CHANNELS    2
 171
 172 struct am335x_ehrpwm_softc {
 173         device_t                sc_dev;
 174         device_t                sc_busdev;
 175         struct mtx              sc_mtx;
 176         struct resource         *sc_mem_res;
 177         int                     sc_mem_rid;
 178
 179         /* Things used for configuration via sysctl [deprecated]. */
 180         int                     sc_pwm_clkdiv;
 181         int                     sc_pwm_freq;
 182         struct sysctl_oid       *sc_clkdiv_oid;
 183         struct sysctl_oid       *sc_freq_oid;
 184         struct sysctl_oid       *sc_period_oid;
 185         struct sysctl_oid       *sc_chanA_oid;
 186         struct sysctl_oid       *sc_chanB_oid;
 187         uint32_t                sc_pwm_period;
 188         uint32_t                sc_pwm_dutyA;
 189         uint32_t                sc_pwm_dutyB;
 190
 191         /* Things used for configuration via pwm(9) api. */
 192         u_int                   sc_clkfreq; /* frequency in Hz */
 193         u_int                   sc_clktick; /* duration in ns */
 194         u_int                   sc_period;  /* duration in ns */
 195         struct ehrpwm_channel   sc_channels[NUM_CHANNELS];
 196 };
 197
 198 static struct ofw_compat_data compat_data[] = {
 199         {"ti,am33xx-ehrpwm",    true},
 200         {NULL,                  false},
 201 };
 202 SIMPLEBUS_PNP_INFO(compat_data);
 203
 204 static void
 205 am335x_ehrpwm_cfg_duty(struct am335x_ehrpwm_softc *sc, u_int chan, u_int duty)
 206 {
 207         u_int tbcmp;
 208
 209         if (duty == 0)
 210                 tbcmp = 0;
 211         else
 212                 tbcmp = max(1, duty / sc->sc_clktick);
 213
 214         sc->sc_channels[chan].duty = tbcmp * sc->sc_clktick;
 215
 216         PWM_LOCK_ASSERT(sc);
 217         EPWM_WRITE2(sc, (chan == 0) ? EPWM_CMPA : EPWM_CMPB, tbcmp);
 218 }
 219
 220 static void
 221 am335x_ehrpwm_cfg_enable(struct am335x_ehrpwm_softc *sc, u_int chan, bool enable)
 222 {
 223         uint16_t regval;
 224
 225         sc->sc_channels[chan].enabled = enable;
 226
 227         /*
 228          * Turn off any existing software-force of the channel, then force
 229          * it in the right direction (high or low) if it's not being enabled.
 230          */
 231         PWM_LOCK_ASSERT(sc);
 232         regval = EPWM_READ2(sc, EPWM_AQCSFRC);
 233         regval &= ~AQCSFRC(chan, AQCSFRC_MASK);
 234         if (!sc->sc_channels[chan].enabled) {
 235                 if (sc->sc_channels[chan].inverted)
 236                         regval |= AQCSFRC(chan, AQCSFRC_HI);
 237                 else
 238                         regval |= AQCSFRC(chan, AQCSFRC_LO);
 239         }
 240         EPWM_WRITE2(sc, EPWM_AQCSFRC, regval);
 241 }
 242
 243 static bool
 244 am335x_ehrpwm_cfg_period(struct am335x_ehrpwm_softc *sc, u_int period)
 245 {
 246         uint16_t regval;
 247         u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd;
 248
 249         /* Can't do a period shorter than 2 clock ticks. */
 250         if (period < 2 * NS_PER_SEC / PWM_CLOCK) {
 251                 sc->sc_clkfreq = 0;
 252                 sc->sc_clktick = 0;
 253                 sc->sc_period  = 0;
 254                 return (false);
 255         }
 256
 257         /*
 258          * Figure out how much we have to divide down the base 100MHz clock so
 259          * that we can express the requested period as a 16-bit tick count.
 260          */
 261         tbprd = 0;
 262         for (clkdiv = 0; clkdiv < 8; ++clkdiv) {
 263                 const u_int cd = 1 << clkdiv;
 264                 for (hspclkdiv = 0; hspclkdiv < 8; ++hspclkdiv) {
 265                         const u_int cdhs = max(1, hspclkdiv * 2);
 266                         pwmclk = PWM_CLOCK / (cd * cdhs);
 267                         pwmtick = NS_PER_SEC / pwmclk;
 268                         if (period / pwmtick < 65536) {
 269                                 tbprd = period / pwmtick;
 270                                 break;
 271                         }
 272                 }
 273                 if (tbprd != 0)
 274                         break;
 275         }
 276
 277         /* Handle requested period too long for available clock divisors. */
 278         if (tbprd == 0)
 279                 return (false);
 280
 281         /*
 282          * If anything has changed from the current settings, reprogram the
 283          * clock divisors and period register.
 284          */
 285         if (sc->sc_clkfreq != pwmclk || sc->sc_clktick != pwmtick ||
 286             sc->sc_period != tbprd * pwmtick) {
 287
 288                 sc->sc_clkfreq = pwmclk;
 289                 sc->sc_clktick = pwmtick;
 290                 sc->sc_period  = tbprd * pwmtick;
 291
 292                 PWM_LOCK_ASSERT(sc);
 293                 regval = EPWM_READ2(sc, EPWM_TBCTL);
 294                 regval &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
 295                 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv);
 296                 EPWM_WRITE2(sc, EPWM_TBCTL, regval);
 297                 EPWM_WRITE2(sc, EPWM_TBPRD, tbprd - 1);
 298 #if 0
 299                 device_printf(sc->sc_dev, "clkdiv %u hspclkdiv %u tbprd %u "
 300                     "clkfreq %u Hz clktick %u ns period got %u requested %u\n",
 301                     clkdiv, hspclkdiv, tbprd - 1,
 302                     sc->sc_clkfreq, sc->sc_clktick, sc->sc_period, period);
 303 #endif
 304                 /*
 305                  * If the period changed, that invalidates the current CMP
 306                  * registers (duty values), just zero them out.
 307                  */
 308                 am335x_ehrpwm_cfg_duty(sc, 0, 0);
 309                 am335x_ehrpwm_cfg_duty(sc, 1, 0);
 310         }
 311
 312         return (true);
 313 }
 314
 315 static void
 316 am335x_ehrpwm_freq(struct am335x_ehrpwm_softc *sc)
 317 {
 318         int clkdiv;
 319
 320         clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
 321         sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period;
 322 }
 323
 324 static int
 325 am335x_ehrpwm_sysctl_freq(SYSCTL_HANDLER_ARGS)
 326 {
 327         int clkdiv, error, freq, i, period;
 328         struct am335x_ehrpwm_softc *sc;
 329         uint32_t reg;
 330
 331         sc = (struct am335x_ehrpwm_softc *)arg1;
 332
 333         PWM_LOCK(sc);
 334         freq = sc->sc_pwm_freq;
 335         PWM_UNLOCK(sc);
 336
 337         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
 338         if (error != 0 || req->newptr == NULL)
 339                 return (error);
 340
 341         if (freq > PWM_CLOCK)
 342                 freq = PWM_CLOCK;
 343
 344         PWM_LOCK(sc);
 345         if (freq != sc->sc_pwm_freq) {
 346                 for (i = nitems(am335x_ehrpwm_clkdiv) - 1; i >= 0; i--) {
 347                         clkdiv = am335x_ehrpwm_clkdiv[i];
 348                         period = PWM_CLOCK / clkdiv / freq;
 349                         if (period > USHRT_MAX)
 350                                 break;
 351                         sc->sc_pwm_clkdiv = i;
 352                         sc->sc_pwm_period = period;
 353                 }
 354                 /* Reset the duty cycle settings. */
 355                 sc->sc_pwm_dutyA = 0;
 356                 sc->sc_pwm_dutyB = 0;
 357                 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
 358                 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
 359                 /* Update the clkdiv settings. */
 360                 reg = EPWM_READ2(sc, EPWM_TBCTL);
 361                 reg &= ~TBCTL_CLKDIV_MASK;
 362                 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv);
 363                 EPWM_WRITE2(sc, EPWM_TBCTL, reg);
 364                 /* Update the period settings. */
 365                 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
 366                 am335x_ehrpwm_freq(sc);
 367         }
 368         PWM_UNLOCK(sc);
 369
 370         return (0);
 371 }
 372
 373 static int
 374 am335x_ehrpwm_sysctl_clkdiv(SYSCTL_HANDLER_ARGS)
 375 {
 376         int error, i, clkdiv;
 377         struct am335x_ehrpwm_softc *sc;
 378         uint32_t reg;
 379
 380         sc = (struct am335x_ehrpwm_softc *)arg1;
 381
 382         PWM_LOCK(sc);
 383         clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
 384         PWM_UNLOCK(sc);
 385
 386         error = sysctl_handle_int(oidp, &clkdiv, sizeof(clkdiv), req);
 387         if (error != 0 || req->newptr == NULL)
 388                 return (error);
 389
 390         PWM_LOCK(sc);
 391         if (clkdiv != am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]) {
 392                 for (i = 0; i < nitems(am335x_ehrpwm_clkdiv); i++)
 393                         if (clkdiv >= am335x_ehrpwm_clkdiv[i])
 394                                 sc->sc_pwm_clkdiv = i;
 395
 396                 reg = EPWM_READ2(sc, EPWM_TBCTL);
 397                 reg &= ~TBCTL_CLKDIV_MASK;
 398                 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv);
 399                 EPWM_WRITE2(sc, EPWM_TBCTL, reg);
 400                 am335x_ehrpwm_freq(sc);
 401         }
 402         PWM_UNLOCK(sc);
 403
 404         return (0);
 405 }
 406
 407 static int
 408 am335x_ehrpwm_sysctl_duty(SYSCTL_HANDLER_ARGS)
 409 {
 410         struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1;
 411         int error;
 412         uint32_t duty;
 413
 414         if (oidp == sc->sc_chanA_oid)
 415                 duty = sc->sc_pwm_dutyA;
 416         else
 417                 duty = sc->sc_pwm_dutyB;
 418         error = sysctl_handle_int(oidp, &duty, 0, req);
 419
 420         if (error != 0 || req->newptr == NULL)
 421                 return (error);
 422
 423         if (duty > sc->sc_pwm_period) {
 424                 device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n");
 425                 return (EINVAL);
 426         }
 427
 428         PWM_LOCK(sc);
 429         if (oidp == sc->sc_chanA_oid) {
 430                 sc->sc_pwm_dutyA = duty;
 431                 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
 432         }
 433         else {
 434                 sc->sc_pwm_dutyB = duty;
 435                 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
 436         }
 437         PWM_UNLOCK(sc);
 438
 439         return (error);
 440 }
 441
 442 static int
 443 am335x_ehrpwm_sysctl_period(SYSCTL_HANDLER_ARGS)
 444 {
 445         struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1;
 446         int error;
 447         uint32_t period;
 448
 449         period = sc->sc_pwm_period;
 450         error = sysctl_handle_int(oidp, &period, 0, req);
 451
 452         if (error != 0 || req->newptr == NULL)
 453                 return (error);
 454
 455         if (period < 1)
 456                 return (EINVAL);
 457
 458         if (period > USHRT_MAX)
 459                 period = USHRT_MAX;
 460
 461         PWM_LOCK(sc);
 462         /* Reset the duty cycle settings. */
 463         sc->sc_pwm_dutyA = 0;
 464         sc->sc_pwm_dutyB = 0;
 465         EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
 466         EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
 467         /* Update the period settings. */
 468         sc->sc_pwm_period = period;
 469         EPWM_WRITE2(sc, EPWM_TBPRD, period - 1);
 470         am335x_ehrpwm_freq(sc);
 471         PWM_UNLOCK(sc);
 472
 473         return (error);
 474 }
 475
 476 static int
 477 am335x_ehrpwm_channel_count(device_t dev, u_int *nchannel)
 478 {
 479
 480         *nchannel = NUM_CHANNELS;
 481
 482         return (0);
 483 }
 484
 485 static int
 486 am335x_ehrpwm_channel_config(device_t dev, u_int channel, u_int period, u_int duty)
 487 {
 488         struct am335x_ehrpwm_softc *sc;
 489         bool status;
 490
 491         if (channel >= NUM_CHANNELS)
 492                 return (EINVAL);
 493
 494         sc = device_get_softc(dev);
 495
 496         PWM_LOCK(sc);
 497         status = am335x_ehrpwm_cfg_period(sc, period);
 498         if (status)
 499                 am335x_ehrpwm_cfg_duty(sc, channel, duty);
 500         PWM_UNLOCK(sc);
 501
 502         return (status ? 0 : EINVAL);
 503 }
 504
 505 static int
 506 am335x_ehrpwm_channel_get_config(device_t dev, u_int channel,
 507     u_int *period, u_int *duty)
 508 {
 509         struct am335x_ehrpwm_softc *sc;
 510
 511         if (channel >= NUM_CHANNELS)
 512                 return (EINVAL);
 513
 514         sc = device_get_softc(dev);
 515         *period = sc->sc_period;
 516         *duty = sc->sc_channels[channel].duty;
 517         return (0);
 518 }
 519
 520 static int
 521 am335x_ehrpwm_channel_enable(device_t dev, u_int channel, bool enable)
 522 {
 523         struct am335x_ehrpwm_softc *sc;
 524
 525         if (channel >= NUM_CHANNELS)
 526                 return (EINVAL);
 527
 528         sc = device_get_softc(dev);
 529
 530         PWM_LOCK(sc);
 531         am335x_ehrpwm_cfg_enable(sc, channel, enable);
 532         PWM_UNLOCK(sc);
 533
 534         return (0);
 535 }
 536
 537 static int
 538 am335x_ehrpwm_channel_is_enabled(device_t dev, u_int channel, bool *enabled)
 539 {
 540         struct am335x_ehrpwm_softc *sc;
 541
 542         if (channel >= NUM_CHANNELS)
 543                 return (EINVAL);
 544
 545         sc = device_get_softc(dev);
 546
 547         *enabled = sc->sc_channels[channel].enabled;
 548
 549         return (0);
 550 }
 551
 552 static int
 553 am335x_ehrpwm_probe(device_t dev)
 554 {
 555
 556         if (!ofw_bus_status_okay(dev))
 557                 return (ENXIO);
 558
 559         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
 560                 return (ENXIO);
 561
 562         device_set_desc(dev, "AM335x EHRPWM");
 563
 564         return (BUS_PROBE_DEFAULT);
 565 }
 566
 567 static int
 568 am335x_ehrpwm_attach(device_t dev)
 569 {
 570         struct am335x_ehrpwm_softc *sc;
 571         uint32_t reg;
 572         struct sysctl_ctx_list *ctx;
 573         struct sysctl_oid *tree;
 574
 575         sc = device_get_softc(dev);
 576         sc->sc_dev = dev;
 577
 578         PWM_LOCK_INIT(sc);
 579
 580         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 581             &sc->sc_mem_rid, RF_ACTIVE);
 582         if (sc->sc_mem_res == NULL) {
 583                 device_printf(dev, "cannot allocate memory resources\n");
 584                 goto fail;
 585         }
 586
 587         /* Init sysctl interface */
 588         ctx = device_get_sysctl_ctx(sc->sc_dev);
 589         tree = device_get_sysctl_tree(sc->sc_dev);
 590
 591         sc->sc_clkdiv_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 592             "clkdiv", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
 593             am335x_ehrpwm_sysctl_clkdiv, "I", "PWM clock prescaler");
 594
 595         sc->sc_freq_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 596             "freq", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
 597             am335x_ehrpwm_sysctl_freq, "I", "PWM frequency");
 598
 599         sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 600             "period", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
 601             am335x_ehrpwm_sysctl_period, "I", "PWM period");
 602
 603         sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 604             "dutyA", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
 605             am335x_ehrpwm_sysctl_duty, "I", "Channel A duty cycles");
 606
 607         sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 608             "dutyB", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
 609             am335x_ehrpwm_sysctl_duty, "I", "Channel B duty cycles");
 610
 611         /* CONFIGURE EPWM1 */
 612         reg = EPWM_READ2(sc, EPWM_TBCTL);
 613         reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
 614         EPWM_WRITE2(sc, EPWM_TBCTL, reg);
 615
 616         sc->sc_pwm_period = DEFAULT_PWM_PERIOD;
 617         sc->sc_pwm_dutyA = 0;
 618         sc->sc_pwm_dutyB = 0;
 619         am335x_ehrpwm_freq(sc);
 620
 621         EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
 622         EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
 623         EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
 624
 625         EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR));
 626         EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR));
 627
 628         /* START EPWM */
 629         reg &= ~TBCTL_CTRMODE_MASK;
 630         reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN;
 631         EPWM_WRITE2(sc, EPWM_TBCTL, reg);
 632
 633         EPWM_WRITE2(sc, EPWM_TZCTL, 0xf);
 634         reg = EPWM_READ2(sc, EPWM_TZFLG);
 635
 636         if ((sc->sc_busdev = device_add_child(dev, "pwmbus", -1)) == NULL) {
 637                 device_printf(dev, "Cannot add child pwmbus\n");
 638                 // This driver can still do things even without the bus child.
 639         }
 640
 641         bus_generic_probe(dev);
 642         return (bus_generic_attach(dev));
 643 fail:
 644         PWM_LOCK_DESTROY(sc);
 645         if (sc->sc_mem_res)
 646                 bus_release_resource(dev, SYS_RES_MEMORY,
 647                     sc->sc_mem_rid, sc->sc_mem_res);
 648
 649         return(ENXIO);
 650 }
 651
 652 static int
 653 am335x_ehrpwm_detach(device_t dev)
 654 {
 655         struct am335x_ehrpwm_softc *sc;
 656         int error;
 657
 658         sc = device_get_softc(dev);
 659
 660         if ((error = bus_generic_detach(sc->sc_dev)) != 0)
 661                 return (error);
 662
 663         PWM_LOCK(sc);
 664
 665         if (sc->sc_busdev != NULL)
 666                 device_delete_child(dev, sc->sc_busdev);
 667
 668         if (sc->sc_mem_res)
 669                 bus_release_resource(dev, SYS_RES_MEMORY,
 670                     sc->sc_mem_rid, sc->sc_mem_res);
 671
 672         PWM_UNLOCK(sc);
 673
 674         PWM_LOCK_DESTROY(sc);
 675
 676         return (0);
 677 }
 678
 679 static phandle_t
 680 am335x_ehrpwm_get_node(device_t bus, device_t dev)
 681 {
 682
 683         /*
 684          * Share our controller node with our pwmbus child; it instantiates
 685          * devices by walking the children contained within our node.
 686          */
 687         return ofw_bus_get_node(bus);
 688 }
 689
 690 static device_method_t am335x_ehrpwm_methods[] = {
 691         DEVMETHOD(device_probe,         am335x_ehrpwm_probe),
 692         DEVMETHOD(device_attach,        am335x_ehrpwm_attach),
 693         DEVMETHOD(device_detach,        am335x_ehrpwm_detach),
 694
 695         /* ofw_bus_if */
 696         DEVMETHOD(ofw_bus_get_node,     am335x_ehrpwm_get_node),
 697
 698         /* pwm interface */
 699         DEVMETHOD(pwmbus_channel_count,         am335x_ehrpwm_channel_count),
 700         DEVMETHOD(pwmbus_channel_config,        am335x_ehrpwm_channel_config),
 701         DEVMETHOD(pwmbus_channel_get_config,    am335x_ehrpwm_channel_get_config),
 702         DEVMETHOD(pwmbus_channel_enable,        am335x_ehrpwm_channel_enable),
 703         DEVMETHOD(pwmbus_channel_is_enabled,    am335x_ehrpwm_channel_is_enabled),
 704
 705         DEVMETHOD_END
 706 };
 707
 708 static driver_t am335x_ehrpwm_driver = {
 709         "pwm",
 710         am335x_ehrpwm_methods,
 711         sizeof(struct am335x_ehrpwm_softc),
 712 };
 713
 714 static devclass_t am335x_ehrpwm_devclass;
 715
 716 DRIVER_MODULE(am335x_ehrpwm, am335x_pwmss, am335x_ehrpwm_driver, am335x_ehrpwm_devclass, 0, 0);
 717 MODULE_VERSION(am335x_ehrpwm, 1);
 718 MODULE_DEPEND(am335x_ehrpwm, am335x_pwmss, 1, 1, 1);
 719 MODULE_DEPEND(am335x_ehrpwm, pwmbus, 1, 1, 1);