2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "opt_syscons.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/clock.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
44 #include <sys/sysctl.h>
48 #include <sys/consio.h>
50 #include <machine/bus.h>
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
57 #include <dev/videomode/videomode.h>
58 #include <dev/videomode/edidvar.h>
60 #include <dev/fb/fbreg.h>
62 #include <dev/syscons/syscons.h>
64 #include <dev/vt/vt.h>
67 #include <arm/ti/ti_prcm.h>
68 #include <arm/ti/ti_scm.h>
70 #include "am335x_lcd.h"
71 #include "am335x_pwm.h"
78 #define CTRL_DIV_MASK 0xff
79 #define CTRL_DIV_SHIFT 8
80 #define CTRL_AUTO_UFLOW_RESTART (1 << 1)
81 #define CTRL_RASTER_MODE 1
82 #define CTRL_LIDD_MODE 0
83 #define LCD_LIDD_CTRL 0x0C
84 #define LCD_LIDD_CS0_CONF 0x10
85 #define LCD_LIDD_CS0_ADDR 0x14
86 #define LCD_LIDD_CS0_DATA 0x18
87 #define LCD_LIDD_CS1_CONF 0x1C
88 #define LCD_LIDD_CS1_ADDR 0x20
89 #define LCD_LIDD_CS1_DATA 0x24
90 #define LCD_RASTER_CTRL 0x28
91 #define RASTER_CTRL_TFT24_UNPACKED (1 << 26)
92 #define RASTER_CTRL_TFT24 (1 << 25)
93 #define RASTER_CTRL_STN565 (1 << 24)
94 #define RASTER_CTRL_TFTPMAP (1 << 23)
95 #define RASTER_CTRL_NIBMODE (1 << 22)
96 #define RASTER_CTRL_PALMODE_SHIFT 20
97 #define PALETTE_PALETTE_AND_DATA 0x00
98 #define PALETTE_PALETTE_ONLY 0x01
99 #define PALETTE_DATA_ONLY 0x02
100 #define RASTER_CTRL_REQDLY_SHIFT 12
101 #define RASTER_CTRL_MONO8B (1 << 9)
102 #define RASTER_CTRL_RBORDER (1 << 8)
103 #define RASTER_CTRL_LCDTFT (1 << 7)
104 #define RASTER_CTRL_LCDBW (1 << 1)
105 #define RASTER_CTRL_LCDEN (1 << 0)
106 #define LCD_RASTER_TIMING_0 0x2C
107 #define RASTER_TIMING_0_HBP_SHIFT 24
108 #define RASTER_TIMING_0_HFP_SHIFT 16
109 #define RASTER_TIMING_0_HSW_SHIFT 10
110 #define RASTER_TIMING_0_PPLLSB_SHIFT 4
111 #define RASTER_TIMING_0_PPLMSB_SHIFT 3
112 #define LCD_RASTER_TIMING_1 0x30
113 #define RASTER_TIMING_1_VBP_SHIFT 24
114 #define RASTER_TIMING_1_VFP_SHIFT 16
115 #define RASTER_TIMING_1_VSW_SHIFT 10
116 #define RASTER_TIMING_1_LPP_SHIFT 0
117 #define LCD_RASTER_TIMING_2 0x34
118 #define RASTER_TIMING_2_HSWHI_SHIFT 27
119 #define RASTER_TIMING_2_LPP_B10_SHIFT 26
120 #define RASTER_TIMING_2_PHSVS (1 << 25)
121 #define RASTER_TIMING_2_PHSVS_RISE (1 << 24)
122 #define RASTER_TIMING_2_PHSVS_FALL (0 << 24)
123 #define RASTER_TIMING_2_IOE (1 << 23)
124 #define RASTER_TIMING_2_IPC (1 << 22)
125 #define RASTER_TIMING_2_IHS (1 << 21)
126 #define RASTER_TIMING_2_IVS (1 << 20)
127 #define RASTER_TIMING_2_ACBI_SHIFT 16
128 #define RASTER_TIMING_2_ACB_SHIFT 8
129 #define RASTER_TIMING_2_HBPHI_SHIFT 4
130 #define RASTER_TIMING_2_HFPHI_SHIFT 0
131 #define LCD_RASTER_SUBPANEL 0x38
132 #define LCD_RASTER_SUBPANEL2 0x3C
133 #define LCD_LCDDMA_CTRL 0x40
134 #define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16
135 #define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8
136 #define LCDDMA_CTRL_BURST_SIZE_SHIFT 4
137 #define LCDDMA_CTRL_BYTES_SWAP (1 << 3)
138 #define LCDDMA_CTRL_BE (1 << 1)
139 #define LCDDMA_CTRL_FB0_ONLY 0
140 #define LCDDMA_CTRL_FB0_FB1 (1 << 0)
141 #define LCD_LCDDMA_FB0_BASE 0x44
142 #define LCD_LCDDMA_FB0_CEILING 0x48
143 #define LCD_LCDDMA_FB1_BASE 0x4C
144 #define LCD_LCDDMA_FB1_CEILING 0x50
145 #define LCD_SYSCONFIG 0x54
146 #define SYSCONFIG_STANDBY_FORCE (0 << 4)
147 #define SYSCONFIG_STANDBY_NONE (1 << 4)
148 #define SYSCONFIG_STANDBY_SMART (2 << 4)
149 #define SYSCONFIG_IDLE_FORCE (0 << 2)
150 #define SYSCONFIG_IDLE_NONE (1 << 2)
151 #define SYSCONFIG_IDLE_SMART (2 << 2)
152 #define LCD_IRQSTATUS_RAW 0x58
153 #define LCD_IRQSTATUS 0x5C
154 #define LCD_IRQENABLE_SET 0x60
155 #define LCD_IRQENABLE_CLEAR 0x64
156 #define IRQ_EOF1 (1 << 9)
157 #define IRQ_EOF0 (1 << 8)
158 #define IRQ_PL (1 << 6)
159 #define IRQ_FUF (1 << 5)
160 #define IRQ_ACB (1 << 3)
161 #define IRQ_SYNC_LOST (1 << 2)
162 #define IRQ_RASTER_DONE (1 << 1)
163 #define IRQ_FRAME_DONE (1 << 0)
164 #define LCD_END_OF_INT_IND 0x68
165 #define LCD_CLKC_ENABLE 0x6C
166 #define CLKC_ENABLE_DMA (1 << 2)
167 #define CLKC_ENABLE_LDID (1 << 1)
168 #define CLKC_ENABLE_CORE (1 << 0)
169 #define LCD_CLKC_RESET 0x70
170 #define CLKC_RESET_MAIN (1 << 3)
171 #define CLKC_RESET_DMA (1 << 2)
172 #define CLKC_RESET_LDID (1 << 1)
173 #define CLKC_RESET_CORE (1 << 0)
175 #define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
176 #define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
177 #define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
178 device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF)
179 #define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx);
181 #define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);
182 #define LCD_WRITE4(_sc, reg, value) \
183 bus_write_4((_sc)->sc_mem_res, reg, value);
185 /* Backlight is controlled by eCAS interface on PWM unit 0 */
187 #define PWM_PERIOD 100
189 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end)
190 #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay)
191 #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start)
192 #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end)
193 #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay)
194 #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start)
196 #define MAX_PIXEL_CLOCK 126000
197 #define MAX_BANDWIDTH (1280*1024*60)
199 struct am335x_lcd_softc {
201 struct fb_info sc_fb_info;
202 struct resource *sc_mem_res;
203 struct resource *sc_irq_res;
207 struct sysctl_oid *sc_oid;
209 struct panel_info sc_panel;
212 bus_dma_tag_t sc_dma_tag;
213 bus_dmamap_t sc_dma_map;
215 bus_addr_t sc_fb_phys;
219 phandle_t sc_hdmi_framer;
220 eventhandler_tag sc_hdmi_evh;
224 am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
231 addr = (bus_addr_t*)arg;
232 *addr = segs[0].ds_addr;
236 am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq)
239 uint32_t delta, min_delta;
244 /* Raster mode case: divisors are in range from 2 to 255 */
245 for (i = 2; i < 255; i++) {
246 delta = abs(reference/i - freq);
247 if (delta < min_delta) {
257 am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS)
259 struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1;
263 backlight = sc->sc_backlight;
264 error = sysctl_handle_int(oidp, &backlight, 0, req);
266 if (error != 0 || req->newptr == NULL)
275 error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD,
276 backlight*PWM_PERIOD/100);
278 sc->sc_backlight = backlight;
285 am335x_mode_vrefresh(const struct videomode *mode)
289 /* Calculate vertical refresh rate */
290 refresh = (mode->dot_clock * 1000 / mode->htotal);
291 refresh = (refresh + mode->vtotal / 2) / mode->vtotal;
293 if (mode->flags & VID_INTERLACE)
295 if (mode->flags & VID_DBLSCAN)
302 am335x_mode_is_valid(const struct videomode *mode)
304 uint32_t hbp, hfp, hsw;
305 uint32_t vbp, vfp, vsw;
307 if (mode->dot_clock > MAX_PIXEL_CLOCK)
310 if (mode->hdisplay & 0xf)
313 if (mode->vdisplay > 2048)
316 /* Check ranges for timing parameters */
317 hbp = MODE_HBP(mode) - 1;
318 hfp = MODE_HFP(mode) - 1;
319 hsw = MODE_HSW(mode) - 1;
320 vbp = MODE_VBP(mode);
321 vfp = MODE_VFP(mode);
322 vsw = MODE_VSW(mode) - 1;
337 if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode)
345 am335x_read_hdmi_property(device_t dev)
347 phandle_t node, xref;
350 struct am335x_lcd_softc *sc;
352 sc = device_get_softc(dev);
353 node = ofw_bus_get_node(dev);
354 sc->sc_hdmi_framer = 0;
357 * Old FreeBSD way of referencing to HDMI framer
359 if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) != -1) {
360 sc->sc_hdmi_framer = hdmi_xref;
365 * Use bindings described in Linux docs:
366 * bindings/media/video-interfaces.txt
367 * We assume that the only endpoint in LCDC node
370 node = ofw_bus_find_child(node, "port");
372 /* No media bindings */
376 for (endpoint = OF_child(node); endpoint != 0; endpoint = OF_peer(endpoint)) {
377 if (OF_getencprop(endpoint, "remote-endpoint", &xref, sizeof(xref)) != -1) {
378 /* port/port@0/endpoint@0 */
379 node = OF_node_from_xref(xref);
381 node = OF_parent(node);
383 node = OF_parent(node);
384 /* actual owner of port, in our case HDMI framer */
385 sc->sc_hdmi_framer = OF_xref_from_node(OF_parent(node));
386 if (sc->sc_hdmi_framer != 0)
393 am335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val)
397 if ((OF_getencprop(node, name, &cell, sizeof(cell))) <= 0) {
398 device_printf(dev, "missing '%s' attribute in LCD panel info\n",
409 am335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel)
412 phandle_t timings_node, timing_node, native;
414 timings_node = ofw_bus_find_child(node, "display-timings");
415 if (timings_node == 0) {
416 device_printf(dev, "no \"display-timings\" node\n");
420 if (OF_searchencprop(timings_node, "native-mode", &native,
421 sizeof(native)) == -1) {
422 device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n");
426 timing_node = OF_node_from_xref(native);
429 if ((error = am335x_read_property(dev, timing_node,
430 "hactive", &panel->panel_width)))
433 if ((error = am335x_read_property(dev, timing_node,
434 "vactive", &panel->panel_height)))
437 if ((error = am335x_read_property(dev, timing_node,
438 "hfront-porch", &panel->panel_hfp)))
441 if ((error = am335x_read_property(dev, timing_node,
442 "hback-porch", &panel->panel_hbp)))
445 if ((error = am335x_read_property(dev, timing_node,
446 "hsync-len", &panel->panel_hsw)))
449 if ((error = am335x_read_property(dev, timing_node,
450 "vfront-porch", &panel->panel_vfp)))
453 if ((error = am335x_read_property(dev, timing_node,
454 "vback-porch", &panel->panel_vbp)))
457 if ((error = am335x_read_property(dev, timing_node,
458 "vsync-len", &panel->panel_vsw)))
461 if ((error = am335x_read_property(dev, timing_node,
462 "clock-frequency", &panel->panel_pxl_clk)))
465 if ((error = am335x_read_property(dev, timing_node,
466 "pixelclk-active", &panel->pixelclk_active)))
469 if ((error = am335x_read_property(dev, timing_node,
470 "hsync-active", &panel->hsync_active)))
473 if ((error = am335x_read_property(dev, timing_node,
474 "vsync-active", &panel->vsync_active)))
482 am335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel)
484 phandle_t panel_info_node;
486 panel_info_node = ofw_bus_find_child(node, "panel-info");
487 if (panel_info_node == 0)
490 am335x_read_property(dev, panel_info_node,
491 "ac-bias", &panel->ac_bias);
493 am335x_read_property(dev, panel_info_node,
494 "ac-bias-intrpt", &panel->ac_bias_intrpt);
496 am335x_read_property(dev, panel_info_node,
497 "dma-burst-sz", &panel->dma_burst_sz);
499 am335x_read_property(dev, panel_info_node,
502 am335x_read_property(dev, panel_info_node,
505 am335x_read_property(dev, panel_info_node,
506 "sync-edge", &panel->sync_edge);
508 am335x_read_property(dev, panel_info_node,
509 "sync-ctrl", &panel->sync_ctrl);
515 am335x_lcd_intr(void *arg)
517 struct am335x_lcd_softc *sc = arg;
520 reg = LCD_READ4(sc, LCD_IRQSTATUS);
521 LCD_WRITE4(sc, LCD_IRQSTATUS, reg);
522 /* Read value back to make sure it reached the hardware */
523 reg = LCD_READ4(sc, LCD_IRQSTATUS);
525 if (reg & IRQ_SYNC_LOST) {
526 reg = LCD_READ4(sc, LCD_RASTER_CTRL);
527 reg &= ~RASTER_CTRL_LCDEN;
528 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);
530 reg = LCD_READ4(sc, LCD_RASTER_CTRL);
531 reg |= RASTER_CTRL_LCDEN;
532 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);
537 reg = LCD_READ4(sc, LCD_RASTER_CTRL);
538 reg &= ~RASTER_CTRL_LCDEN;
539 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);
541 reg = LCD_READ4(sc, LCD_RASTER_CTRL);
542 reg |= RASTER_CTRL_LCDEN;
543 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);
547 if (reg & IRQ_EOF0) {
548 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys);
549 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1);
553 if (reg & IRQ_EOF1) {
554 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys);
555 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1);
560 /* TODO: Handle FUF */
564 /* TODO: Handle ACB */
568 LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0);
569 /* Read value back to make sure it reached the hardware */
570 reg = LCD_READ4(sc, LCD_END_OF_INT_IND);
573 static const struct videomode *
574 am335x_lcd_pick_mode(struct edid_info *ei)
576 const struct videomode *videomode;
577 const struct videomode *m;
580 /* Get standard VGA as default */
586 if (ei->edid_preferred_mode != NULL) {
587 if (am335x_mode_is_valid(ei->edid_preferred_mode))
588 videomode = ei->edid_preferred_mode;
591 if (videomode == NULL) {
594 sort_modes(ei->edid_modes,
595 &ei->edid_preferred_mode,
597 for (n = 0; n < ei->edid_nmodes; n++)
598 if (am335x_mode_is_valid(&m[n])) {
608 am335x_lcd_configure(struct am335x_lcd_softc *sc)
611 uint32_t reg, timing0, timing1, timing2;
614 uint32_t hbp, hfp, hsw;
615 uint32_t vbp, vfp, vsw;
616 uint32_t width, height;
617 unsigned int ref_freq;
621 * try to adjust clock to get double of requested frequency
622 * HDMI/DVI displays are very sensitive to error in frequncy value
624 if (ti_prcm_clk_set_source_freq(LCDC_CLK, sc->sc_panel.panel_pxl_clk*2)) {
625 device_printf(sc->sc_dev, "can't set source frequency\n");
629 if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) {
630 device_printf(sc->sc_dev, "can't get reference frequency\n");
634 /* Panle initialization */
635 dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8);
638 * Now allocate framebuffer memory
640 err = bus_dma_tag_create(
641 bus_get_dma_tag(sc->sc_dev),
642 4, 0, /* alignment, boundary */
643 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
644 BUS_SPACE_MAXADDR, /* highaddr */
645 NULL, NULL, /* filter, filterarg */
646 dma_size, 1, /* maxsize, nsegments */
647 dma_size, 0, /* maxsegsize, flags */
648 NULL, NULL, /* lockfunc, lockarg */
653 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base,
654 BUS_DMA_COHERENT, &sc->sc_dma_map);
657 device_printf(sc->sc_dev, "cannot allocate framebuffer\n");
661 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base,
662 dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT);
665 device_printf(sc->sc_dev, "cannot load DMA map\n");
669 /* Make sure it's blank */
670 memset(sc->sc_fb_base, 0x0, dma_size);
672 /* Calculate actual FB Size */
673 sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8;
675 /* Only raster mode is supported */
676 reg = CTRL_RASTER_MODE;
677 div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk);
678 reg |= (div << CTRL_DIV_SHIFT);
679 LCD_WRITE4(sc, LCD_CTRL, reg);
682 timing0 = timing1 = timing2 = 0;
684 hbp = sc->sc_panel.panel_hbp - 1;
685 hfp = sc->sc_panel.panel_hfp - 1;
686 hsw = sc->sc_panel.panel_hsw - 1;
688 vbp = sc->sc_panel.panel_vbp;
689 vfp = sc->sc_panel.panel_vfp;
690 vsw = sc->sc_panel.panel_vsw - 1;
692 height = sc->sc_panel.panel_height - 1;
693 width = sc->sc_panel.panel_width - 1;
695 /* Horizontal back porch */
696 timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT;
697 timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT;
698 /* Horizontal front porch */
699 timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT;
700 timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT;
701 /* Horizontal sync width */
702 timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT;
703 timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT;
705 /* Vertical back porch, front porch, sync width */
706 timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT;
707 timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT;
708 timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT;
710 /* Pixels per line */
711 timing0 |= ((width >> 10) & 1)
712 << RASTER_TIMING_0_PPLMSB_SHIFT;
713 timing0 |= ((width >> 4) & 0x3f)
714 << RASTER_TIMING_0_PPLLSB_SHIFT;
716 /* Lines per panel */
717 timing1 |= (height & 0x3ff)
718 << RASTER_TIMING_1_LPP_SHIFT;
719 timing2 |= ((height >> 10 ) & 1)
720 << RASTER_TIMING_2_LPP_B10_SHIFT;
722 /* clock signal settings */
723 if (sc->sc_panel.sync_ctrl)
724 timing2 |= RASTER_TIMING_2_PHSVS;
725 if (sc->sc_panel.sync_edge)
726 timing2 |= RASTER_TIMING_2_PHSVS_RISE;
728 timing2 |= RASTER_TIMING_2_PHSVS_FALL;
729 if (sc->sc_panel.hsync_active == 0)
730 timing2 |= RASTER_TIMING_2_IHS;
731 if (sc->sc_panel.vsync_active == 0)
732 timing2 |= RASTER_TIMING_2_IVS;
733 if (sc->sc_panel.pixelclk_active == 0)
734 timing2 |= RASTER_TIMING_2_IPC;
737 timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT);
738 timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT);
740 LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0);
741 LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1);
742 LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2);
745 reg = LCDDMA_CTRL_FB0_FB1;
746 /* Find power of 2 for current burst size */
747 switch (sc->sc_panel.dma_burst_sz) {
765 reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT);
767 reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT);
768 LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg);
770 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys);
771 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1);
772 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys);
773 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1);
776 reg = RASTER_CTRL_LCDTFT;
777 reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT);
778 reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT);
779 if (sc->sc_panel.bpp >= 24)
780 reg |= RASTER_CTRL_TFT24;
781 if (sc->sc_panel.bpp == 32)
782 reg |= RASTER_CTRL_TFT24_UNPACKED;
783 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);
785 LCD_WRITE4(sc, LCD_CLKC_ENABLE,
786 CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE);
788 LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN);
790 LCD_WRITE4(sc, LCD_CLKC_RESET, 0);
792 reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL |
793 IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE |
795 LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg);
797 reg = LCD_READ4(sc, LCD_RASTER_CTRL);
798 reg |= RASTER_CTRL_LCDEN;
799 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);
801 LCD_WRITE4(sc, LCD_SYSCONFIG,
802 SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART);
804 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev);
805 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base;
806 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys;
807 sc->sc_fb_info.fb_size = sc->sc_fb_size;
808 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp;
809 sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8;
810 sc->sc_fb_info.fb_width = sc->sc_panel.panel_width;
811 sc->sc_fb_info.fb_height = sc->sc_panel.panel_height;
814 err = (sc_attach_unit(device_get_unit(sc->sc_dev),
815 device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD));
818 device_printf(sc->sc_dev, "failed to attach syscons\n");
822 am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel);
824 device_t fbd = device_add_child(sc->sc_dev, "fbd",
825 device_get_unit(sc->sc_dev));
827 if (device_probe_and_attach(fbd) != 0)
828 device_printf(sc->sc_dev, "failed to attach fbd device\n");
830 device_printf(sc->sc_dev, "failed to add fbd child\n");
838 am335x_lcd_hdmi_event(void *arg, device_t hdmi, int event)
840 struct am335x_lcd_softc *sc;
841 const struct videomode *videomode;
842 struct videomode hdmi_mode;
850 /* Nothing to work with */
851 if (!sc->sc_hdmi_framer) {
852 device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n");
856 hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer);
858 device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n");
864 if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) {
865 device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n");
871 if (edid_parse(edid, &ei) == 0) {
873 videomode = am335x_lcd_pick_mode(&ei);
875 device_printf(sc->sc_dev, "failed to parse EDID\n");
877 /* Use standard VGA as fallback */
878 if (videomode == NULL)
879 videomode = pick_mode_by_ref(640, 480, 60);
881 if (videomode == NULL) {
882 device_printf(sc->sc_dev, "failed to find usable videomode");
886 device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay,
887 videomode->vdisplay, am335x_mode_vrefresh(videomode));
889 sc->sc_panel.panel_width = videomode->hdisplay;
890 sc->sc_panel.panel_height = videomode->vdisplay;
891 sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay;
892 sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end;
893 sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start;
894 sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay;
895 sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end;
896 sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start;
897 sc->sc_panel.pixelclk_active = 1;
899 /* logic for HSYNC should be reversed */
900 if (videomode->flags & VID_NHSYNC)
901 sc->sc_panel.hsync_active = 1;
903 sc->sc_panel.hsync_active = 0;
905 if (videomode->flags & VID_NVSYNC)
906 sc->sc_panel.vsync_active = 0;
908 sc->sc_panel.vsync_active = 1;
910 sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000;
912 am335x_lcd_configure(sc);
914 memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode));
915 hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start;
916 hdmi_mode.flags |= VID_HSKEW;
918 HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode);
922 am335x_lcd_probe(device_t dev)
928 if (!ofw_bus_status_okay(dev))
931 if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc"))
934 device_set_desc(dev, "AM335x LCD controller");
937 err = sc_probe_unit(device_get_unit(dev),
938 device_get_flags(dev) | SC_AUTODETECT_KBD);
943 return (BUS_PROBE_DEFAULT);
947 am335x_lcd_attach(device_t dev)
949 struct am335x_lcd_softc *sc;
953 struct sysctl_ctx_list *ctx;
954 struct sysctl_oid *tree;
955 phandle_t root, panel_node;
958 sc = device_get_softc(dev);
961 am335x_read_hdmi_property(dev);
963 root = OF_finddevice("/");
965 device_printf(dev, "failed to get FDT root node\n");
969 sc->sc_panel.ac_bias = 255;
970 sc->sc_panel.ac_bias_intrpt = 0;
971 sc->sc_panel.dma_burst_sz = 16;
972 sc->sc_panel.bpp = 16;
973 sc->sc_panel.fdd = 128;
974 sc->sc_panel.sync_edge = 0;
975 sc->sc_panel.sync_ctrl = 1;
977 panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1);
978 if (panel_node != 0) {
979 device_printf(dev, "using static panel info\n");
980 if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) {
981 device_printf(dev, "failed to read panel info\n");
985 if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) {
986 device_printf(dev, "failed to read timings\n");
991 ti_prcm_clk_enable(LCDC_CLK);
994 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
996 if (!sc->sc_mem_res) {
997 device_printf(dev, "cannot allocate memory window\n");
1002 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1004 if (!sc->sc_irq_res) {
1005 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
1006 device_printf(dev, "cannot allocate interrupt\n");
1010 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
1011 NULL, am335x_lcd_intr, sc,
1012 &sc->sc_intr_hl) != 0) {
1013 bus_release_resource(dev, SYS_RES_IRQ, rid,
1015 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1017 device_printf(dev, "Unable to setup the irq handler.\n");
1023 /* Init backlight interface */
1024 ctx = device_get_sysctl_ctx(sc->sc_dev);
1025 tree = device_get_sysctl_tree(sc->sc_dev);
1026 sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
1027 "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
1028 am335x_lcd_sysctl_backlight, "I", "LCD backlight");
1029 sc->sc_backlight = 0;
1030 /* Check if eCAS interface is available at this point */
1031 if (am335x_pwm_config_ecap(PWM_UNIT,
1032 PWM_PERIOD, PWM_PERIOD) == 0)
1033 sc->sc_backlight = 100;
1035 if (panel_node != 0)
1036 am335x_lcd_configure(sc);
1038 sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event,
1039 am335x_lcd_hdmi_event, sc, EVENTHANDLER_PRI_ANY);
1045 am335x_lcd_detach(device_t dev)
1047 /* Do not let unload driver */
1051 static struct fb_info *
1052 am335x_lcd_fb_getinfo(device_t dev)
1054 struct am335x_lcd_softc *sc;
1056 sc = device_get_softc(dev);
1058 return (&sc->sc_fb_info);
1061 static device_method_t am335x_lcd_methods[] = {
1062 DEVMETHOD(device_probe, am335x_lcd_probe),
1063 DEVMETHOD(device_attach, am335x_lcd_attach),
1064 DEVMETHOD(device_detach, am335x_lcd_detach),
1066 /* Framebuffer service methods */
1067 DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo),
1072 static driver_t am335x_lcd_driver = {
1075 sizeof(struct am335x_lcd_softc),
1078 static devclass_t am335x_lcd_devclass;
1080 DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0);
1081 MODULE_VERSION(am335x_lcd, 1);
1082 MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1);