2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
39 #include <sys/timeet.h>
40 #include <sys/timetc.h>
41 #include <sys/watchdog.h>
42 #include <machine/bus.h>
43 #include <machine/cpu.h>
44 #include <machine/intr.h>
46 #include <arm/ti/tivar.h>
47 #include <arm/ti/ti_scm.h>
48 #include <arm/ti/ti_prcm.h>
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <machine/bus.h>
56 #include "am335x_scm.h"
59 #define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x000)
60 #define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x004)
61 #define CM_PER_L3_CLKSTCTRL (CM_PER + 0x00C)
62 #define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x014)
63 #define CM_PER_LCDC_CLKCTRL (CM_PER + 0x018)
64 #define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C)
65 #define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024)
66 #define CM_PER_UART5_CLKCTRL (CM_PER + 0x038)
67 #define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C)
68 #define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044)
69 #define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048)
70 #define CM_PER_SPI0_CLKCTRL (CM_PER + 0x04C)
71 #define CM_PER_SPI1_CLKCTRL (CM_PER + 0x050)
72 #define CM_PER_UART1_CLKCTRL (CM_PER + 0x06C)
73 #define CM_PER_UART2_CLKCTRL (CM_PER + 0x070)
74 #define CM_PER_UART3_CLKCTRL (CM_PER + 0x074)
75 #define CM_PER_UART4_CLKCTRL (CM_PER + 0x078)
76 #define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C)
77 #define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080)
78 #define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084)
79 #define CM_PER_TIMER4_CLKCTRL (CM_PER + 0x088)
80 #define CM_PER_GPIO1_CLKCTRL (CM_PER + 0x0AC)
81 #define CM_PER_GPIO2_CLKCTRL (CM_PER + 0x0B0)
82 #define CM_PER_GPIO3_CLKCTRL (CM_PER + 0x0B4)
83 #define CM_PER_TPCC_CLKCTRL (CM_PER + 0x0BC)
84 #define CM_PER_EPWMSS1_CLKCTRL (CM_PER + 0x0CC)
85 #define CM_PER_EPWMSS0_CLKCTRL (CM_PER + 0x0D4)
86 #define CM_PER_EPWMSS2_CLKCTRL (CM_PER + 0x0D8)
87 #define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0x0DC)
88 #define CM_PER_L3_CLKCTRL (CM_PER + 0x0E0)
89 #define CM_PER_PRUSS_CLKCTRL (CM_PER + 0x0E8)
90 #define CM_PER_TIMER5_CLKCTRL (CM_PER + 0x0EC)
91 #define CM_PER_TIMER6_CLKCTRL (CM_PER + 0x0F0)
92 #define CM_PER_MMC1_CLKCTRL (CM_PER + 0x0F4)
93 #define CM_PER_MMC2_CLKCTRL (CM_PER + 0x0F8)
94 #define CM_PER_TPTC1_CLKCTRL (CM_PER + 0x0FC)
95 #define CM_PER_TPTC2_CLKCTRL (CM_PER + 0x100)
96 #define CM_PER_SPINLOCK0_CLKCTRL (CM_PER + 0x10C)
97 #define CM_PER_MAILBOX0_CLKCTRL (CM_PER + 0x110)
98 #define CM_PER_OCPWP_L3_CLKSTCTRL (CM_PER + 0x12C)
99 #define CM_PER_OCPWP_CLKCTRL (CM_PER + 0x130)
100 #define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144)
101 #define CM_PER_PRUSS_CLKSTCTRL (CM_PER + 0x140)
103 #define CM_WKUP 0x400
104 #define CM_WKUP_CLKSTCTRL (CM_WKUP + 0x000)
105 #define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x004)
106 #define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x008)
107 #define CM_WKUP_CM_L3_AON_CLKSTCTRL (CM_WKUP + 0x01C)
108 #define CM_WKUP_CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x02C)
109 #define CM_WKUP_CM_IDLEST_DPLL_DISP (CM_WKUP + 0x048)
110 #define CM_WKUP_CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x054)
111 #define CM_WKUP_CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x07C)
112 #define CM_WKUP_CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x098)
113 #define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0x0B8)
114 #define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0x0BC)
116 #define CM_DPLL 0x500
117 #define CLKSEL_TIMER7_CLK (CM_DPLL + 0x004)
118 #define CLKSEL_TIMER2_CLK (CM_DPLL + 0x008)
119 #define CLKSEL_TIMER3_CLK (CM_DPLL + 0x00C)
120 #define CLKSEL_TIMER4_CLK (CM_DPLL + 0x010)
121 #define CLKSEL_TIMER5_CLK (CM_DPLL + 0x018)
122 #define CLKSEL_TIMER6_CLK (CM_DPLL + 0x01C)
123 #define CLKSEL_PRUSS_OCP_CLK (CM_DPLL + 0x030)
126 #define CM_RTC_RTC_CLKCTRL (CM_RTC + 0x000)
127 #define CM_RTC_CLKSTCTRL (CM_RTC + 0x004)
129 #define PRM_PER 0xC00
130 #define PRM_PER_RSTCTRL (PRM_PER + 0x00)
132 #define PRM_DEVICE_OFFSET 0xF00
133 #define PRM_RSTCTRL (PRM_DEVICE_OFFSET + 0x00)
135 struct am335x_prcm_softc {
136 struct resource * res[2];
138 bus_space_handle_t bsh;
141 static struct resource_spec am335x_prcm_spec[] = {
142 { SYS_RES_MEMORY, 0, RF_ACTIVE },
146 static struct am335x_prcm_softc *am335x_prcm_sc = NULL;
148 static int am335x_clk_noop_activate(struct ti_clock_dev *clkdev);
149 static int am335x_clk_generic_activate(struct ti_clock_dev *clkdev);
150 static int am335x_clk_gpio_activate(struct ti_clock_dev *clkdev);
151 static int am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev);
152 static int am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev);
153 static int am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
154 static int am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
155 static int am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
156 static int am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
157 static int am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
158 static int am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
159 static int am335x_clk_set_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int freq);
160 static void am335x_prcm_reset(void);
161 static int am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev);
162 static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev);
163 static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev);
164 static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev);
166 #define AM335X_NOOP_CLOCK_DEV(i) \
168 .clk_activate = am335x_clk_noop_activate, \
169 .clk_deactivate = am335x_clk_noop_deactivate, \
170 .clk_set_source = am335x_clk_noop_set_source, \
171 .clk_accessible = NULL, \
172 .clk_get_source_freq = NULL, \
173 .clk_set_source_freq = NULL \
176 #define AM335X_GENERIC_CLOCK_DEV(i) \
178 .clk_activate = am335x_clk_generic_activate, \
179 .clk_deactivate = am335x_clk_generic_deactivate, \
180 .clk_set_source = am335x_clk_generic_set_source, \
181 .clk_accessible = NULL, \
182 .clk_get_source_freq = NULL, \
183 .clk_set_source_freq = NULL \
186 #define AM335X_GPIO_CLOCK_DEV(i) \
188 .clk_activate = am335x_clk_gpio_activate, \
189 .clk_deactivate = am335x_clk_generic_deactivate, \
190 .clk_set_source = am335x_clk_generic_set_source, \
191 .clk_accessible = NULL, \
192 .clk_get_source_freq = NULL, \
193 .clk_set_source_freq = NULL \
196 #define AM335X_MMCHS_CLOCK_DEV(i) \
198 .clk_activate = am335x_clk_generic_activate, \
199 .clk_deactivate = am335x_clk_generic_deactivate, \
200 .clk_set_source = am335x_clk_generic_set_source, \
201 .clk_accessible = NULL, \
202 .clk_get_source_freq = am335x_clk_hsmmc_get_source_freq, \
203 .clk_set_source_freq = NULL \
206 struct ti_clock_dev ti_am335x_clk_devmap[] = {
209 .clk_activate = NULL,
210 .clk_deactivate = NULL,
211 .clk_set_source = NULL,
212 .clk_accessible = NULL,
213 .clk_get_source_freq = am335x_clk_get_sysclk_freq,
214 .clk_set_source_freq = NULL,
216 /* MPU (ARM) core clocks */
218 .clk_activate = NULL,
219 .clk_deactivate = NULL,
220 .clk_set_source = NULL,
221 .clk_accessible = NULL,
222 .clk_get_source_freq = am335x_clk_get_arm_fclk_freq,
223 .clk_set_source_freq = NULL,
225 /* CPSW Ethernet Switch core clocks */
227 .clk_activate = am335x_clk_cpsw_activate,
228 .clk_deactivate = NULL,
229 .clk_set_source = NULL,
230 .clk_accessible = NULL,
231 .clk_get_source_freq = NULL,
232 .clk_set_source_freq = NULL,
235 /* Mentor USB HS controller core clocks */
237 .clk_activate = am335x_clk_musb0_activate,
238 .clk_deactivate = NULL,
239 .clk_set_source = NULL,
240 .clk_accessible = NULL,
241 .clk_get_source_freq = NULL,
242 .clk_set_source_freq = NULL,
245 /* LCD controller clocks */
247 .clk_activate = am335x_clk_lcdc_activate,
248 .clk_deactivate = NULL,
249 .clk_set_source = NULL,
250 .clk_accessible = NULL,
251 .clk_get_source_freq = am335x_clk_get_arm_disp_freq,
252 .clk_set_source_freq = am335x_clk_set_arm_disp_freq,
256 AM335X_NOOP_CLOCK_DEV(UART1_CLK),
257 AM335X_GENERIC_CLOCK_DEV(UART2_CLK),
258 AM335X_GENERIC_CLOCK_DEV(UART3_CLK),
259 AM335X_GENERIC_CLOCK_DEV(UART4_CLK),
260 AM335X_GENERIC_CLOCK_DEV(UART5_CLK),
261 AM335X_GENERIC_CLOCK_DEV(UART6_CLK),
264 AM335X_GENERIC_CLOCK_DEV(TIMER2_CLK),
265 AM335X_GENERIC_CLOCK_DEV(TIMER3_CLK),
266 AM335X_GENERIC_CLOCK_DEV(TIMER4_CLK),
267 AM335X_GENERIC_CLOCK_DEV(TIMER5_CLK),
268 AM335X_GENERIC_CLOCK_DEV(TIMER6_CLK),
269 AM335X_GENERIC_CLOCK_DEV(TIMER7_CLK),
271 /* GPIO, we use hwmods as reference, not units in spec */
272 AM335X_GPIO_CLOCK_DEV(GPIO1_CLK),
273 AM335X_GPIO_CLOCK_DEV(GPIO2_CLK),
274 AM335X_GPIO_CLOCK_DEV(GPIO3_CLK),
275 AM335X_GPIO_CLOCK_DEV(GPIO4_CLK),
277 /* I2C we use hwmods as reference, not units in spec */
278 AM335X_GENERIC_CLOCK_DEV(I2C1_CLK),
279 AM335X_GENERIC_CLOCK_DEV(I2C2_CLK),
280 AM335X_GENERIC_CLOCK_DEV(I2C3_CLK),
282 /* McSPI we use hwmods as reference, not units in spec */
283 AM335X_GENERIC_CLOCK_DEV(SPI0_CLK),
284 AM335X_GENERIC_CLOCK_DEV(SPI1_CLK),
287 AM335X_GENERIC_CLOCK_DEV(TSC_ADC_CLK),
290 AM335X_GENERIC_CLOCK_DEV(EDMA_TPCC_CLK),
291 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC0_CLK),
292 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC1_CLK),
293 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC2_CLK),
296 AM335X_MMCHS_CLOCK_DEV(MMC1_CLK),
297 AM335X_MMCHS_CLOCK_DEV(MMC2_CLK),
298 AM335X_MMCHS_CLOCK_DEV(MMC3_CLK),
301 AM335X_GENERIC_CLOCK_DEV(PWMSS0_CLK),
302 AM335X_GENERIC_CLOCK_DEV(PWMSS1_CLK),
303 AM335X_GENERIC_CLOCK_DEV(PWMSS2_CLK),
305 /* System Mailbox clock */
306 AM335X_GENERIC_CLOCK_DEV(MAILBOX0_CLK),
309 AM335X_GENERIC_CLOCK_DEV(SPINLOCK0_CLK),
313 .clk_activate = am335x_clk_pruss_activate,
314 .clk_deactivate = NULL,
315 .clk_set_source = NULL,
316 .clk_accessible = NULL,
317 .clk_get_source_freq = NULL,
318 .clk_set_source_freq = NULL,
322 AM335X_GENERIC_CLOCK_DEV(RTC_CLK),
324 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL }
327 struct am335x_clk_details {
329 uint32_t clkctrl_reg;
333 #define _CLK_DETAIL(i, c, s) \
335 .clkctrl_reg = (c), \
339 static struct am335x_clk_details g_am335x_clk_details[] = {
341 /* UART. UART0 clock not controllable. */
342 _CLK_DETAIL(UART1_CLK, 0, 0),
343 _CLK_DETAIL(UART2_CLK, CM_PER_UART1_CLKCTRL, 0),
344 _CLK_DETAIL(UART3_CLK, CM_PER_UART2_CLKCTRL, 0),
345 _CLK_DETAIL(UART4_CLK, CM_PER_UART3_CLKCTRL, 0),
346 _CLK_DETAIL(UART5_CLK, CM_PER_UART4_CLKCTRL, 0),
347 _CLK_DETAIL(UART6_CLK, CM_PER_UART5_CLKCTRL, 0),
349 /* DMTimer modules */
350 _CLK_DETAIL(TIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK),
351 _CLK_DETAIL(TIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK),
352 _CLK_DETAIL(TIMER4_CLK, CM_PER_TIMER4_CLKCTRL, CLKSEL_TIMER4_CLK),
353 _CLK_DETAIL(TIMER5_CLK, CM_PER_TIMER5_CLKCTRL, CLKSEL_TIMER5_CLK),
354 _CLK_DETAIL(TIMER6_CLK, CM_PER_TIMER6_CLKCTRL, CLKSEL_TIMER6_CLK),
355 _CLK_DETAIL(TIMER7_CLK, CM_PER_TIMER7_CLKCTRL, CLKSEL_TIMER7_CLK),
357 /* GPIO modules, hwmods start with gpio1 */
358 _CLK_DETAIL(GPIO1_CLK, CM_WKUP_GPIO0_CLKCTRL, 0),
359 _CLK_DETAIL(GPIO2_CLK, CM_PER_GPIO1_CLKCTRL, 0),
360 _CLK_DETAIL(GPIO3_CLK, CM_PER_GPIO2_CLKCTRL, 0),
361 _CLK_DETAIL(GPIO4_CLK, CM_PER_GPIO3_CLKCTRL, 0),
363 /* I2C modules, hwmods start with i2c1 */
364 _CLK_DETAIL(I2C1_CLK, CM_WKUP_I2C0_CLKCTRL, 0),
365 _CLK_DETAIL(I2C2_CLK, CM_PER_I2C1_CLKCTRL, 0),
366 _CLK_DETAIL(I2C3_CLK, CM_PER_I2C2_CLKCTRL, 0),
368 /* McSPI modules, hwmods start with spi0 */
369 _CLK_DETAIL(SPI0_CLK, CM_PER_SPI0_CLKCTRL, 0),
370 _CLK_DETAIL(SPI1_CLK, CM_PER_SPI1_CLKCTRL, 0),
373 _CLK_DETAIL(TSC_ADC_CLK, CM_WKUP_ADC_TSC_CLKCTRL, 0),
376 _CLK_DETAIL(EDMA_TPCC_CLK, CM_PER_TPCC_CLKCTRL, 0),
377 _CLK_DETAIL(EDMA_TPTC0_CLK, CM_PER_TPTC0_CLKCTRL, 0),
378 _CLK_DETAIL(EDMA_TPTC1_CLK, CM_PER_TPTC1_CLKCTRL, 0),
379 _CLK_DETAIL(EDMA_TPTC2_CLK, CM_PER_TPTC2_CLKCTRL, 0),
381 /* MMCHS modules, hwmods start with mmc1*/
382 _CLK_DETAIL(MMC1_CLK, CM_PER_MMC0_CLKCTRL, 0),
383 _CLK_DETAIL(MMC2_CLK, CM_PER_MMC1_CLKCTRL, 0),
384 _CLK_DETAIL(MMC3_CLK, CM_PER_MMC1_CLKCTRL, 0),
387 _CLK_DETAIL(PWMSS0_CLK, CM_PER_EPWMSS0_CLKCTRL, 0),
388 _CLK_DETAIL(PWMSS1_CLK, CM_PER_EPWMSS1_CLKCTRL, 0),
389 _CLK_DETAIL(PWMSS2_CLK, CM_PER_EPWMSS2_CLKCTRL, 0),
391 _CLK_DETAIL(MAILBOX0_CLK, CM_PER_MAILBOX0_CLKCTRL, 0),
392 _CLK_DETAIL(SPINLOCK0_CLK, CM_PER_SPINLOCK0_CLKCTRL, 0),
395 _CLK_DETAIL(RTC_CLK, CM_RTC_RTC_CLKCTRL, 0),
397 { INVALID_CLK_IDENT, 0},
400 /* Read/Write macros */
401 #define prcm_read_4(reg) \
402 bus_space_read_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg)
403 #define prcm_write_4(reg, val) \
404 bus_space_write_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg, val)
406 void am335x_prcm_setup_dmtimer(int);
409 am335x_prcm_probe(device_t dev)
412 if (!ofw_bus_status_okay(dev))
415 if (ofw_bus_is_compatible(dev, "ti,am3-prcm")) {
416 device_set_desc(dev, "AM335x Power and Clock Management");
417 return(BUS_PROBE_DEFAULT);
424 am335x_prcm_attach(device_t dev)
426 struct am335x_prcm_softc *sc = device_get_softc(dev);
427 unsigned int sysclk, fclk;
432 if (bus_alloc_resources(dev, am335x_prcm_spec, sc->res)) {
433 device_printf(dev, "could not allocate resources\n");
437 sc->bst = rman_get_bustag(sc->res[0]);
438 sc->bsh = rman_get_bushandle(sc->res[0]);
441 ti_cpu_reset = am335x_prcm_reset;
443 if (am335x_clk_get_sysclk_freq(NULL, &sysclk) != 0)
445 if (am335x_clk_get_arm_fclk_freq(NULL, &fclk) != 0)
448 device_printf(dev, "Clocks: System %u.%01u MHz, CPU %u MHz\n",
449 sysclk/1000000, (sysclk % 1000000)/100000, fclk/1000000);
451 device_printf(dev, "can't read frequencies yet (SCM device not ready?)\n");
456 static device_method_t am335x_prcm_methods[] = {
457 DEVMETHOD(device_probe, am335x_prcm_probe),
458 DEVMETHOD(device_attach, am335x_prcm_attach),
462 static driver_t am335x_prcm_driver = {
465 sizeof(struct am335x_prcm_softc),
468 static devclass_t am335x_prcm_devclass;
470 EARLY_DRIVER_MODULE(am335x_prcm, simplebus, am335x_prcm_driver,
471 am335x_prcm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY);
472 MODULE_VERSION(am335x_prcm, 1);
473 MODULE_DEPEND(am335x_prcm, ti_scm, 1, 1, 1);
475 static struct am335x_clk_details*
476 am335x_clk_details(clk_ident_t id)
478 struct am335x_clk_details *walker;
480 for (walker = g_am335x_clk_details; walker->id != INVALID_CLK_IDENT; walker++) {
481 if (id == walker->id)
489 am335x_clk_noop_activate(struct ti_clock_dev *clkdev)
496 am335x_clk_generic_activate(struct ti_clock_dev *clkdev)
498 struct am335x_prcm_softc *sc = am335x_prcm_sc;
499 struct am335x_clk_details* clk_details;
504 clk_details = am335x_clk_details(clkdev->id);
506 if (clk_details == NULL)
509 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */
510 prcm_write_4(clk_details->clkctrl_reg, 2);
511 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2)
518 am335x_clk_gpio_activate(struct ti_clock_dev *clkdev)
520 struct am335x_prcm_softc *sc = am335x_prcm_sc;
521 struct am335x_clk_details* clk_details;
526 clk_details = am335x_clk_details(clkdev->id);
528 if (clk_details == NULL)
531 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */
532 /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */
533 prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18));
534 while ((prcm_read_4(clk_details->clkctrl_reg) &
535 (3 | (1 << 18) )) != (2 | (1 << 18)))
542 am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev)
549 am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev)
551 struct am335x_prcm_softc *sc = am335x_prcm_sc;
552 struct am335x_clk_details* clk_details;
557 clk_details = am335x_clk_details(clkdev->id);
559 if (clk_details == NULL)
562 /* set *_CLKCTRL register MODULEMODE[1:0] to disable(0) */
563 prcm_write_4(clk_details->clkctrl_reg, 0);
564 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0)
571 am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc)
578 am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc)
580 struct am335x_prcm_softc *sc = am335x_prcm_sc;
581 struct am335x_clk_details* clk_details;
587 clk_details = am335x_clk_details(clkdev->id);
589 if (clk_details == NULL)
594 reg = 0; /* SEL2: TCLKIN clock */
597 reg = 1; /* SEL1: CLK_M_OSC clock */
600 reg = 2; /* SEL3: CLK_32KHZ clock */
606 prcm_write_4(clk_details->clksel_reg, reg);
607 while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg)
614 am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
621 am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
623 uint32_t ctrl_status;
625 /* Read the input clock freq from the control module. */
626 if (ti_scm_reg_read_4(SCM_CTRL_STATUS, &ctrl_status))
629 switch ((ctrl_status>>22) & 0x3) {
651 #define DPLL_BYP_CLKSEL(reg) ((reg>>23) & 1)
652 #define DPLL_DIV(reg) ((reg & 0x7f)+1)
653 #define DPLL_MULT(reg) ((reg>>8) & 0x7FF)
654 #define DPLL_MAX_MUL 0x800
655 #define DPLL_MAX_DIV 0x80
658 am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
663 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_MPU);
665 /*Check if we are running in bypass */
666 if (DPLL_BYP_CLKSEL(reg))
669 am335x_clk_get_sysclk_freq(NULL, &sysclk);
670 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg));
675 am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
680 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_DISP);
682 /*Check if we are running in bypass */
683 if (DPLL_BYP_CLKSEL(reg))
686 am335x_clk_get_sysclk_freq(NULL, &sysclk);
687 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg));
692 am335x_clk_set_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int freq)
697 unsigned int delta, min_delta;
699 am335x_clk_get_sysclk_freq(NULL, &sysclk);
702 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4);
704 /* Make sure it's in bypass mode */
705 while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP)
709 /* Dumb and non-optimal implementation */
711 for (i = 1; i < DPLL_MAX_MUL; i++) {
712 for (j = 1; j < DPLL_MAX_DIV; j++) {
713 delta = abs(freq - i*(sysclk/j));
714 if (delta < min_delta) {
724 prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (mul << 8) | (div - 1));
727 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7);
730 while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP)
731 & (1 << 0))) && timeout--)
738 am335x_prcm_reset(void)
740 prcm_write_4(PRM_RSTCTRL, (1<<1));
744 am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev)
746 struct am335x_prcm_softc *sc = am335x_prcm_sc;
751 /* set MODULENAME to ENABLE */
752 prcm_write_4(CM_PER_CPGMAC0_CLKCTRL, 2);
754 /* wait for IDLEST to become Func(0) */
755 while(prcm_read_4(CM_PER_CPGMAC0_CLKCTRL) & (3<<16));
757 /*set CLKTRCTRL to SW_WKUP(2) */
758 prcm_write_4(CM_PER_CPSW_CLKSTCTRL, 2);
760 /* wait for 125 MHz OCP clock to become active */
761 while((prcm_read_4(CM_PER_CPSW_CLKSTCTRL) & (1<<4)) == 0);
766 am335x_clk_musb0_activate(struct ti_clock_dev *clkdev)
768 struct am335x_prcm_softc *sc = am335x_prcm_sc;
773 /* set ST_DPLL_CLKDCOLDO(9) to CLK_GATED(1) */
774 /* set DPLL_CLKDCOLDO_GATE_CTRL(8) to CLK_ENABLE(1)*/
775 prcm_write_4(CM_WKUP_CM_CLKDCOLDO_DPLL_PER, 0x300);
777 /*set MODULEMODE to ENABLE(2) */
778 prcm_write_4(CM_PER_USB0_CLKCTRL, 2);
780 /* wait for MODULEMODE to become ENABLE(2) */
781 while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2)
784 /* wait for IDLEST to become Func(0) */
785 while(prcm_read_4(CM_PER_USB0_CLKCTRL) & (3<<16))
792 am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev)
794 struct am335x_prcm_softc *sc = am335x_prcm_sc;
800 * For now set frequency to 2*VGA_PIXEL_CLOCK
802 am335x_clk_set_arm_disp_freq(clkdev, 25175000*2);
804 /*set MODULEMODE to ENABLE(2) */
805 prcm_write_4(CM_PER_LCDC_CLKCTRL, 2);
807 /* wait for MODULEMODE to become ENABLE(2) */
808 while ((prcm_read_4(CM_PER_LCDC_CLKCTRL) & 0x3) != 2)
811 /* wait for IDLEST to become Func(0) */
812 while(prcm_read_4(CM_PER_LCDC_CLKCTRL) & (3<<16))
819 am335x_clk_pruss_activate(struct ti_clock_dev *clkdev)
821 struct am335x_prcm_softc *sc = am335x_prcm_sc;
826 /* Set MODULEMODE to ENABLE(2) */
827 prcm_write_4(CM_PER_PRUSS_CLKCTRL, 2);
829 /* Wait for MODULEMODE to become ENABLE(2) */
830 while ((prcm_read_4(CM_PER_PRUSS_CLKCTRL) & 0x3) != 2)
833 /* Set CLKTRCTRL to SW_WKUP(2) */
834 prcm_write_4(CM_PER_PRUSS_CLKSTCTRL, 2);
836 /* Wait for the 200 MHz OCP clock to become active */
837 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<4)) == 0)
840 /* Wait for the 200 MHz IEP clock to become active */
841 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<5)) == 0)
844 /* Wait for the 192 MHz UART clock to become active */
845 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0)
848 /* Select L3F as OCP clock */
849 prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 0);
850 while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0)
853 /* Clear the RESET bit */
854 prcm_write_4(PRM_PER_RSTCTRL, prcm_read_4(PRM_PER_RSTCTRL) & ~2);