sys/arm/ti/am335x/am335x_prcm.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/bus.h>
  35 #include <sys/kernel.h>
  36 #include <sys/module.h>
  37 #include <sys/malloc.h>
  38 #include <sys/rman.h>
  39 #include <sys/timeet.h>
  40 #include <sys/timetc.h>
  41 #include <sys/watchdog.h>
  42 #include <machine/bus.h>
  43 #include <machine/cpu.h>
  44 #include <machine/intr.h>
  45
  46 #include <arm/ti/tivar.h>
  47 #include <arm/ti/ti_scm.h>
  48 #include <arm/ti/ti_prcm.h>
  49
  50 #include <dev/ofw/openfirm.h>
  51 #include <dev/ofw/ofw_bus.h>
  52 #include <dev/ofw/ofw_bus_subr.h>
  53
  54 #include <machine/bus.h>
  55
  56 #include "am335x_scm.h"
  57
  58 #define CM_PER                          0
  59 #define CM_PER_L4LS_CLKSTCTRL           (CM_PER + 0x000)
  60 #define CM_PER_L3S_CLKSTCTRL            (CM_PER + 0x004)
  61 #define CM_PER_L3_CLKSTCTRL             (CM_PER + 0x00C)
  62 #define CM_PER_CPGMAC0_CLKCTRL          (CM_PER + 0x014)
  63 #define CM_PER_LCDC_CLKCTRL             (CM_PER + 0x018)
  64 #define CM_PER_USB0_CLKCTRL             (CM_PER + 0x01C)
  65 #define CM_PER_TPTC0_CLKCTRL            (CM_PER + 0x024)
  66 #define CM_PER_UART5_CLKCTRL            (CM_PER + 0x038)
  67 #define CM_PER_MMC0_CLKCTRL             (CM_PER + 0x03C)
  68 #define CM_PER_I2C2_CLKCTRL             (CM_PER + 0x044)
  69 #define CM_PER_I2C1_CLKCTRL             (CM_PER + 0x048)
  70 #define CM_PER_SPI0_CLKCTRL             (CM_PER + 0x04C)
  71 #define CM_PER_SPI1_CLKCTRL             (CM_PER + 0x050)
  72 #define CM_PER_UART1_CLKCTRL            (CM_PER + 0x06C)
  73 #define CM_PER_UART2_CLKCTRL            (CM_PER + 0x070)
  74 #define CM_PER_UART3_CLKCTRL            (CM_PER + 0x074)
  75 #define CM_PER_UART4_CLKCTRL            (CM_PER + 0x078)
  76 #define CM_PER_TIMER7_CLKCTRL           (CM_PER + 0x07C)
  77 #define CM_PER_TIMER2_CLKCTRL           (CM_PER + 0x080)
  78 #define CM_PER_TIMER3_CLKCTRL           (CM_PER + 0x084)
  79 #define CM_PER_TIMER4_CLKCTRL           (CM_PER + 0x088)
  80 #define CM_PER_GPIO1_CLKCTRL            (CM_PER + 0x0AC)
  81 #define CM_PER_GPIO2_CLKCTRL            (CM_PER + 0x0B0)
  82 #define CM_PER_GPIO3_CLKCTRL            (CM_PER + 0x0B4)
  83 #define CM_PER_TPCC_CLKCTRL             (CM_PER + 0x0BC)
  84 #define CM_PER_EPWMSS1_CLKCTRL          (CM_PER + 0x0CC)
  85 #define CM_PER_EPWMSS0_CLKCTRL          (CM_PER + 0x0D4)
  86 #define CM_PER_EPWMSS2_CLKCTRL          (CM_PER + 0x0D8)
  87 #define CM_PER_L3_INSTR_CLKCTRL         (CM_PER + 0x0DC)
  88 #define CM_PER_L3_CLKCTRL               (CM_PER + 0x0E0)
  89 #define CM_PER_PRUSS_CLKCTRL            (CM_PER + 0x0E8)
  90 #define CM_PER_TIMER5_CLKCTRL           (CM_PER + 0x0EC)
  91 #define CM_PER_TIMER6_CLKCTRL           (CM_PER + 0x0F0)
  92 #define CM_PER_MMC1_CLKCTRL             (CM_PER + 0x0F4)
  93 #define CM_PER_MMC2_CLKCTRL             (CM_PER + 0x0F8)
  94 #define CM_PER_TPTC1_CLKCTRL            (CM_PER + 0x0FC)
  95 #define CM_PER_TPTC2_CLKCTRL            (CM_PER + 0x100)
  96 #define CM_PER_SPINLOCK0_CLKCTRL        (CM_PER + 0x10C)
  97 #define CM_PER_MAILBOX0_CLKCTRL         (CM_PER + 0x110)
  98 #define CM_PER_OCPWP_L3_CLKSTCTRL       (CM_PER + 0x12C)
  99 #define CM_PER_OCPWP_CLKCTRL            (CM_PER + 0x130)
 100 #define CM_PER_CPSW_CLKSTCTRL           (CM_PER + 0x144)
 101 #define CM_PER_PRUSS_CLKSTCTRL          (CM_PER + 0x140)
 102
 103 #define CM_WKUP                         0x400
 104 #define CM_WKUP_CLKSTCTRL               (CM_WKUP + 0x000)
 105 #define CM_WKUP_CONTROL_CLKCTRL         (CM_WKUP + 0x004)
 106 #define CM_WKUP_GPIO0_CLKCTRL           (CM_WKUP + 0x008)
 107 #define CM_WKUP_CM_L3_AON_CLKSTCTRL     (CM_WKUP + 0x01C)
 108 #define CM_WKUP_CM_CLKSEL_DPLL_MPU      (CM_WKUP + 0x02C)
 109 #define CM_WKUP_CM_IDLEST_DPLL_DISP     (CM_WKUP + 0x048)
 110 #define CM_WKUP_CM_CLKSEL_DPLL_DISP     (CM_WKUP + 0x054)
 111 #define CM_WKUP_CM_CLKDCOLDO_DPLL_PER   (CM_WKUP + 0x07C)
 112 #define CM_WKUP_CM_CLKMODE_DPLL_DISP    (CM_WKUP + 0x098)
 113 #define CM_WKUP_I2C0_CLKCTRL            (CM_WKUP + 0x0B8)
 114 #define CM_WKUP_ADC_TSC_CLKCTRL         (CM_WKUP + 0x0BC)
 115
 116 #define CM_DPLL                         0x500
 117 #define CLKSEL_TIMER7_CLK               (CM_DPLL + 0x004)
 118 #define CLKSEL_TIMER2_CLK               (CM_DPLL + 0x008)
 119 #define CLKSEL_TIMER3_CLK               (CM_DPLL + 0x00C)
 120 #define CLKSEL_TIMER4_CLK               (CM_DPLL + 0x010)
 121 #define CLKSEL_TIMER5_CLK               (CM_DPLL + 0x018)
 122 #define CLKSEL_TIMER6_CLK               (CM_DPLL + 0x01C)
 123 #define CLKSEL_PRUSS_OCP_CLK            (CM_DPLL + 0x030)
 124
 125 #define CM_RTC                          0x800
 126 #define CM_RTC_RTC_CLKCTRL              (CM_RTC + 0x000)
 127 #define CM_RTC_CLKSTCTRL                (CM_RTC + 0x004)
 128
 129 #define PRM_PER                         0xC00
 130 #define PRM_PER_RSTCTRL                 (PRM_PER + 0x00)
 131
 132 #define PRM_DEVICE_OFFSET               0xF00
 133 #define PRM_RSTCTRL                     (PRM_DEVICE_OFFSET + 0x00)
 134
 135 struct am335x_prcm_softc {
 136         struct resource *       res[2];
 137         bus_space_tag_t         bst;
 138         bus_space_handle_t      bsh;
 139 };
 140
 141 static struct resource_spec am335x_prcm_spec[] = {
 142         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 143         { -1, 0 }
 144 };
 145
 146 static struct am335x_prcm_softc *am335x_prcm_sc = NULL;
 147
 148 static int am335x_clk_noop_activate(struct ti_clock_dev *clkdev);
 149 static int am335x_clk_generic_activate(struct ti_clock_dev *clkdev);
 150 static int am335x_clk_gpio_activate(struct ti_clock_dev *clkdev);
 151 static int am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev);
 152 static int am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev);
 153 static int am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
 154 static int am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
 155 static int am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev,  unsigned int *freq);
 156 static int am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
 157 static int am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
 158 static int am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
 159 static int am335x_clk_set_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int freq);
 160 static void am335x_prcm_reset(void);
 161 static int am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev);
 162 static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev);
 163 static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev);
 164 static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev);
 165
 166 #define AM335X_NOOP_CLOCK_DEV(i) \
 167         {       .id = (i), \
 168                 .clk_activate = am335x_clk_noop_activate, \
 169                 .clk_deactivate = am335x_clk_noop_deactivate, \
 170                 .clk_set_source = am335x_clk_noop_set_source, \
 171                 .clk_accessible = NULL, \
 172                 .clk_get_source_freq = NULL, \
 173                 .clk_set_source_freq = NULL \
 174         }
 175
 176 #define AM335X_GENERIC_CLOCK_DEV(i) \
 177         {       .id = (i), \
 178                 .clk_activate = am335x_clk_generic_activate, \
 179                 .clk_deactivate = am335x_clk_generic_deactivate, \
 180                 .clk_set_source = am335x_clk_generic_set_source, \
 181                 .clk_accessible = NULL, \
 182                 .clk_get_source_freq = NULL, \
 183                 .clk_set_source_freq = NULL \
 184         }
 185
 186 #define AM335X_GPIO_CLOCK_DEV(i) \
 187         {       .id = (i), \
 188                 .clk_activate = am335x_clk_gpio_activate, \
 189                 .clk_deactivate = am335x_clk_generic_deactivate, \
 190                 .clk_set_source = am335x_clk_generic_set_source, \
 191                 .clk_accessible = NULL, \
 192                 .clk_get_source_freq = NULL, \
 193                 .clk_set_source_freq = NULL \
 194         }
 195
 196 #define AM335X_MMCHS_CLOCK_DEV(i) \
 197         {       .id = (i), \
 198                 .clk_activate = am335x_clk_generic_activate, \
 199                 .clk_deactivate = am335x_clk_generic_deactivate, \
 200                 .clk_set_source = am335x_clk_generic_set_source, \
 201                 .clk_accessible = NULL, \
 202                 .clk_get_source_freq = am335x_clk_hsmmc_get_source_freq, \
 203                 .clk_set_source_freq = NULL \
 204         }
 205
 206 struct ti_clock_dev ti_am335x_clk_devmap[] = {
 207         /* System clocks */
 208         {       .id                  = SYS_CLK,
 209                 .clk_activate        = NULL,
 210                 .clk_deactivate      = NULL,
 211                 .clk_set_source      = NULL,
 212                 .clk_accessible      = NULL,
 213                 .clk_get_source_freq = am335x_clk_get_sysclk_freq,
 214                 .clk_set_source_freq = NULL,
 215         },
 216         /* MPU (ARM) core clocks */
 217         {       .id                  = MPU_CLK,
 218                 .clk_activate        = NULL,
 219                 .clk_deactivate      = NULL,
 220                 .clk_set_source      = NULL,
 221                 .clk_accessible      = NULL,
 222                 .clk_get_source_freq = am335x_clk_get_arm_fclk_freq,
 223                 .clk_set_source_freq = NULL,
 224         },
 225         /* CPSW Ethernet Switch core clocks */
 226         {       .id                  = CPSW_CLK,
 227                 .clk_activate        = am335x_clk_cpsw_activate,
 228                 .clk_deactivate      = NULL,
 229                 .clk_set_source      = NULL,
 230                 .clk_accessible      = NULL,
 231                 .clk_get_source_freq = NULL,
 232                 .clk_set_source_freq = NULL,
 233         },
 234
 235         /* Mentor USB HS controller core clocks */
 236         {       .id                  = MUSB0_CLK,
 237                 .clk_activate        = am335x_clk_musb0_activate,
 238                 .clk_deactivate      = NULL,
 239                 .clk_set_source      = NULL,
 240                 .clk_accessible      = NULL,
 241                 .clk_get_source_freq = NULL,
 242                 .clk_set_source_freq = NULL,
 243         },
 244
 245         /* LCD controller clocks */
 246         {       .id                  = LCDC_CLK,
 247                 .clk_activate        = am335x_clk_lcdc_activate,
 248                 .clk_deactivate      = NULL,
 249                 .clk_set_source      = NULL,
 250                 .clk_accessible      = NULL,
 251                 .clk_get_source_freq = am335x_clk_get_arm_disp_freq,
 252                 .clk_set_source_freq = am335x_clk_set_arm_disp_freq,
 253         },
 254
 255         /* UART */
 256         AM335X_NOOP_CLOCK_DEV(UART1_CLK),
 257         AM335X_GENERIC_CLOCK_DEV(UART2_CLK),
 258         AM335X_GENERIC_CLOCK_DEV(UART3_CLK),
 259         AM335X_GENERIC_CLOCK_DEV(UART4_CLK),
 260         AM335X_GENERIC_CLOCK_DEV(UART5_CLK),
 261         AM335X_GENERIC_CLOCK_DEV(UART6_CLK),
 262
 263         /* DMTimer */
 264         AM335X_GENERIC_CLOCK_DEV(TIMER2_CLK),
 265         AM335X_GENERIC_CLOCK_DEV(TIMER3_CLK),
 266         AM335X_GENERIC_CLOCK_DEV(TIMER4_CLK),
 267         AM335X_GENERIC_CLOCK_DEV(TIMER5_CLK),
 268         AM335X_GENERIC_CLOCK_DEV(TIMER6_CLK),
 269         AM335X_GENERIC_CLOCK_DEV(TIMER7_CLK),
 270
 271         /* GPIO, we use hwmods as reference, not units in spec */
 272         AM335X_GPIO_CLOCK_DEV(GPIO1_CLK),
 273         AM335X_GPIO_CLOCK_DEV(GPIO2_CLK),
 274         AM335X_GPIO_CLOCK_DEV(GPIO3_CLK),
 275         AM335X_GPIO_CLOCK_DEV(GPIO4_CLK),
 276
 277         /* I2C we use hwmods as reference, not units in spec */
 278         AM335X_GENERIC_CLOCK_DEV(I2C1_CLK),
 279         AM335X_GENERIC_CLOCK_DEV(I2C2_CLK),
 280         AM335X_GENERIC_CLOCK_DEV(I2C3_CLK),
 281
 282         /* McSPI we use hwmods as reference, not units in spec */
 283         AM335X_GENERIC_CLOCK_DEV(SPI0_CLK),
 284         AM335X_GENERIC_CLOCK_DEV(SPI1_CLK),
 285
 286         /* TSC_ADC */
 287         AM335X_GENERIC_CLOCK_DEV(TSC_ADC_CLK),
 288
 289         /* EDMA */
 290         AM335X_GENERIC_CLOCK_DEV(EDMA_TPCC_CLK),
 291         AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC0_CLK),
 292         AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC1_CLK),
 293         AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC2_CLK),
 294
 295         /* MMCHS */
 296         AM335X_MMCHS_CLOCK_DEV(MMC1_CLK),
 297         AM335X_MMCHS_CLOCK_DEV(MMC2_CLK),
 298         AM335X_MMCHS_CLOCK_DEV(MMC3_CLK),
 299
 300         /* PWMSS */
 301         AM335X_GENERIC_CLOCK_DEV(PWMSS0_CLK),
 302         AM335X_GENERIC_CLOCK_DEV(PWMSS1_CLK),
 303         AM335X_GENERIC_CLOCK_DEV(PWMSS2_CLK),
 304
 305         /* System Mailbox clock */
 306         AM335X_GENERIC_CLOCK_DEV(MAILBOX0_CLK),
 307
 308         /* SPINLOCK */
 309         AM335X_GENERIC_CLOCK_DEV(SPINLOCK0_CLK),
 310
 311         /* PRU-ICSS */
 312         {       .id                  = PRUSS_CLK,
 313                 .clk_activate        = am335x_clk_pruss_activate,
 314                 .clk_deactivate      = NULL,
 315                 .clk_set_source      = NULL,
 316                 .clk_accessible      = NULL,
 317                 .clk_get_source_freq = NULL,
 318                 .clk_set_source_freq = NULL,
 319         },
 320
 321         /* RTC */
 322         AM335X_GENERIC_CLOCK_DEV(RTC_CLK),
 323
 324         {  INVALID_CLK_IDENT, NULL, NULL, NULL, NULL }
 325 };
 326
 327 struct am335x_clk_details {
 328         clk_ident_t     id;
 329         uint32_t        clkctrl_reg;
 330         uint32_t        clksel_reg;
 331 };
 332
 333 #define _CLK_DETAIL(i, c, s) \
 334         {       .id = (i), \
 335                 .clkctrl_reg = (c), \
 336                 .clksel_reg = (s), \
 337         }
 338
 339 static struct am335x_clk_details g_am335x_clk_details[] = {
 340
 341         /* UART. UART0 clock not controllable. */
 342         _CLK_DETAIL(UART1_CLK, 0, 0),
 343         _CLK_DETAIL(UART2_CLK, CM_PER_UART1_CLKCTRL, 0),
 344         _CLK_DETAIL(UART3_CLK, CM_PER_UART2_CLKCTRL, 0),
 345         _CLK_DETAIL(UART4_CLK, CM_PER_UART3_CLKCTRL, 0),
 346         _CLK_DETAIL(UART5_CLK, CM_PER_UART4_CLKCTRL, 0),
 347         _CLK_DETAIL(UART6_CLK, CM_PER_UART5_CLKCTRL, 0),
 348
 349         /* DMTimer modules */
 350         _CLK_DETAIL(TIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK),
 351         _CLK_DETAIL(TIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK),
 352         _CLK_DETAIL(TIMER4_CLK, CM_PER_TIMER4_CLKCTRL, CLKSEL_TIMER4_CLK),
 353         _CLK_DETAIL(TIMER5_CLK, CM_PER_TIMER5_CLKCTRL, CLKSEL_TIMER5_CLK),
 354         _CLK_DETAIL(TIMER6_CLK, CM_PER_TIMER6_CLKCTRL, CLKSEL_TIMER6_CLK),
 355         _CLK_DETAIL(TIMER7_CLK, CM_PER_TIMER7_CLKCTRL, CLKSEL_TIMER7_CLK),
 356
 357         /* GPIO modules, hwmods start with gpio1 */
 358         _CLK_DETAIL(GPIO1_CLK, CM_WKUP_GPIO0_CLKCTRL, 0),
 359         _CLK_DETAIL(GPIO2_CLK, CM_PER_GPIO1_CLKCTRL, 0),
 360         _CLK_DETAIL(GPIO3_CLK, CM_PER_GPIO2_CLKCTRL, 0),
 361         _CLK_DETAIL(GPIO4_CLK, CM_PER_GPIO3_CLKCTRL, 0),
 362
 363         /* I2C modules, hwmods start with i2c1 */
 364         _CLK_DETAIL(I2C1_CLK, CM_WKUP_I2C0_CLKCTRL, 0),
 365         _CLK_DETAIL(I2C2_CLK, CM_PER_I2C1_CLKCTRL, 0),
 366         _CLK_DETAIL(I2C3_CLK, CM_PER_I2C2_CLKCTRL, 0),
 367
 368         /* McSPI modules, hwmods start with spi0 */
 369         _CLK_DETAIL(SPI0_CLK, CM_PER_SPI0_CLKCTRL, 0),
 370         _CLK_DETAIL(SPI1_CLK, CM_PER_SPI1_CLKCTRL, 0),
 371
 372         /* TSC_ADC module */
 373         _CLK_DETAIL(TSC_ADC_CLK, CM_WKUP_ADC_TSC_CLKCTRL, 0),
 374
 375         /* EDMA modules */
 376         _CLK_DETAIL(EDMA_TPCC_CLK, CM_PER_TPCC_CLKCTRL, 0),
 377         _CLK_DETAIL(EDMA_TPTC0_CLK, CM_PER_TPTC0_CLKCTRL, 0),
 378         _CLK_DETAIL(EDMA_TPTC1_CLK, CM_PER_TPTC1_CLKCTRL, 0),
 379         _CLK_DETAIL(EDMA_TPTC2_CLK, CM_PER_TPTC2_CLKCTRL, 0),
 380
 381         /* MMCHS modules, hwmods start with mmc1*/
 382         _CLK_DETAIL(MMC1_CLK, CM_PER_MMC0_CLKCTRL, 0),
 383         _CLK_DETAIL(MMC2_CLK, CM_PER_MMC1_CLKCTRL, 0),
 384         _CLK_DETAIL(MMC3_CLK, CM_PER_MMC1_CLKCTRL, 0),
 385
 386         /* PWMSS modules */
 387         _CLK_DETAIL(PWMSS0_CLK, CM_PER_EPWMSS0_CLKCTRL, 0),
 388         _CLK_DETAIL(PWMSS1_CLK, CM_PER_EPWMSS1_CLKCTRL, 0),
 389         _CLK_DETAIL(PWMSS2_CLK, CM_PER_EPWMSS2_CLKCTRL, 0),
 390
 391         _CLK_DETAIL(MAILBOX0_CLK, CM_PER_MAILBOX0_CLKCTRL, 0),
 392         _CLK_DETAIL(SPINLOCK0_CLK, CM_PER_SPINLOCK0_CLKCTRL, 0),
 393
 394         /* RTC module */
 395         _CLK_DETAIL(RTC_CLK, CM_RTC_RTC_CLKCTRL, 0),
 396
 397         { INVALID_CLK_IDENT, 0},
 398 };
 399
 400 /* Read/Write macros */
 401 #define prcm_read_4(reg)                \
 402         bus_space_read_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg)
 403 #define prcm_write_4(reg, val)          \
 404         bus_space_write_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg, val)
 405
 406 void am335x_prcm_setup_dmtimer(int);
 407
 408 static int
 409 am335x_prcm_probe(device_t dev)
 410 {
 411
 412         if (!ofw_bus_status_okay(dev))
 413                 return (ENXIO);
 414
 415         if (ofw_bus_is_compatible(dev, "ti,am3-prcm")) {
 416                 device_set_desc(dev, "AM335x Power and Clock Management");
 417                 return(BUS_PROBE_DEFAULT);
 418         }
 419
 420         return (ENXIO);
 421 }
 422
 423 static int
 424 am335x_prcm_attach(device_t dev)
 425 {
 426         struct am335x_prcm_softc *sc = device_get_softc(dev);
 427         unsigned int sysclk, fclk;
 428
 429         if (am335x_prcm_sc)
 430                 return (ENXIO);
 431
 432         if (bus_alloc_resources(dev, am335x_prcm_spec, sc->res)) {
 433                 device_printf(dev, "could not allocate resources\n");
 434                 return (ENXIO);
 435         }
 436
 437         sc->bst = rman_get_bustag(sc->res[0]);
 438         sc->bsh = rman_get_bushandle(sc->res[0]);
 439
 440         am335x_prcm_sc = sc;
 441         ti_cpu_reset = am335x_prcm_reset;
 442
 443         if (am335x_clk_get_sysclk_freq(NULL, &sysclk) != 0)
 444                 sysclk = 0;
 445         if (am335x_clk_get_arm_fclk_freq(NULL, &fclk) != 0)
 446                 fclk = 0;
 447         if (sysclk && fclk)
 448                 device_printf(dev, "Clocks: System %u.%01u MHz, CPU %u MHz\n",
 449                     sysclk/1000000, (sysclk % 1000000)/100000, fclk/1000000);
 450         else
 451                 device_printf(dev, "can't read frequencies yet (SCM device not ready?)\n");
 452
 453         return (0);
 454 }
 455
 456 static device_method_t am335x_prcm_methods[] = {
 457         DEVMETHOD(device_probe,         am335x_prcm_probe),
 458         DEVMETHOD(device_attach,        am335x_prcm_attach),
 459         { 0, 0 }
 460 };
 461
 462 static driver_t am335x_prcm_driver = {
 463         "am335x_prcm",
 464         am335x_prcm_methods,
 465         sizeof(struct am335x_prcm_softc),
 466 };
 467
 468 static devclass_t am335x_prcm_devclass;
 469
 470 EARLY_DRIVER_MODULE(am335x_prcm, simplebus, am335x_prcm_driver,
 471         am335x_prcm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY);
 472 MODULE_VERSION(am335x_prcm, 1);
 473 MODULE_DEPEND(am335x_prcm, ti_scm, 1, 1, 1);
 474
 475 static struct am335x_clk_details*
 476 am335x_clk_details(clk_ident_t id)
 477 {
 478         struct am335x_clk_details *walker;
 479
 480         for (walker = g_am335x_clk_details; walker->id != INVALID_CLK_IDENT; walker++) {
 481                 if (id == walker->id)
 482                         return (walker);
 483         }
 484
 485         return NULL;
 486 }
 487
 488 static int
 489 am335x_clk_noop_activate(struct ti_clock_dev *clkdev)
 490 {
 491
 492         return (0);
 493 }
 494
 495 static int
 496 am335x_clk_generic_activate(struct ti_clock_dev *clkdev)
 497 {
 498         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 499         struct am335x_clk_details* clk_details;
 500
 501         if (sc == NULL)
 502                 return ENXIO;
 503
 504         clk_details = am335x_clk_details(clkdev->id);
 505
 506         if (clk_details == NULL)
 507                 return (ENXIO);
 508
 509         /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */
 510         prcm_write_4(clk_details->clkctrl_reg, 2);
 511         while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2)
 512                 DELAY(10);
 513
 514         return (0);
 515 }
 516
 517 static int
 518 am335x_clk_gpio_activate(struct ti_clock_dev *clkdev)
 519 {
 520         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 521         struct am335x_clk_details* clk_details;
 522
 523         if (sc == NULL)
 524                 return ENXIO;
 525
 526         clk_details = am335x_clk_details(clkdev->id);
 527
 528         if (clk_details == NULL)
 529                 return (ENXIO);
 530
 531         /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */
 532         /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */
 533         prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18));
 534         while ((prcm_read_4(clk_details->clkctrl_reg) &
 535             (3 | (1 << 18) )) != (2 | (1 << 18)))
 536                 DELAY(10);
 537
 538         return (0);
 539 }
 540
 541 static int
 542 am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev)
 543 {
 544
 545         return(0);
 546 }
 547
 548 static int
 549 am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev)
 550 {
 551         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 552         struct am335x_clk_details* clk_details;
 553
 554         if (sc == NULL)
 555                 return ENXIO;
 556
 557         clk_details = am335x_clk_details(clkdev->id);
 558
 559         if (clk_details == NULL)
 560                 return (ENXIO);
 561
 562         /* set *_CLKCTRL register MODULEMODE[1:0] to disable(0) */
 563         prcm_write_4(clk_details->clkctrl_reg, 0);
 564         while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0)
 565                 DELAY(10);
 566
 567         return (0);
 568 }
 569
 570 static int
 571 am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc)
 572 {
 573
 574         return (0);
 575 }
 576
 577 static int
 578 am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc)
 579 {
 580         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 581         struct am335x_clk_details* clk_details;
 582         uint32_t reg;
 583
 584         if (sc == NULL)
 585                 return ENXIO;
 586
 587         clk_details = am335x_clk_details(clkdev->id);
 588
 589         if (clk_details == NULL)
 590                 return (ENXIO);
 591
 592         switch (clksrc) {
 593                 case EXT_CLK:
 594                         reg = 0; /* SEL2: TCLKIN clock */
 595                         break;
 596                 case SYSCLK_CLK:
 597                         reg = 1; /* SEL1: CLK_M_OSC clock */
 598                         break;
 599                 case F32KHZ_CLK:
 600                         reg = 2; /* SEL3: CLK_32KHZ clock */
 601                         break;
 602                 default:
 603                         return (ENXIO);
 604         }
 605
 606         prcm_write_4(clk_details->clksel_reg, reg);
 607         while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg)
 608                 DELAY(10);
 609
 610         return (0);
 611 }
 612
 613 static int
 614 am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev,  unsigned int *freq)
 615 {
 616         *freq = 96000000;
 617         return (0);
 618 }
 619
 620 static int
 621 am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
 622 {
 623         uint32_t ctrl_status;
 624
 625         /* Read the input clock freq from the control module. */
 626         if (ti_scm_reg_read_4(SCM_CTRL_STATUS, &ctrl_status))
 627                 return (ENXIO);
 628
 629         switch ((ctrl_status>>22) & 0x3) {
 630         case 0x0:
 631                 /* 19.2Mhz */
 632                 *freq = 19200000;
 633                 break;
 634         case 0x1:
 635                 /* 24Mhz */
 636                 *freq = 24000000;
 637                 break;
 638         case 0x2:
 639                 /* 25Mhz */
 640                 *freq = 25000000;
 641                 break;
 642         case 0x3:
 643                 /* 26Mhz */
 644                 *freq = 26000000;
 645                 break;
 646         }
 647
 648         return (0);
 649 }
 650
 651 #define DPLL_BYP_CLKSEL(reg)    ((reg>>23) & 1)
 652 #define DPLL_DIV(reg)           ((reg & 0x7f)+1)
 653 #define DPLL_MULT(reg)          ((reg>>8) & 0x7FF)
 654 #define DPLL_MAX_MUL            0x800
 655 #define DPLL_MAX_DIV            0x80
 656
 657 static int
 658 am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
 659 {
 660         uint32_t reg;
 661         uint32_t sysclk;
 662
 663         reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_MPU);
 664
 665         /*Check if we are running in bypass */
 666         if (DPLL_BYP_CLKSEL(reg))
 667                 return ENXIO;
 668
 669         am335x_clk_get_sysclk_freq(NULL, &sysclk);
 670         *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg));
 671         return(0);
 672 }
 673
 674 static int
 675 am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq)
 676 {
 677         uint32_t reg;
 678         uint32_t sysclk;
 679
 680         reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_DISP);
 681
 682         /*Check if we are running in bypass */
 683         if (DPLL_BYP_CLKSEL(reg))
 684                 return ENXIO;
 685
 686         am335x_clk_get_sysclk_freq(NULL, &sysclk);
 687         *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg));
 688         return(0);
 689 }
 690
 691 static int
 692 am335x_clk_set_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int freq)
 693 {
 694         uint32_t sysclk;
 695         uint32_t mul, div;
 696         uint32_t i, j;
 697         unsigned int delta, min_delta;
 698
 699         am335x_clk_get_sysclk_freq(NULL, &sysclk);
 700
 701         /* Bypass mode */
 702         prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4);
 703
 704         /* Make sure it's in bypass mode */
 705         while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP)
 706             & (1 << 8)))
 707                 DELAY(10);
 708
 709         /* Dumb and non-optimal implementation */
 710         min_delta = freq;
 711         for (i = 1; i < DPLL_MAX_MUL; i++) {
 712                 for (j = 1; j < DPLL_MAX_DIV; j++) {
 713                         delta = abs(freq - i*(sysclk/j));
 714                         if (delta < min_delta) {
 715                                 mul = i;
 716                                 div = j;
 717                                 min_delta = delta;
 718                         }
 719                         if (min_delta == 0)
 720                                 break;
 721                 }
 722         }
 723
 724         prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (mul << 8) | (div - 1));
 725
 726         /* Locked mode */
 727         prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7);
 728
 729         int timeout = 10000;
 730         while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP)
 731             & (1 << 0))) && timeout--)
 732                 DELAY(10);
 733
 734         return(0);
 735 }
 736
 737 static void
 738 am335x_prcm_reset(void)
 739 {
 740         prcm_write_4(PRM_RSTCTRL, (1<<1));
 741 }
 742
 743 static int
 744 am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev)
 745 {
 746         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 747
 748         if (sc == NULL)
 749                 return ENXIO;
 750
 751         /* set MODULENAME to ENABLE */
 752         prcm_write_4(CM_PER_CPGMAC0_CLKCTRL, 2);
 753
 754         /* wait for IDLEST to become Func(0) */
 755         while(prcm_read_4(CM_PER_CPGMAC0_CLKCTRL) & (3<<16));
 756
 757         /*set CLKTRCTRL to SW_WKUP(2) */
 758         prcm_write_4(CM_PER_CPSW_CLKSTCTRL, 2);
 759
 760         /* wait for 125 MHz OCP clock to become active */
 761         while((prcm_read_4(CM_PER_CPSW_CLKSTCTRL) & (1<<4)) == 0);
 762         return(0);
 763 }
 764
 765 static int
 766 am335x_clk_musb0_activate(struct ti_clock_dev *clkdev)
 767 {
 768         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 769
 770         if (sc == NULL)
 771                 return ENXIO;
 772
 773         /* set ST_DPLL_CLKDCOLDO(9) to CLK_GATED(1) */
 774         /* set DPLL_CLKDCOLDO_GATE_CTRL(8) to CLK_ENABLE(1)*/
 775         prcm_write_4(CM_WKUP_CM_CLKDCOLDO_DPLL_PER, 0x300);
 776
 777         /*set MODULEMODE to ENABLE(2) */
 778         prcm_write_4(CM_PER_USB0_CLKCTRL, 2);
 779
 780         /* wait for MODULEMODE to become ENABLE(2) */
 781         while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2)
 782                 DELAY(10);
 783
 784         /* wait for IDLEST to become Func(0) */
 785         while(prcm_read_4(CM_PER_USB0_CLKCTRL) & (3<<16))
 786                 DELAY(10);
 787
 788         return(0);
 789 }
 790
 791 static int
 792 am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev)
 793 {
 794         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 795
 796         if (sc == NULL)
 797                 return (ENXIO);
 798
 799         /*
 800          * For now set frequency to 2*VGA_PIXEL_CLOCK
 801          */
 802         am335x_clk_set_arm_disp_freq(clkdev, 25175000*2);
 803
 804         /*set MODULEMODE to ENABLE(2) */
 805         prcm_write_4(CM_PER_LCDC_CLKCTRL, 2);
 806
 807         /* wait for MODULEMODE to become ENABLE(2) */
 808         while ((prcm_read_4(CM_PER_LCDC_CLKCTRL) & 0x3) != 2)
 809                 DELAY(10);
 810
 811         /* wait for IDLEST to become Func(0) */
 812         while(prcm_read_4(CM_PER_LCDC_CLKCTRL) & (3<<16))
 813                 DELAY(10);
 814
 815         return (0);
 816 }
 817
 818 static int
 819 am335x_clk_pruss_activate(struct ti_clock_dev *clkdev)
 820 {
 821         struct am335x_prcm_softc *sc = am335x_prcm_sc;
 822
 823         if (sc == NULL)
 824                 return (ENXIO);
 825
 826         /* Set MODULEMODE to ENABLE(2) */
 827         prcm_write_4(CM_PER_PRUSS_CLKCTRL, 2);
 828
 829         /* Wait for MODULEMODE to become ENABLE(2) */
 830         while ((prcm_read_4(CM_PER_PRUSS_CLKCTRL) & 0x3) != 2)
 831                 DELAY(10);
 832
 833         /* Set CLKTRCTRL to SW_WKUP(2) */
 834         prcm_write_4(CM_PER_PRUSS_CLKSTCTRL, 2);
 835
 836         /* Wait for the 200 MHz OCP clock to become active */
 837         while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<4)) == 0)
 838                 DELAY(10);
 839
 840         /* Wait for the 200 MHz IEP clock to become active */
 841         while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<5)) == 0)
 842                 DELAY(10);
 843
 844         /* Wait for the 192 MHz UART clock to become active */
 845         while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0)
 846                 DELAY(10);
 847
 848         /* Select L3F as OCP clock */
 849         prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 0);
 850         while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0)
 851                 DELAY(10);
 852
 853         /* Clear the RESET bit */
 854         prcm_write_4(PRM_PER_RSTCTRL, prcm_read_4(PRM_PER_RSTCTRL) & ~2);
 855
 856         return (0);
 857 }