2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include "opt_evdev.h"
32 #include <sys/param.h>
33 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/limits.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/condvar.h>
43 #include <sys/resource.h>
45 #include <sys/sysctl.h>
46 #include <sys/selinfo.h>
50 #include <machine/bus.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
57 #include <dev/evdev/input.h>
58 #include <dev/evdev/evdev.h>
61 #include <arm/ti/ti_prcm.h>
62 #include <arm/ti/ti_adcreg.h>
63 #include <arm/ti/ti_adcvar.h>
67 #define DEFAULT_CHARGE_DELAY 0x400
68 #define STEPDLY_OPEN 0x98
75 /* Define our 8 steps, one for each input channel. */
76 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
77 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) },
78 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) },
79 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) },
80 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) },
81 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) },
82 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) },
83 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) },
84 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) },
87 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
89 static int ti_adc_detach(device_t dev);
93 ti_adc_ev_report(struct ti_adc_softc *sc)
96 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_X, sc->sc_x);
97 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_Y, sc->sc_y);
98 evdev_push_event(sc->sc_evdev, EV_KEY, BTN_TOUCH, sc->sc_pen_down);
99 evdev_sync(sc->sc_evdev);
104 ti_adc_enable(struct ti_adc_softc *sc)
108 TI_ADC_LOCK_ASSERT(sc);
110 if (sc->sc_last_state == 1)
113 /* Enable the FIFO0 threshold and the end of sequence interrupt. */
114 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
115 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
117 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID;
118 if (sc->sc_tsc_wires > 0) {
119 reg |= ADC_CTRL_TSC_ENABLE;
120 switch (sc->sc_tsc_wires) {
122 reg |= ADC_CTRL_TSC_4WIRE;
125 reg |= ADC_CTRL_TSC_5WIRE;
128 reg |= ADC_CTRL_TSC_8WIRE;
134 reg |= ADC_CTRL_ENABLE;
135 /* Enable the ADC. Run thru enabled steps, start the conversions. */
136 ADC_WRITE4(sc, ADC_CTRL, reg);
138 sc->sc_last_state = 1;
142 ti_adc_disable(struct ti_adc_softc *sc)
147 TI_ADC_LOCK_ASSERT(sc);
149 if (sc->sc_last_state == 0)
152 /* Disable all the enabled steps. */
153 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
155 /* Disable the ADC. */
156 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
158 /* Disable the FIFO0 threshold and the end of sequence interrupt. */
159 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
160 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
162 /* ACK any pending interrupt. */
163 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
165 /* Drain the FIFO data. */
166 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
168 data = ADC_READ4(sc, ADC_FIFO0DATA);
169 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
172 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
174 data = ADC_READ4(sc, ADC_FIFO1DATA);
175 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
178 sc->sc_last_state = 0;
182 ti_adc_setup(struct ti_adc_softc *sc)
187 TI_ADC_LOCK_ASSERT(sc);
189 /* Check for enabled inputs. */
190 enabled = sc->sc_tsc_enabled;
191 for (i = 0; i < sc->sc_adc_nchannels; i++) {
192 ain = sc->sc_adc_channels[i];
193 if (ti_adc_inputs[ain].enable)
194 enabled |= (1U << (ain + 1));
197 /* Set the ADC global status. */
200 /* Update the enabled steps. */
201 if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
202 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
210 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
212 struct ti_adc_input *input;
215 TI_ADC_LOCK_ASSERT(sc);
217 input = &ti_adc_inputs[ain];
218 reg = input->stepconfig;
219 val = ADC_READ4(sc, reg);
221 /* Set single ended operation. */
222 val &= ~ADC_STEP_DIFF_CNTRL;
224 /* Set the negative voltage reference. */
225 val &= ~ADC_STEP_RFM_MSK;
227 /* Set the positive voltage reference. */
228 val &= ~ADC_STEP_RFP_MSK;
230 /* Set the samples average. */
231 val &= ~ADC_STEP_AVG_MSK;
232 val |= input->samples << ADC_STEP_AVG_SHIFT;
234 /* Select the desired input. */
235 val &= ~ADC_STEP_INP_MSK;
236 val |= ain << ADC_STEP_INP_SHIFT;
238 /* Set the ADC to one-shot mode. */
239 val &= ~ADC_STEP_MODE_MSK;
241 ADC_WRITE4(sc, reg, val);
245 ti_adc_reset(struct ti_adc_softc *sc)
249 TI_ADC_LOCK_ASSERT(sc);
251 /* Disable all the inputs. */
252 for (i = 0; i < sc->sc_adc_nchannels; i++) {
253 ain = sc->sc_adc_channels[i];
254 ti_adc_inputs[ain].enable = 0;
259 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
262 struct ti_adc_softc *sc;
264 sc = (struct ti_adc_softc *)arg1;
267 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
270 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
271 if (error != 0 || req->newptr == NULL)
275 * The actual written value is the prescaler setting - 1.
276 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum
277 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
286 /* Disable the ADC. */
288 /* Update the ADC prescaler setting. */
289 ADC_WRITE4(sc, ADC_CLKDIV, reg);
290 /* Enable the ADC again. */
298 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)
302 struct ti_adc_softc *sc;
303 struct ti_adc_input *input;
305 input = (struct ti_adc_input *)arg1;
308 enable = input->enable;
309 error = sysctl_handle_int(oidp, &enable, sizeof(enable),
311 if (error != 0 || req->newptr == NULL)
318 /* Setup the ADC as needed. */
319 if (input->enable != enable) {
320 input->enable = enable;
322 if (input->enable == 0)
331 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
334 struct ti_adc_softc *sc;
335 struct ti_adc_input *input;
337 input = (struct ti_adc_input *)arg1;
341 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
344 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
345 if (error != 0 || req->newptr == NULL)
352 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
359 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)
361 int error, samples, i;
362 struct ti_adc_softc *sc;
363 struct ti_adc_input *input;
365 input = (struct ti_adc_input *)arg1;
368 if (input->samples > nitems(ti_adc_samples))
369 input->samples = nitems(ti_adc_samples);
370 samples = ti_adc_samples[input->samples];
372 error = sysctl_handle_int(oidp, &samples, 0, req);
373 if (error != 0 || req->newptr == NULL)
377 if (samples != ti_adc_samples[input->samples]) {
379 for (i = 0; i < nitems(ti_adc_samples); i++)
380 if (samples >= ti_adc_samples[i])
382 ti_adc_input_setup(sc, input->input);
390 ti_adc_read_data(struct ti_adc_softc *sc)
393 struct ti_adc_input *input;
396 TI_ADC_LOCK_ASSERT(sc);
398 /* Read the available data. */
399 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
401 data = ADC_READ4(sc, ADC_FIFO0DATA);
402 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT;
403 input = &ti_adc_inputs[ain];
404 if (input->enable == 0)
407 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK);
408 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
413 cmp_values(const void *a, const void *b)
415 const uint32_t *v1, *v2;
427 ti_adc_tsc_read_data(struct ti_adc_softc *sc)
434 TI_ADC_LOCK_ASSERT(sc);
436 /* Read the available data. */
437 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
443 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;
444 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
447 if (sc->sc_coord_readouts > 3) {
449 end = sc->sc_coord_readouts - 1;
450 qsort(data, sc->sc_coord_readouts,
451 sizeof(data[0]), &cmp_values);
452 qsort(&data[sc->sc_coord_readouts + 2],
453 sc->sc_coord_readouts,
454 sizeof(data[0]), &cmp_values);
458 end = sc->sc_coord_readouts;
462 for (i = start; i < end; i++)
466 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++)
471 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y);
475 if ((sc->sc_x != x) || (sc->sc_y != y)) {
478 ti_adc_ev_report(sc);
484 ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
486 /* Read the available data. */
487 if (status & ADC_IRQ_FIFO0_THRES)
488 ti_adc_read_data(sc);
492 ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
494 /* Read the available data. */
495 if (status & ADC_IRQ_FIFO1_THRES)
496 ti_adc_tsc_read_data(sc);
501 ti_adc_intr(void *arg)
503 struct ti_adc_softc *sc;
504 uint32_t status, rawstatus;
506 sc = (struct ti_adc_softc *)arg;
510 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);
511 status = ADC_READ4(sc, ADC_IRQSTATUS);
513 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) {
515 status |= ADC_IRQ_HW_PEN_ASYNC;
516 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
517 ADC_IRQ_HW_PEN_ASYNC);
519 ti_adc_ev_report(sc);
523 if (rawstatus & ADC_IRQ_PEN_UP) {
525 status |= ADC_IRQ_PEN_UP;
527 ti_adc_ev_report(sc);
531 if (status & ADC_IRQ_FIFO0_THRES)
532 ti_adc_intr_locked(sc, status);
534 if (status & ADC_IRQ_FIFO1_THRES)
535 ti_adc_tsc_intr_locked(sc, status);
538 /* ACK the interrupt. */
539 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
542 /* Start the next conversion ? */
543 if (status & ADC_IRQ_END_OF_SEQ)
550 ti_adc_sysctl_init(struct ti_adc_softc *sc)
553 struct sysctl_ctx_list *ctx;
554 struct sysctl_oid *tree_node, *inp_node, *inpN_node;
555 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
559 * Add per-pin sysctl tree/handlers.
561 ctx = device_get_sysctl_ctx(sc->sc_dev);
562 tree_node = device_get_sysctl_tree(sc->sc_dev);
563 tree = SYSCTL_CHILDREN(tree_node);
564 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv",
565 CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
566 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler");
567 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain",
568 CTLFLAG_RD, NULL, "ADC inputs");
569 inp_tree = SYSCTL_CHILDREN(inp_node);
571 for (i = 0; i < sc->sc_adc_nchannels; i++) {
572 ain = sc->sc_adc_channels[i];
574 snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
575 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
576 CTLFLAG_RD, NULL, "ADC input");
577 inpN_tree = SYSCTL_CHILDREN(inpN_node);
579 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable",
580 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
581 ti_adc_enable_proc, "IU", "Enable ADC input");
582 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay",
583 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
584 ti_adc_open_delay_proc, "IU", "ADC open delay");
585 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg",
586 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
587 ti_adc_samples_avg_proc, "IU", "ADC samples average");
588 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input",
589 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0,
590 "Converted raw value for the ADC input");
595 ti_adc_inputs_init(struct ti_adc_softc *sc)
598 struct ti_adc_input *input;
601 for (i = 0; i < sc->sc_adc_nchannels; i++) {
602 ain = sc->sc_adc_channels[i];
603 input = &ti_adc_inputs[ain];
609 ti_adc_input_setup(sc, ain);
615 ti_adc_tsc_init(struct ti_adc_softc *sc)
617 int i, start_step, end_step;
618 uint32_t stepconfig, val;
623 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
624 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit;
625 if (sc->sc_tsc_wires == 4)
626 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
627 else if (sc->sc_tsc_wires == 5)
628 stepconfig |= ADC_STEP_INP(4) |
629 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit;
630 else if (sc->sc_tsc_wires == 8)
631 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
633 start_step = ADC_STEPS - sc->sc_coord_readouts + 1;
634 end_step = start_step + sc->sc_coord_readouts - 1;
635 for (i = start_step; i <= end_step; i++) {
636 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
637 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
641 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
642 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit |
644 if (sc->sc_tsc_wires == 4)
645 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
646 else if (sc->sc_tsc_wires == 5)
647 stepconfig |= ADC_STEP_INP(4) |
648 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit;
649 else if (sc->sc_tsc_wires == 8)
650 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
652 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
653 end_step = start_step + sc->sc_coord_readouts - 1;
654 for (i = start_step; i <= end_step; i++) {
655 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
656 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
660 val = ADC_READ4(sc, ADC_IDLECONFIG);
661 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val);
662 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay);
665 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1;
666 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
667 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit |
668 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) |
670 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
671 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
673 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp);
674 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
675 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
677 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1);
679 sc->sc_tsc_enabled = 1;
680 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
681 end_step = ADC_STEPS;
682 for (i = start_step; i <= end_step; i++) {
683 sc->sc_tsc_enabled |= (1 << i);
691 ti_adc_idlestep_init(struct ti_adc_softc *sc)
695 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW;
697 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
701 ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs)
706 for (i = 0; i < nwire_configs; i++) {
707 wire = wire_configs[i] & 0xf;
708 ai = (wire_configs[i] >> 4) & 0xf;
711 sc->sc_xp_bit = ADC_STEP_XPP_SW;
715 sc->sc_xn_bit = ADC_STEP_XNN_SW;
719 sc->sc_yp_bit = ADC_STEP_YPP_SW;
723 sc->sc_yn_bit = ADC_STEP_YNN_SW;
727 device_printf(sc->sc_dev, "Invalid wire config\n");
735 ti_adc_probe(device_t dev)
738 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc"))
740 device_set_desc(dev, "TI ADC controller");
742 return (BUS_PROBE_DEFAULT);
746 ti_adc_attach(device_t dev)
749 struct ti_adc_softc *sc;
751 phandle_t node, child;
757 sc = device_get_softc(dev);
760 node = ofw_bus_get_node(dev);
762 sc->sc_tsc_wires = 0;
763 sc->sc_coord_readouts = 1;
764 sc->sc_x_plate_resistance = 0;
765 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY;
766 /* Read "tsc" node properties */
767 child = ofw_bus_find_child(node, "tsc");
768 if (child != 0 && OF_hasprop(child, "ti,wires")) {
769 if ((OF_getencprop(child, "ti,wires", &cell, sizeof(cell))) > 0)
770 sc->sc_tsc_wires = cell;
771 if ((OF_getencprop(child, "ti,coordinate-readouts", &cell,
773 sc->sc_coord_readouts = cell;
774 if ((OF_getencprop(child, "ti,x-plate-resistance", &cell,
776 sc->sc_x_plate_resistance = cell;
777 if ((OF_getencprop(child, "ti,charge-delay", &cell,
779 sc->sc_charge_delay = cell;
780 nwire_configs = OF_getencprop_alloc_multi(child,
781 "ti,wire-config", sizeof(*wire_configs),
782 (void **)&wire_configs);
783 if (nwire_configs != sc->sc_tsc_wires) {
784 device_printf(sc->sc_dev,
785 "invalid number of ti,wire-config: %d (should be %d)\n",
786 nwire_configs, sc->sc_tsc_wires);
787 OF_prop_free(wire_configs);
790 err = ti_adc_config_wires(sc, wire_configs, nwire_configs);
791 OF_prop_free(wire_configs);
796 /* Read "adc" node properties */
797 child = ofw_bus_find_child(node, "adc");
799 sc->sc_adc_nchannels = OF_getencprop_alloc_multi(child,
800 "ti,adc-channels", sizeof(*channels), (void **)&channels);
801 if (sc->sc_adc_nchannels > 0) {
802 for (i = 0; i < sc->sc_adc_nchannels; i++)
803 sc->sc_adc_channels[i] = channels[i];
804 OF_prop_free(channels);
808 /* Sanity check FDT data */
809 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) {
810 device_printf(dev, "total number of chanels (%d) is larger than %d\n",
811 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS);
816 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
818 if (!sc->sc_mem_res) {
819 device_printf(dev, "cannot allocate memory window\n");
823 /* Activate the ADC_TSC module. */
824 err = ti_prcm_clk_enable(TSC_ADC_CLK);
829 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
831 if (!sc->sc_irq_res) {
832 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
833 device_printf(dev, "cannot allocate interrupt\n");
837 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
838 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
839 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
840 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
841 device_printf(dev, "Unable to setup the irq handler.\n");
845 /* Check the ADC revision. */
846 rev = ADC_READ4(sc, ADC_REVISION);
848 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
849 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
850 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
851 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
852 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
853 rev & ADC_REV_MINOR_MSK,
854 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
856 reg = ADC_READ4(sc, ADC_CTRL);
857 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
860 * Set the ADC prescaler to 2400 if touchscreen is not enabled
861 * and to 24 if it is. This sets the ADC clock to ~10Khz and
862 * ~1Mhz respectively (CLK_M_OSC / prescaler).
864 if (sc->sc_tsc_wires)
865 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1);
867 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1);
869 TI_ADC_LOCK_INIT(sc);
871 ti_adc_idlestep_init(sc);
872 ti_adc_inputs_init(sc);
873 ti_adc_sysctl_init(sc);
881 if (sc->sc_tsc_wires > 0) {
882 sc->sc_evdev = evdev_alloc();
883 evdev_set_name(sc->sc_evdev, device_get_desc(dev));
884 evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev));
885 evdev_set_id(sc->sc_evdev, BUS_VIRTUAL, 0, 0, 0);
886 evdev_support_prop(sc->sc_evdev, INPUT_PROP_DIRECT);
887 evdev_support_event(sc->sc_evdev, EV_SYN);
888 evdev_support_event(sc->sc_evdev, EV_ABS);
889 evdev_support_event(sc->sc_evdev, EV_KEY);
891 evdev_support_abs(sc->sc_evdev, ABS_X, 0, 0,
892 ADC_MAX_VALUE, 0, 0, 0);
893 evdev_support_abs(sc->sc_evdev, ABS_Y, 0, 0,
894 ADC_MAX_VALUE, 0, 0, 0);
896 evdev_support_key(sc->sc_evdev, BTN_TOUCH);
898 err = evdev_register(sc->sc_evdev);
901 "failed to register evdev: error=%d\n", err);
916 ti_adc_detach(device_t dev)
918 struct ti_adc_softc *sc;
920 sc = device_get_softc(dev);
922 /* Turn off the ADC. */
928 evdev_free(sc->sc_evdev);
933 TI_ADC_LOCK_DESTROY(sc);
936 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
938 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
940 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
942 return (bus_generic_detach(dev));
945 static device_method_t ti_adc_methods[] = {
946 DEVMETHOD(device_probe, ti_adc_probe),
947 DEVMETHOD(device_attach, ti_adc_attach),
948 DEVMETHOD(device_detach, ti_adc_detach),
953 static driver_t ti_adc_driver = {
956 sizeof(struct ti_adc_softc),
959 static devclass_t ti_adc_devclass;
961 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0);
962 MODULE_VERSION(ti_adc, 1);
963 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1);
965 MODULE_DEPEND(ti_adc, evdev, 1, 1, 1);