2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define ADC_REVISION 0x000
33 #define ADC_REV_SCHEME_MSK 0xc0000000
34 #define ADC_REV_SCHEME_SHIFT 30
35 #define ADC_REV_FUNC_MSK 0x0fff0000
36 #define ADC_REV_FUNC_SHIFT 16
37 #define ADC_REV_RTL_MSK 0x0000f800
38 #define ADC_REV_RTL_SHIFT 11
39 #define ADC_REV_MAJOR_MSK 0x00000700
40 #define ADC_REV_MAJOR_SHIFT 8
41 #define ADC_REV_CUSTOM_MSK 0x000000c0
42 #define ADC_REV_CUSTOM_SHIFT 6
43 #define ADC_REV_MINOR_MSK 0x0000003f
44 #define ADC_SYSCFG 0x010
45 #define ADC_SYSCFG_IDLE_MSK 0x000000c0
46 #define ADC_SYSCFG_IDLE_SHIFT 2
47 #define ADC_IRQSTATUS_RAW 0x024
48 #define ADC_IRQSTATUS 0x028
49 #define ADC_IRQENABLE_SET 0x02c
50 #define ADC_IRQENABLE_CLR 0x030
51 #define ADC_IRQ_HW_PEN_SYNC (1 << 10)
52 #define ADC_IRQ_PEN_UP (1 << 9)
53 #define ADC_IRQ_OUT_RANGE (1 << 8)
54 #define ADC_IRQ_FIFO1_UNDR (1 << 7)
55 #define ADC_IRQ_FIFO1_OVERR (1 << 6)
56 #define ADC_IRQ_FIFO1_THRES (1 << 5)
57 #define ADC_IRQ_FIFO0_UNDR (1 << 4)
58 #define ADC_IRQ_FIFO0_OVERR (1 << 3)
59 #define ADC_IRQ_FIFO0_THRES (1 << 2)
60 #define ADC_IRQ_END_OF_SEQ (1 << 1)
61 #define ADC_IRQ_HW_PEN_ASYNC (1 << 0)
62 #define ADC_CTRL 0x040
63 #define ADC_CTRL_TSC_ENABLE (1 << 7)
64 #define ADC_CTRL_TSC_4WIRE (1 << 5)
65 #define ADC_CTRL_TSC_5WIRE (2 << 5)
66 #define ADC_CTRL_TSC_8WIRE (3 << 5)
67 #define ADC_CTRL_STEP_WP (1 << 2)
68 #define ADC_CTRL_STEP_ID (1 << 1)
69 #define ADC_CTRL_ENABLE (1 << 0)
70 #define ADC_STAT 0x044
71 #define ADC_CLKDIV 0x04c
72 #define ADC_STEPENABLE 0x054
73 #define ADC_IDLECONFIG 0x058
74 #define ADC_TC_CHARGE_STEPCONFIG 0x05C
75 #define ADC_TC_CHARGE_DELAY 0x060
77 #define ADC_STEPCFG(n) (0x064 + (8*((n)-1)))
78 #define ADC_STEPDLY(n) (0x068 + (8*((n)-1)))
79 #define ADC_STEP_FIFO1 (1 << 26)
80 #define ADC_STEP_DIFF_CNTRL (1 << 25)
81 #define ADC_STEP_RFM_MSK 0x01800000
82 #define ADC_STEP_RFM_SHIFT 23
83 #define ADC_STEP_RFM_VSSA 0
84 #define ADC_STEP_RFM_XNUR 1
85 #define ADC_STEP_RFM_YNLR 2
86 #define ADC_STEP_RFM_VREFN 3
87 #define ADC_STEP_INP_MSK 0x00780000
88 #define ADC_STEP_INP_SHIFT 19
89 #define ADC_STEP_INP(i) ((i) << ADC_STEP_INP_SHIFT)
90 #define ADC_STEP_INM_MSK 0x00078000
91 #define ADC_STEP_INM_SHIFT 15
92 #define ADC_STEP_INM(i) ((i) << ADC_STEP_INM_SHIFT)
93 #define ADC_STEP_IN_VREFN 8
94 #define ADC_STEP_RFP_MSK 0x00007000
95 #define ADC_STEP_RFP_SHIFT 12
96 #define ADC_STEP_RFP_VDDA 0
97 #define ADC_STEP_RFP_XPUL 1
98 #define ADC_STEP_RFP_YPLL 2
99 #define ADC_STEP_RFP_VREFP 3
100 #define ADC_STEP_RFP_INTREF 4
101 #define ADC_STEP_YPN_SW (1 << 10)
102 #define ADC_STEP_YNN_SW (1 << 8)
103 #define ADC_STEP_YPP_SW (1 << 7)
104 #define ADC_STEP_XNN_SW (1 << 6)
105 #define ADC_STEP_XPP_SW (1 << 5)
106 #define ADC_STEP_AVG_MSK 0x0000001c
107 #define ADC_STEP_AVG_SHIFT 2
108 #define ADC_STEP_MODE_MSK 0x00000003
109 #define ADC_STEP_MODE_ONESHOT 0x00000000
110 #define ADC_STEP_MODE_CONTINUOUS 0x00000001
111 #define ADC_STEP_MODE_HW_ONESHOT 0x00000002
112 #define ADC_STEP_MODE_HW_CONTINUOUS 0x00000003
113 #define ADC_STEP_SAMPLE_DELAY 0xff000000
114 #define ADC_STEP_OPEN_DELAY 0x0003ffff
115 #define ADC_FIFO0COUNT 0x0e4
116 #define ADC_FIFO0THRESHOLD 0x0e8
117 #define ADC_FIFO1COUNT 0x0f0
118 #define ADC_FIFO1THRESHOLD 0x0f4
119 #define ADC_FIFO0DATA 0x100
120 #define ADC_FIFO1DATA 0x200
121 #define ADC_FIFO_COUNT_MSK 0x0000007f
122 #define ADC_FIFO_STEP_ID_MSK 0x000f0000
123 #define ADC_FIFO_STEP_ID_SHIFT 16
124 #define ADC_FIFO_DATA_MSK 0x00000fff
125 #define ADC_MAX_VALUE 0xfff
127 #endif /* _TI_ADCREG_H_ */