3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's.
31 * Currently this driver only does the basics, get a value on a pin & set a
32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic
33 * and support interrupts and other various bits on the SoC can do ... in the
34 * meantime this is all you get.
36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
53 #include <sys/mutex.h>
56 #include <machine/bus.h>
57 #include <machine/resource.h>
59 #include <arm/ti/ti_cpuid.h>
60 #include <arm/ti/ti_gpio.h>
61 #include <arm/ti/ti_scm.h>
62 #include <arm/ti/ti_prcm.h>
64 #include <dev/fdt/fdt_common.h>
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
70 #include "ti_gpio_if.h"
72 /* Register definitions */
73 #define TI_GPIO_REVISION 0x0000
74 #define TI_GPIO_SYSCONFIG 0x0010
75 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
76 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
77 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
78 #define TI_GPIO_IRQSTATUS_0 0x002C
79 #define TI_GPIO_IRQSTATUS_1 0x0030
80 #define TI_GPIO_IRQSTATUS_SET_0 0x0034
81 #define TI_GPIO_IRQSTATUS_SET_1 0x0038
82 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C
83 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040
84 #define TI_GPIO_IRQWAKEN_0 0x0044
85 #define TI_GPIO_IRQWAKEN_1 0x0048
86 #define TI_GPIO_SYSSTATUS 0x0114
87 #define TI_GPIO_IRQSTATUS1 0x0118
88 #define TI_GPIO_IRQENABLE1 0x011C
89 #define TI_GPIO_WAKEUPENABLE 0x0120
90 #define TI_GPIO_IRQSTATUS2 0x0128
91 #define TI_GPIO_IRQENABLE2 0x012C
92 #define TI_GPIO_CTRL 0x0130
93 #define TI_GPIO_OE 0x0134
94 #define TI_GPIO_DATAIN 0x0138
95 #define TI_GPIO_DATAOUT 0x013C
96 #define TI_GPIO_LEVELDETECT0 0x0140
97 #define TI_GPIO_LEVELDETECT1 0x0144
98 #define TI_GPIO_RISINGDETECT 0x0148
99 #define TI_GPIO_FALLINGDETECT 0x014C
100 #define TI_GPIO_DEBOUNCENABLE 0x0150
101 #define TI_GPIO_DEBOUNCINGTIME 0x0154
102 #define TI_GPIO_CLEARWKUPENA 0x0180
103 #define TI_GPIO_SETWKUENA 0x0184
104 #define TI_GPIO_CLEARDATAOUT 0x0190
105 #define TI_GPIO_SETDATAOUT 0x0194
110 /* Other SoC Specific definitions */
111 #define OMAP4_MAX_GPIO_BANKS 6
112 #define OMAP4_FIRST_GPIO_BANK 1
113 #define OMAP4_INTR_PER_BANK 1
114 #define OMAP4_GPIO_REV 0x50600801
115 #define AM335X_MAX_GPIO_BANKS 4
116 #define AM335X_FIRST_GPIO_BANK 0
117 #define AM335X_INTR_PER_BANK 2
118 #define AM335X_GPIO_REV 0x50600801
119 #define PINS_PER_BANK 32
122 ti_max_gpio_banks(void)
127 return (OMAP4_MAX_GPIO_BANKS);
131 return (AM335X_MAX_GPIO_BANKS);
138 ti_max_gpio_intrs(void)
143 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK);
147 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK);
154 ti_first_gpio_bank(void)
159 return (OMAP4_FIRST_GPIO_BANK);
163 return (AM335X_FIRST_GPIO_BANK);
175 return (OMAP4_GPIO_REV);
179 return (AM335X_GPIO_REV);
186 * ti_gpio_mem_spec - Resource specification used when allocating resources
187 * ti_gpio_irq_spec - Resource specification used when allocating resources
189 * This driver module can have up to six independent memory regions, each
190 * region typically controls 32 GPIO pins.
192 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
193 * but there are two set of registers which control the interrupt delivery
194 * to internal subsystems. The first set of registers control the
195 * interrupts delivery to the MPU and the second set control the
196 * interrupts delivery to the DSP.
198 * On AM335x there are two physical interrupt lines for each GPIO module.
199 * Each interrupt line is controlled by a set of registers.
201 static struct resource_spec ti_gpio_mem_spec[] = {
202 { SYS_RES_MEMORY, 0, RF_ACTIVE },
203 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
204 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
205 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
206 #if !defined(SOC_TI_AM335X)
207 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
208 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
212 static struct resource_spec ti_gpio_irq_spec[] = {
213 { SYS_RES_IRQ, 0, RF_ACTIVE },
214 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
215 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
216 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
217 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
218 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
219 #if defined(SOC_TI_AM335X)
220 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
221 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
227 * Macros for driver mutex locking
229 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
230 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
231 #define TI_GPIO_LOCK_INIT(_sc) \
232 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
234 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
235 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
236 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
239 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers
240 * @sc: GPIO device context
241 * @bank: The bank to read from
242 * @off: The offset of a register from the GPIO register address range
246 * 32-bit value read from the register.
248 static inline uint32_t
249 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
251 return (bus_read_4(sc->sc_mem_res[bank], off));
255 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers
256 * @sc: GPIO device context
257 * @bank: The bank to write to
258 * @off: The offset of a register from the GPIO register address range
259 * @val: The value to write into the register
265 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
268 bus_write_4(sc->sc_mem_res[bank], off, val);
272 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
275 /* We clear both set of registers. */
276 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
277 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
278 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
280 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask);
281 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask);
286 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
287 * @dev: gpio device handle
288 * @maxpin: pointer to a value that upon return will contain the maximum number
289 * of pins in the device.
293 * Internally locks the context
296 * Returns 0 on success otherwise an error code
299 ti_gpio_pin_max(device_t dev, int *maxpin)
301 struct ti_gpio_softc *sc = device_get_softc(dev);
303 unsigned int banks = 0;
307 /* Calculate how many valid banks we have and then multiply that by 32 to
308 * give use the total number of pins.
310 for (i = 0; i < ti_max_gpio_banks(); i++) {
311 if (sc->sc_mem_res[i] != NULL)
315 *maxpin = (banks * PINS_PER_BANK) - 1;
323 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
324 * @dev: gpio device handle
325 * @pin: the number of the pin
326 * @caps: pointer to a value that upon return will contain the capabilities
328 * Currently all pins have the same capability, notably:
332 * - GPIO_PIN_PULLDOWN
335 * Internally locks the context
338 * Returns 0 on success otherwise an error code
341 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
343 struct ti_gpio_softc *sc = device_get_softc(dev);
344 uint32_t bank = (pin / PINS_PER_BANK);
348 /* Sanity check the pin number is valid */
349 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
354 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP |
363 * ti_gpio_pin_getflags - Gets the current flags of a given pin
364 * @dev: gpio device handle
365 * @pin: the number of the pin
366 * @flags: upon return will contain the current flags of the pin
368 * Reads the current flags of a given pin, here we actually read the H/W
369 * registers to determine the flags, rather than storing the value in the
373 * Internally locks the context
376 * Returns 0 on success otherwise an error code
379 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
381 struct ti_gpio_softc *sc = device_get_softc(dev);
382 uint32_t bank = (pin / PINS_PER_BANK);
386 /* Sanity check the pin number is valid */
387 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
392 /* Get the current pin state */
393 TI_GPIO_GET_FLAGS(dev, pin, flags);
401 * ti_gpio_pin_getname - Gets the name of a given pin
402 * @dev: gpio device handle
403 * @pin: the number of the pin
404 * @name: buffer to put the name in
406 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
410 * Internally locks the context
413 * Returns 0 on success otherwise an error code
416 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
418 struct ti_gpio_softc *sc = device_get_softc(dev);
419 uint32_t bank = (pin / PINS_PER_BANK);
423 /* Sanity check the pin number is valid */
424 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
429 /* Set a very simple name */
430 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
431 name[GPIOMAXNAME - 1] = '\0';
439 * ti_gpio_pin_setflags - Sets the flags for a given pin
440 * @dev: gpio device handle
441 * @pin: the number of the pin
442 * @flags: the flags to set
444 * The flags of the pin correspond to things like input/output mode, pull-ups,
445 * pull-downs, etc. This driver doesn't support all flags, only the following:
449 * - GPIO_PIN_PULLDOWN
452 * Internally locks the context
455 * Returns 0 on success otherwise an error code
458 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
460 struct ti_gpio_softc *sc = device_get_softc(dev);
461 uint32_t bank = (pin / PINS_PER_BANK);
462 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
467 /* Sanity check the pin number is valid */
468 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
473 /* Set the GPIO mode and state */
474 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
479 /* If configuring as an output set the "output enable" bit */
480 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
481 if (flags & GPIO_PIN_INPUT)
485 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val);
493 * ti_gpio_pin_set - Sets the current level on a GPIO pin
494 * @dev: gpio device handle
495 * @pin: the number of the pin
496 * @value: non-zero value will drive the pin high, otherwise the pin is
501 * Internally locks the context
504 * Returns 0 on success otherwise a error code
507 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
509 struct ti_gpio_softc *sc = device_get_softc(dev);
510 uint32_t bank = (pin / PINS_PER_BANK);
511 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
515 /* Sanity check the pin number is valid */
516 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
521 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT
522 : TI_GPIO_SETDATAOUT, mask);
530 * ti_gpio_pin_get - Gets the current level on a GPIO pin
531 * @dev: gpio device handle
532 * @pin: the number of the pin
533 * @value: pointer to a value that upond return will contain the pin value
535 * The pin must be configured as an input pin beforehand, otherwise this
536 * function will fail.
539 * Internally locks the context
542 * Returns 0 on success otherwise a error code
545 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
547 struct ti_gpio_softc *sc = device_get_softc(dev);
548 uint32_t bank = (pin / PINS_PER_BANK);
549 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
554 /* Sanity check the pin number is valid */
555 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
560 /* Sanity check the pin is not configured as an output */
561 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
563 /* Read the value on the pin */
565 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0;
567 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0;
575 * ti_gpio_pin_toggle - Toggles a given GPIO pin
576 * @dev: gpio device handle
577 * @pin: the number of the pin
581 * Internally locks the context
584 * Returns 0 on success otherwise a error code
587 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
589 struct ti_gpio_softc *sc = device_get_softc(dev);
590 uint32_t bank = (pin / PINS_PER_BANK);
591 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
596 /* Sanity check the pin number is valid */
597 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
603 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
605 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask);
607 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask);
615 * ti_gpio_intr - ISR for all GPIO modules
616 * @arg: the soft context pointer
621 * Internally locks the context
625 ti_gpio_intr(void *arg)
627 struct ti_gpio_softc *sc = arg;
630 /* TODO: something useful */
635 ti_gpio_attach_intr(device_t dev)
638 struct ti_gpio_softc *sc;
640 sc = device_get_softc(dev);
641 for (i = 0; i < ti_max_gpio_intrs(); i++) {
642 if (sc->sc_irq_res[i] == NULL)
646 * Register our interrupt handler for each of the IRQ resources.
648 if (bus_setup_intr(dev, sc->sc_irq_res[i],
649 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
650 &sc->sc_irq_hdl[i]) != 0) {
652 "WARNING: unable to register interrupt handler\n");
661 ti_gpio_detach_intr(device_t dev)
664 struct ti_gpio_softc *sc;
666 /* Teardown our interrupt handlers. */
667 sc = device_get_softc(dev);
668 for (i = 0; i < ti_max_gpio_intrs(); i++) {
669 if (sc->sc_irq_res[i] == NULL)
672 if (sc->sc_irq_hdl[i]) {
673 bus_teardown_intr(dev, sc->sc_irq_res[i],
682 ti_gpio_bank_init(device_t dev, int bank)
685 struct ti_gpio_softc *sc;
686 uint32_t flags, reg_oe;
688 sc = device_get_softc(dev);
690 /* Enable the interface and functional clocks for the module. */
691 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank);
694 * Read the revision number of the module. TI don't publish the
695 * actual revision numbers, so instead the values have been
696 * determined by experimentation.
698 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
700 /* Check the revision. */
701 if (sc->sc_revision[bank] != ti_gpio_rev()) {
702 device_printf(dev, "Warning: could not determine the revision "
703 "of %u GPIO module (revision:0x%08x)\n",
704 bank, sc->sc_revision[bank]);
708 /* Disable interrupts for all pins. */
709 ti_gpio_intr_clr(sc, bank, 0xffffffff);
711 /* Init OE register based on pads configuration. */
713 for (pin = 0; pin < PINS_PER_BANK; pin++) {
714 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags);
715 if (flags & GPIO_PIN_OUTPUT)
716 reg_oe &= ~(1UL << pin);
718 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
724 * ti_gpio_attach - attach function for the driver
725 * @dev: gpio device handle
727 * Allocates and sets up the driver context for all GPIO banks. This function
728 * expects the memory ranges and IRQs to already be allocated to the driver.
737 ti_gpio_attach(device_t dev)
739 struct ti_gpio_softc *sc;
743 sc = device_get_softc(dev);
746 TI_GPIO_LOCK_INIT(sc);
748 /* There are up to 6 different GPIO register sets located in different
749 * memory areas on the chip. The memory range should have been set for
750 * the driver when it was added as a child.
752 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
753 device_printf(dev, "Error: could not allocate mem resources\n");
757 /* Request the IRQ resources */
758 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
759 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
760 device_printf(dev, "Error: could not allocate irq resources\n");
764 /* Setup the IRQ resources */
765 if (ti_gpio_attach_intr(dev) != 0) {
766 ti_gpio_detach_intr(dev);
767 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
768 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
772 /* We need to go through each block and ensure the clocks are running and
773 * the module is enabled. It might be better to do this only when the
774 * pins are configured which would result in less power used if the GPIO
775 * pins weren't used ...
777 for (i = 0; i < ti_max_gpio_banks(); i++) {
778 if (sc->sc_mem_res[i] != NULL) {
779 /* Initialize the GPIO module. */
780 err = ti_gpio_bank_init(dev, i);
782 ti_gpio_detach_intr(dev);
783 bus_release_resources(dev, ti_gpio_irq_spec,
785 bus_release_resources(dev, ti_gpio_mem_spec,
792 /* Finish of the probe call */
793 device_add_child(dev, "gpioc", -1);
794 device_add_child(dev, "gpiobus", -1);
796 return (bus_generic_attach(dev));
800 * ti_gpio_detach - detach function for the driver
801 * @dev: scm device handle
803 * Allocates and sets up the driver context, this simply entails creating a
804 * bus mappings for the SCM register set.
813 ti_gpio_detach(device_t dev)
815 struct ti_gpio_softc *sc = device_get_softc(dev);
818 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
820 /* Disable all interrupts */
821 for (i = 0; i < ti_max_gpio_banks(); i++) {
822 if (sc->sc_mem_res[i] != NULL)
823 ti_gpio_intr_clr(sc, i, 0xffffffff);
826 bus_generic_detach(dev);
828 /* Release the memory and IRQ resources. */
829 ti_gpio_detach_intr(dev);
830 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
831 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
833 TI_GPIO_LOCK_DESTROY(sc);
839 ti_gpio_get_node(device_t bus, device_t dev)
842 /* We only have one child, the GPIO bus, which needs our own node. */
843 return (ofw_bus_get_node(bus));
846 static device_method_t ti_gpio_methods[] = {
847 DEVMETHOD(device_attach, ti_gpio_attach),
848 DEVMETHOD(device_detach, ti_gpio_detach),
851 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
852 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
853 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
854 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
855 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
856 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
857 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
858 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
860 /* ofw_bus interface */
861 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
866 driver_t ti_gpio_driver = {
869 sizeof(struct ti_gpio_softc),