2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
35 #include <sys/cdefs.h>
36 #include "opt_platform.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
47 #include <sys/mutex.h>
49 #include <sys/interrupt.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
53 #include <machine/resource.h>
55 #include <arm/ti/ti_cpuid.h>
56 #include <arm/ti/ti_gpio.h>
57 #include <arm/ti/ti_scm.h>
58 #include <arm/ti/ti_sysc.h>
60 #include <dev/gpio/gpiobusvar.h>
61 #include <dev/ofw/openfirm.h>
62 #include <dev/ofw/ofw_bus.h>
63 #include <dev/ofw/ofw_bus_subr.h>
66 #include "ti_gpio_if.h"
69 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
73 /* Register definitions */
74 #define TI_GPIO_REVISION 0x0000
75 #define TI_GPIO_SYSCONFIG 0x0010
76 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
77 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
78 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */
79 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */
80 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */
81 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */
82 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */
83 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */
84 #define TI_GPIO_IRQWAKEN_0 0x0044
85 #define TI_GPIO_IRQWAKEN_1 0x0048
86 #define TI_GPIO_SYSSTATUS 0x0114
87 #define TI_GPIO_IRQSTATUS1 0x0118
88 #define TI_GPIO_IRQENABLE1 0x011C
89 #define TI_GPIO_WAKEUPENABLE 0x0120
90 #define TI_GPIO_IRQSTATUS2 0x0128
91 #define TI_GPIO_IRQENABLE2 0x012C
92 #define TI_GPIO_CTRL 0x0130
93 #define TI_GPIO_OE 0x0134
94 #define TI_GPIO_DATAIN 0x0138
95 #define TI_GPIO_DATAOUT 0x013C
96 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */
97 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */
98 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */
99 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */
100 #define TI_GPIO_DEBOUNCENABLE 0x0150
101 #define TI_GPIO_DEBOUNCINGTIME 0x0154
102 #define TI_GPIO_CLEARWKUPENA 0x0180
103 #define TI_GPIO_SETWKUENA 0x0184
104 #define TI_GPIO_CLEARDATAOUT 0x0190
105 #define TI_GPIO_SETDATAOUT 0x0194
107 /* Other SoC Specific definitions */
108 #define OMAP4_FIRST_GPIO_BANK 1
109 #define OMAP4_INTR_PER_BANK 1
110 #define OMAP4_GPIO_REV 0x50600801
111 #define AM335X_FIRST_GPIO_BANK 0
112 #define AM335X_INTR_PER_BANK 2
113 #define AM335X_GPIO_REV 0x50600801
114 #define PINS_PER_BANK 32
115 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
117 #define OMAP4_GPIO1_REV 0x00000
118 #define OMAP4_GPIO2_REV 0x55000
119 #define OMAP4_GPIO3_REV 0x57000
120 #define OMAP4_GPIO4_REV 0x59000
121 #define OMAP4_GPIO5_REV 0x5b000
122 #define OMAP4_GPIO6_REV 0x5d000
124 #define AM335X_GPIO0_REV 0x07000
125 #define AM335X_GPIO1_REV 0x4C000
126 #define AM335X_GPIO2_REV 0xAC000
127 #define AM335X_GPIO3_REV 0xAE000
129 static int ti_gpio_intr(void *arg);
130 static int ti_gpio_detach(device_t);
132 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc);
133 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc);
141 return (OMAP4_GPIO_REV);
145 return (AM335X_GPIO_REV);
152 * Macros for driver mutex locking
154 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
155 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
156 #define TI_GPIO_LOCK_INIT(_sc) \
157 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
159 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
160 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
161 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
164 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
165 * @sc: GPIO device context
166 * @bank: The bank to read from
167 * @off: The offset of a register from the GPIO register address range
171 * 32-bit value read from the register.
173 static inline uint32_t
174 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
176 return (bus_read_4(sc->sc_mem_res, off));
180 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
181 * @sc: GPIO device context
182 * @bank: The bank to write to
183 * @off: The offset of a register from the GPIO register address range
184 * @val: The value to write into the register
190 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
193 bus_write_4(sc->sc_mem_res, off, val);
197 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
200 /* We clear both set of registers. */
201 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
202 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
206 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
210 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
211 * also activate only the first interrupt.
213 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
217 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
221 * Acknowledge the interrupt on both registers even if we use only
224 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
225 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
228 static inline uint32_t
229 ti_gpio_intr_status(struct ti_gpio_softc *sc)
233 /* Get the status from both registers. */
234 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
235 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
241 ti_gpio_get_bus(device_t dev)
243 struct ti_gpio_softc *sc;
245 sc = device_get_softc(dev);
247 return (sc->sc_busdev);
251 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
252 * @dev: gpio device handle
253 * @maxpin: pointer to a value that upon return will contain the maximum number
254 * of pins in the device.
258 * No locking required, returns static data.
261 * Returns 0 on success otherwise an error code
264 ti_gpio_pin_max(device_t dev, int *maxpin)
267 *maxpin = PINS_PER_BANK - 1;
273 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
276 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
283 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin
284 * @dev: gpio device handle
285 * @pin: the number of the pin
286 * @caps: pointer to a value that upon return will contain the capabilities
288 * Currently all pins have the same capability, notably:
292 * - GPIO_PIN_PULLDOWN
293 * - GPIO_INTR_LEVEL_LOW
294 * - GPIO_INTR_LEVEL_HIGH
295 * - GPIO_INTR_EDGE_RISING
296 * - GPIO_INTR_EDGE_FALLING
297 * - GPIO_INTR_EDGE_BOTH
300 * No locking required, returns static data.
303 * Returns 0 on success otherwise an error code
306 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
308 struct ti_gpio_softc *sc;
310 sc = device_get_softc(dev);
311 if (ti_gpio_valid_pin(sc, pin) != 0)
314 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
315 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
316 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
317 GPIO_INTR_EDGE_BOTH);
323 * ti_gpio_pin_getflags - Gets the current flags of a given pin
324 * @dev: gpio device handle
325 * @pin: the number of the pin
326 * @flags: upon return will contain the current flags of the pin
328 * Reads the current flags of a given pin, here we actually read the H/W
329 * registers to determine the flags, rather than storing the value in the
333 * Internally locks the context
336 * Returns 0 on success otherwise an error code
339 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
341 struct ti_gpio_softc *sc;
343 sc = device_get_softc(dev);
344 if (ti_gpio_valid_pin(sc, pin) != 0)
347 /* Get the current pin state */
349 TI_GPIO_GET_FLAGS(dev, pin, flags);
356 * ti_gpio_pin_getname - Gets the name of a given pin
357 * @dev: gpio device handle
358 * @pin: the number of the pin
359 * @name: buffer to put the name in
361 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
365 * No locking required, returns static data.
368 * Returns 0 on success otherwise an error code
371 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
373 struct ti_gpio_softc *sc;
375 sc = device_get_softc(dev);
376 if (ti_gpio_valid_pin(sc, pin) != 0)
379 /* Set a very simple name */
380 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
381 name[GPIOMAXNAME - 1] = '\0';
387 * ti_gpio_pin_setflags - Sets the flags for a given pin
388 * @dev: gpio device handle
389 * @pin: the number of the pin
390 * @flags: the flags to set
392 * The flags of the pin correspond to things like input/output mode, pull-ups,
393 * pull-downs, etc. This driver doesn't support all flags, only the following:
397 * - GPIO_PIN_PULLDOWN
400 * Internally locks the context
403 * Returns 0 on success otherwise an error code
406 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
408 struct ti_gpio_softc *sc;
411 sc = device_get_softc(dev);
412 if (ti_gpio_valid_pin(sc, pin) != 0)
415 /* Set the GPIO mode and state */
417 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
422 /* If configuring as an output set the "output enable" bit */
423 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
424 if (flags & GPIO_PIN_INPUT)
425 oe |= TI_GPIO_MASK(pin);
427 oe &= ~TI_GPIO_MASK(pin);
428 ti_gpio_write_4(sc, TI_GPIO_OE, oe);
435 * ti_gpio_pin_set - Sets the current level on a GPIO pin
436 * @dev: gpio device handle
437 * @pin: the number of the pin
438 * @value: non-zero value will drive the pin high, otherwise the pin is
443 * Internally locks the context
446 * Returns 0 on success otherwise a error code
449 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
451 struct ti_gpio_softc *sc;
454 sc = device_get_softc(dev);
455 if (ti_gpio_valid_pin(sc, pin) != 0)
459 if (value == GPIO_PIN_LOW)
460 reg = TI_GPIO_CLEARDATAOUT;
462 reg = TI_GPIO_SETDATAOUT;
463 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
470 * ti_gpio_pin_get - Gets the current level on a GPIO pin
471 * @dev: gpio device handle
472 * @pin: the number of the pin
473 * @value: pointer to a value that upond return will contain the pin value
475 * The pin must be configured as an input pin beforehand, otherwise this
476 * function will fail.
479 * Internally locks the context
482 * Returns 0 on success otherwise a error code
485 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
487 struct ti_gpio_softc *sc;
488 uint32_t oe, reg, val;
490 sc = device_get_softc(dev);
491 if (ti_gpio_valid_pin(sc, pin) != 0)
495 * Return data from output latch when set as output and from the
496 * input register otherwise.
499 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
500 if (oe & TI_GPIO_MASK(pin))
501 reg = TI_GPIO_DATAIN;
503 reg = TI_GPIO_DATAOUT;
504 val = ti_gpio_read_4(sc, reg);
505 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
512 * ti_gpio_pin_toggle - Toggles a given GPIO pin
513 * @dev: gpio device handle
514 * @pin: the number of the pin
518 * Internally locks the context
521 * Returns 0 on success otherwise a error code
524 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
526 struct ti_gpio_softc *sc;
529 sc = device_get_softc(dev);
530 if (ti_gpio_valid_pin(sc, pin) != 0)
535 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
536 if (val & TI_GPIO_MASK(pin))
537 reg = TI_GPIO_CLEARDATAOUT;
539 reg = TI_GPIO_SETDATAOUT;
540 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
547 ti_gpio_bank_init(device_t dev)
550 struct ti_gpio_softc *sc;
551 uint32_t flags, reg_oe, reg_set, rev;
552 uint64_t rev_address;
554 sc = device_get_softc(dev);
556 /* Enable the interface and functional clocks for the module. */
557 rev_address = ti_sysc_get_rev_address(device_get_parent(dev));
559 * sc->sc_bank used in am335x/am335x_gpio.c and omap4/omap4_gpio.c */
563 switch (rev_address) {
564 case OMAP4_GPIO1_REV:
567 case OMAP4_GPIO2_REV:
570 case OMAP4_GPIO3_REV:
573 case OMAP4_GPIO4_REV:
576 case OMAP4_GPIO5_REV:
579 case OMAP4_GPIO6_REV:
586 switch (rev_address) {
587 case AM335X_GPIO0_REV:
590 case AM335X_GPIO1_REV:
593 case AM335X_GPIO2_REV:
596 case AM335X_GPIO3_REV:
602 err = ti_sysc_clock_enable(device_get_parent(dev));
604 device_printf(dev, "Failed to enable clock\n");
609 * Read the revision number of the module. TI don't publish the
610 * actual revision numbers, so instead the values have been
611 * determined by experimentation.
613 rev = ti_gpio_read_4(sc,
614 ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));
616 /* Check the revision. */
617 if (rev != ti_gpio_rev()) {
618 device_printf(dev, "Warning: could not determine the revision "
619 "of GPIO module (revision:0x%08x)\n", rev);
623 /* Disable interrupts for all pins. */
624 ti_gpio_intr_clr(sc, 0xffffffff);
626 /* Init OE register based on pads configuration. */
629 for (pin = 0; pin < PINS_PER_BANK; pin++) {
630 TI_GPIO_GET_FLAGS(dev, pin, &flags);
631 if (flags & GPIO_PIN_OUTPUT) {
632 reg_oe &= ~(1UL << pin);
633 if (flags & GPIO_PIN_PULLUP)
634 reg_set |= (1UL << pin);
637 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
639 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set);
645 * ti_gpio_attach - attach function for the driver
646 * @dev: gpio device handle
648 * Allocates and sets up the driver context for all GPIO banks. This function
649 * expects the memory ranges and IRQs to already be allocated to the driver.
658 ti_gpio_attach(device_t dev)
660 struct ti_gpio_softc *sc;
663 sc = device_get_softc(dev);
665 TI_GPIO_LOCK_INIT(sc);
666 ti_gpio_pin_max(dev, &sc->sc_maxpin);
670 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
671 &sc->sc_mem_rid, RF_ACTIVE);
672 if (!sc->sc_mem_res) {
673 device_printf(dev, "Error: could not allocate mem resources\n");
679 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
680 &sc->sc_irq_rid, RF_ACTIVE);
681 if (!sc->sc_irq_res) {
682 device_printf(dev, "Error: could not allocate irq resources\n");
688 * Register our interrupt filter for each of the IRQ resources.
690 if (bus_setup_intr(dev, sc->sc_irq_res,
691 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
692 &sc->sc_irq_hdl) != 0) {
694 "WARNING: unable to register interrupt filter\n");
699 if (ti_gpio_pic_attach(sc) != 0) {
700 device_printf(dev, "WARNING: unable to attach PIC\n");
705 /* We need to go through each block and ensure the clocks are running and
706 * the module is enabled. It might be better to do this only when the
707 * pins are configured which would result in less power used if the GPIO
708 * pins weren't used ...
710 if (sc->sc_mem_res != NULL) {
711 /* Initialize the GPIO module. */
712 err = ti_gpio_bank_init(dev);
719 sc->sc_busdev = gpiobus_attach_bus(dev);
720 if (sc->sc_busdev == NULL) {
729 * ti_gpio_detach - detach function for the driver
730 * @dev: scm device handle
732 * Allocates and sets up the driver context, this simply entails creating a
733 * bus mappings for the SCM register set.
742 ti_gpio_detach(device_t dev)
744 struct ti_gpio_softc *sc = device_get_softc(dev);
746 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
748 /* Disable all interrupts */
749 if (sc->sc_mem_res != NULL)
750 ti_gpio_intr_clr(sc, 0xffffffff);
751 if (sc->sc_busdev != NULL)
752 gpiobus_detach_bus(dev);
753 if (sc->sc_isrcs != NULL)
754 ti_gpio_pic_detach(sc);
755 /* Release the memory and IRQ resources. */
756 if (sc->sc_irq_hdl) {
757 bus_teardown_intr(dev, sc->sc_irq_res,
761 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
764 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
766 TI_GPIO_LOCK_DESTROY(sc);
772 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask,
777 value = ti_gpio_read_4(sc, reg);
778 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask);
782 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
785 /* Writing a 0 has no effect. */
786 ti_gpio_intr_clr(sc, tgi->tgi_mask);
790 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
793 /* Writing a 0 has no effect. */
794 ti_gpio_intr_set(sc, tgi->tgi_mask);
798 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
801 /* Writing a 0 has no effect. */
802 ti_gpio_intr_ack(sc, tgi->tgi_mask);
806 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi)
809 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW ||
810 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH);
814 ti_gpio_intr(void *arg)
818 struct ti_gpio_softc *sc;
819 struct trapframe *tf;
820 struct ti_gpio_irqsrc *tgi;
822 sc = (struct ti_gpio_softc *)arg;
823 tf = curthread->td_intr_frame;
825 reg = ti_gpio_intr_status(sc);
826 for (irq = 0; irq < sc->sc_maxpin; irq++) {
827 tgi = &sc->sc_isrcs[irq];
828 if ((reg & tgi->tgi_mask) == 0)
830 if (!ti_gpio_isrc_is_level(tgi))
831 ti_gpio_isrc_eoi(sc, tgi);
832 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {
833 ti_gpio_isrc_mask(sc, tgi);
834 if (ti_gpio_isrc_is_level(tgi))
835 ti_gpio_isrc_eoi(sc, tgi);
836 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
840 return (FILTER_HANDLED);
844 ti_gpio_pic_attach(struct ti_gpio_softc *sc)
850 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF,
853 name = device_get_nameunit(sc->sc_dev);
854 for (irq = 0; irq < sc->sc_maxpin; irq++) {
855 sc->sc_isrcs[irq].tgi_irq = irq;
856 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq);
857 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM;
859 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc,
860 sc->sc_dev, 0, "%s,%u", name, irq);
862 return (error); /* XXX deregister ISRCs */
864 if (intr_pic_register(sc->sc_dev,
865 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL)
872 ti_gpio_pic_detach(struct ti_gpio_softc *sc)
876 * There has not been established any procedure yet
877 * how to detach PIC from living system correctly.
879 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
884 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi,
889 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask,
890 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH);
891 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask,
892 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH);
893 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask,
894 mode == GPIO_INTR_LEVEL_HIGH);
895 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask,
896 mode == GPIO_INTR_LEVEL_LOW);
897 tgi->tgi_mode = mode;
902 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
904 struct ti_gpio_softc *sc = device_get_softc(dev);
905 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
907 ti_gpio_isrc_mask(sc, tgi);
911 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
913 struct ti_gpio_softc *sc = device_get_softc(dev);
914 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
916 arm_irq_memory_barrier(tgi->tgi_irq);
917 ti_gpio_isrc_unmask(sc, tgi);
921 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf,
922 u_int *irqp, uint32_t *modep)
927 * The first cell is the interrupt number.
928 * The second cell is used to specify flags:
929 * bits[3:0] trigger type and level flags:
930 * 1 = low-to-high edge triggered.
931 * 2 = high-to-low edge triggered.
932 * 4 = active high level-sensitive.
933 * 8 = active low level-sensitive.
935 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin)
938 /* Only reasonable modes are supported. */
939 if (daf->cells[1] == 1)
940 mode = GPIO_INTR_EDGE_RISING;
941 else if (daf->cells[1] == 2)
942 mode = GPIO_INTR_EDGE_FALLING;
943 else if (daf->cells[1] == 3)
944 mode = GPIO_INTR_EDGE_BOTH;
945 else if (daf->cells[1] == 4)
946 mode = GPIO_INTR_LEVEL_HIGH;
947 else if (daf->cells[1] == 8)
948 mode = GPIO_INTR_LEVEL_LOW;
952 *irqp = daf->cells[0];
959 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag,
960 u_int *irqp, uint32_t *modep)
964 if (dag->gpio_pin_num >= sc->sc_maxpin)
967 mode = dag->gpio_intr_mode;
968 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH &&
969 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING &&
970 mode != GPIO_INTR_EDGE_BOTH)
973 *irqp = dag->gpio_pin_num;
980 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data,
981 u_int *irqp, uint32_t *modep)
984 switch (data->type) {
985 case INTR_MAP_DATA_FDT:
986 return (ti_gpio_pic_map_fdt(sc,
987 (struct intr_map_data_fdt *)data, irqp, modep));
988 case INTR_MAP_DATA_GPIO:
989 return (ti_gpio_pic_map_gpio(sc,
990 (struct intr_map_data_gpio *)data, irqp, modep));
997 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
998 struct intr_irqsrc **isrcp)
1002 struct ti_gpio_softc *sc = device_get_softc(dev);
1004 error = ti_gpio_pic_map(sc, data, &irq, NULL);
1006 *isrcp = &sc->sc_isrcs[irq].tgi_isrc;
1011 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1013 struct ti_gpio_softc *sc = device_get_softc(dev);
1014 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1016 if (ti_gpio_isrc_is_level(tgi))
1017 ti_gpio_isrc_eoi(sc, tgi);
1021 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1024 ti_gpio_pic_enable_intr(dev, isrc);
1028 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1030 struct ti_gpio_softc *sc = device_get_softc(dev);
1031 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1033 ti_gpio_isrc_mask(sc, tgi);
1034 if (ti_gpio_isrc_is_level(tgi))
1035 ti_gpio_isrc_eoi(sc, tgi);
1039 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1040 struct resource *res, struct intr_map_data *data)
1044 struct ti_gpio_softc *sc;
1045 struct ti_gpio_irqsrc *tgi;
1050 sc = device_get_softc(dev);
1051 tgi = (struct ti_gpio_irqsrc *)isrc;
1053 /* Get and check config for an interrupt. */
1054 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq)
1058 * If this is a setup for another handler,
1059 * only check that its configuration match.
1061 if (isrc->isrc_handlers != 0)
1062 return (tgi->tgi_mode == mode ? 0 : EINVAL);
1064 ti_gpio_pic_config_intr(sc, tgi, mode);
1069 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1070 struct resource *res, struct intr_map_data *data)
1072 struct ti_gpio_softc *sc = device_get_softc(dev);
1073 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1075 if (isrc->isrc_handlers == 0)
1076 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM);
1081 ti_gpio_get_node(device_t bus, device_t dev)
1084 /* We only have one child, the GPIO bus, which needs our own node. */
1085 return (ofw_bus_get_node(bus));
1088 static device_method_t ti_gpio_methods[] = {
1089 DEVMETHOD(device_attach, ti_gpio_attach),
1090 DEVMETHOD(device_detach, ti_gpio_detach),
1093 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
1094 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
1095 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
1096 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
1097 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
1098 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
1099 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
1100 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
1101 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
1103 /* Interrupt controller interface */
1104 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr),
1105 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr),
1106 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr),
1107 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr),
1108 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr),
1109 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter),
1110 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread),
1111 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread),
1113 /* ofw_bus interface */
1114 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
1119 driver_t ti_gpio_driver = {
1122 sizeof(struct ti_gpio_softc),