3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's.
31 * Currently this driver only does the basics, get a value on a pin & set a
32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic
33 * and support interrupts and other various bits on the SoC can do ... in the
34 * meantime this is all you get.
36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
53 #include <sys/mutex.h>
56 #include <machine/bus.h>
57 #include <machine/resource.h>
59 #include <arm/ti/ti_cpuid.h>
60 #include <arm/ti/ti_gpio.h>
61 #include <arm/ti/ti_scm.h>
62 #include <arm/ti/ti_prcm.h>
64 #include <dev/fdt/fdt_common.h>
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
70 #include "ti_gpio_if.h"
72 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
76 /* Register definitions */
77 #define TI_GPIO_REVISION 0x0000
78 #define TI_GPIO_SYSCONFIG 0x0010
79 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
80 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
81 #define TI_GPIO_IRQSTATUS_0 0x002C
82 #define TI_GPIO_IRQSTATUS_1 0x0030
83 #define TI_GPIO_IRQSTATUS_SET_0 0x0034
84 #define TI_GPIO_IRQSTATUS_SET_1 0x0038
85 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C
86 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040
87 #define TI_GPIO_IRQWAKEN_0 0x0044
88 #define TI_GPIO_IRQWAKEN_1 0x0048
89 #define TI_GPIO_SYSSTATUS 0x0114
90 #define TI_GPIO_IRQSTATUS1 0x0118
91 #define TI_GPIO_IRQENABLE1 0x011C
92 #define TI_GPIO_WAKEUPENABLE 0x0120
93 #define TI_GPIO_IRQSTATUS2 0x0128
94 #define TI_GPIO_IRQENABLE2 0x012C
95 #define TI_GPIO_CTRL 0x0130
96 #define TI_GPIO_OE 0x0134
97 #define TI_GPIO_DATAIN 0x0138
98 #define TI_GPIO_DATAOUT 0x013C
99 #define TI_GPIO_LEVELDETECT0 0x0140
100 #define TI_GPIO_LEVELDETECT1 0x0144
101 #define TI_GPIO_RISINGDETECT 0x0148
102 #define TI_GPIO_FALLINGDETECT 0x014C
103 #define TI_GPIO_DEBOUNCENABLE 0x0150
104 #define TI_GPIO_DEBOUNCINGTIME 0x0154
105 #define TI_GPIO_CLEARWKUPENA 0x0180
106 #define TI_GPIO_SETWKUENA 0x0184
107 #define TI_GPIO_CLEARDATAOUT 0x0190
108 #define TI_GPIO_SETDATAOUT 0x0194
110 /* Other SoC Specific definitions */
111 #define OMAP4_MAX_GPIO_BANKS 6
112 #define OMAP4_FIRST_GPIO_BANK 1
113 #define OMAP4_INTR_PER_BANK 1
114 #define OMAP4_GPIO_REV 0x50600801
115 #define AM335X_MAX_GPIO_BANKS 4
116 #define AM335X_FIRST_GPIO_BANK 0
117 #define AM335X_INTR_PER_BANK 2
118 #define AM335X_GPIO_REV 0x50600801
119 #define PINS_PER_BANK 32
120 #define TI_GPIO_BANK(p) ((p) / PINS_PER_BANK)
121 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
124 ti_max_gpio_banks(void)
129 return (OMAP4_MAX_GPIO_BANKS);
133 return (AM335X_MAX_GPIO_BANKS);
140 ti_max_gpio_intrs(void)
145 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK);
149 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK);
156 ti_first_gpio_bank(void)
161 return (OMAP4_FIRST_GPIO_BANK);
165 return (AM335X_FIRST_GPIO_BANK);
177 return (OMAP4_GPIO_REV);
181 return (AM335X_GPIO_REV);
188 * ti_gpio_mem_spec - Resource specification used when allocating resources
189 * ti_gpio_irq_spec - Resource specification used when allocating resources
191 * This driver module can have up to six independent memory regions, each
192 * region typically controls 32 GPIO pins.
194 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
195 * but there are two set of registers which control the interrupt delivery
196 * to internal subsystems. The first set of registers control the
197 * interrupts delivery to the MPU and the second set control the
198 * interrupts delivery to the DSP.
200 * On AM335x there are two physical interrupt lines for each GPIO module.
201 * Each interrupt line is controlled by a set of registers.
203 static struct resource_spec ti_gpio_mem_spec[] = {
204 { SYS_RES_MEMORY, 0, RF_ACTIVE },
205 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
206 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
207 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
208 #if !defined(SOC_TI_AM335X)
209 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
210 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
214 static struct resource_spec ti_gpio_irq_spec[] = {
215 { SYS_RES_IRQ, 0, RF_ACTIVE },
216 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
217 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
218 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
219 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
220 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
221 #if defined(SOC_TI_AM335X)
222 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
223 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
229 * Macros for driver mutex locking
231 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
232 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
233 #define TI_GPIO_LOCK_INIT(_sc) \
234 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
236 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
237 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
238 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
241 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
242 * @sc: GPIO device context
243 * @bank: The bank to read from
244 * @off: The offset of a register from the GPIO register address range
248 * 32-bit value read from the register.
250 static inline uint32_t
251 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
253 return (bus_read_4(sc->sc_mem_res[bank], off));
257 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
258 * @sc: GPIO device context
259 * @bank: The bank to write to
260 * @off: The offset of a register from the GPIO register address range
261 * @val: The value to write into the register
267 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
270 bus_write_4(sc->sc_mem_res[bank], off, val);
274 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
277 /* We clear both set of registers. */
278 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
279 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
283 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
284 * @dev: gpio device handle
285 * @maxpin: pointer to a value that upon return will contain the maximum number
286 * of pins in the device.
290 * No locking required, returns static data.
293 * Returns 0 on success otherwise an error code
296 ti_gpio_pin_max(device_t dev, int *maxpin)
299 *maxpin = ti_max_gpio_banks() * PINS_PER_BANK - 1;
305 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
308 if (pin > sc->sc_maxpin ||
309 TI_GPIO_BANK(pin) >= ti_max_gpio_banks() ||
310 sc->sc_mem_res[TI_GPIO_BANK(pin)] == NULL) {
318 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
319 * @dev: gpio device handle
320 * @pin: the number of the pin
321 * @caps: pointer to a value that upon return will contain the capabilities
323 * Currently all pins have the same capability, notably:
327 * - GPIO_PIN_PULLDOWN
330 * No locking required, returns static data.
333 * Returns 0 on success otherwise an error code
336 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
338 struct ti_gpio_softc *sc;
340 sc = device_get_softc(dev);
341 if (ti_gpio_valid_pin(sc, pin) != 0)
344 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
351 * ti_gpio_pin_getflags - Gets the current flags of a given pin
352 * @dev: gpio device handle
353 * @pin: the number of the pin
354 * @flags: upon return will contain the current flags of the pin
356 * Reads the current flags of a given pin, here we actually read the H/W
357 * registers to determine the flags, rather than storing the value in the
361 * Internally locks the context
364 * Returns 0 on success otherwise an error code
367 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
369 struct ti_gpio_softc *sc;
371 sc = device_get_softc(dev);
372 if (ti_gpio_valid_pin(sc, pin) != 0)
375 /* Get the current pin state */
377 TI_GPIO_GET_FLAGS(dev, pin, flags);
384 * ti_gpio_pin_getname - Gets the name of a given pin
385 * @dev: gpio device handle
386 * @pin: the number of the pin
387 * @name: buffer to put the name in
389 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
393 * No locking required, returns static data.
396 * Returns 0 on success otherwise an error code
399 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
401 struct ti_gpio_softc *sc;
403 sc = device_get_softc(dev);
404 if (ti_gpio_valid_pin(sc, pin) != 0)
407 /* Set a very simple name */
408 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
409 name[GPIOMAXNAME - 1] = '\0';
415 * ti_gpio_pin_setflags - Sets the flags for a given pin
416 * @dev: gpio device handle
417 * @pin: the number of the pin
418 * @flags: the flags to set
420 * The flags of the pin correspond to things like input/output mode, pull-ups,
421 * pull-downs, etc. This driver doesn't support all flags, only the following:
425 * - GPIO_PIN_PULLDOWN
428 * Internally locks the context
431 * Returns 0 on success otherwise an error code
434 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
436 struct ti_gpio_softc *sc;
439 sc = device_get_softc(dev);
440 if (ti_gpio_valid_pin(sc, pin) != 0)
443 /* Set the GPIO mode and state */
445 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
450 /* If configuring as an output set the "output enable" bit */
451 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE);
452 if (flags & GPIO_PIN_INPUT)
453 oe |= TI_GPIO_MASK(pin);
455 oe &= ~TI_GPIO_MASK(pin);
456 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE, oe);
463 * ti_gpio_pin_set - Sets the current level on a GPIO pin
464 * @dev: gpio device handle
465 * @pin: the number of the pin
466 * @value: non-zero value will drive the pin high, otherwise the pin is
471 * Internally locks the context
474 * Returns 0 on success otherwise a error code
477 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
479 struct ti_gpio_softc *sc;
482 sc = device_get_softc(dev);
483 if (ti_gpio_valid_pin(sc, pin) != 0)
487 if (value == GPIO_PIN_LOW)
488 reg = TI_GPIO_CLEARDATAOUT;
490 reg = TI_GPIO_SETDATAOUT;
491 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin));
498 * ti_gpio_pin_get - Gets the current level on a GPIO pin
499 * @dev: gpio device handle
500 * @pin: the number of the pin
501 * @value: pointer to a value that upond return will contain the pin value
503 * The pin must be configured as an input pin beforehand, otherwise this
504 * function will fail.
507 * Internally locks the context
510 * Returns 0 on success otherwise a error code
513 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
515 struct ti_gpio_softc *sc;
516 uint32_t oe, reg, val;
518 sc = device_get_softc(dev);
519 if (ti_gpio_valid_pin(sc, pin) != 0)
523 * Return data from output latch when set as output and from the
524 * input register otherwise.
527 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE);
528 if (oe & TI_GPIO_MASK(pin))
529 reg = TI_GPIO_DATAIN;
531 reg = TI_GPIO_DATAOUT;
532 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), reg);
533 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
540 * ti_gpio_pin_toggle - Toggles a given GPIO pin
541 * @dev: gpio device handle
542 * @pin: the number of the pin
546 * Internally locks the context
549 * Returns 0 on success otherwise a error code
552 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
554 struct ti_gpio_softc *sc;
557 sc = device_get_softc(dev);
558 if (ti_gpio_valid_pin(sc, pin) != 0)
563 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_DATAOUT);
564 if (val & TI_GPIO_MASK(pin))
565 reg = TI_GPIO_CLEARDATAOUT;
567 reg = TI_GPIO_SETDATAOUT;
568 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin));
575 * ti_gpio_intr - ISR for all GPIO modules
576 * @arg: the soft context pointer
581 * Internally locks the context
585 ti_gpio_intr(void *arg)
587 struct ti_gpio_softc *sc = arg;
590 /* TODO: something useful */
595 ti_gpio_attach_intr(device_t dev)
598 struct ti_gpio_softc *sc;
600 sc = device_get_softc(dev);
601 for (i = 0; i < ti_max_gpio_intrs(); i++) {
602 if (sc->sc_irq_res[i] == NULL)
606 * Register our interrupt handler for each of the IRQ resources.
608 if (bus_setup_intr(dev, sc->sc_irq_res[i],
609 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
610 &sc->sc_irq_hdl[i]) != 0) {
612 "WARNING: unable to register interrupt handler\n");
621 ti_gpio_detach_intr(device_t dev)
624 struct ti_gpio_softc *sc;
626 /* Teardown our interrupt handlers. */
627 sc = device_get_softc(dev);
628 for (i = 0; i < ti_max_gpio_intrs(); i++) {
629 if (sc->sc_irq_res[i] == NULL)
632 if (sc->sc_irq_hdl[i]) {
633 bus_teardown_intr(dev, sc->sc_irq_res[i],
642 ti_gpio_bank_init(device_t dev, int bank)
645 struct ti_gpio_softc *sc;
646 uint32_t flags, reg_oe, rev;
648 sc = device_get_softc(dev);
650 /* Enable the interface and functional clocks for the module. */
651 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank);
654 * Read the revision number of the module. TI don't publish the
655 * actual revision numbers, so instead the values have been
656 * determined by experimentation.
658 rev = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
660 /* Check the revision. */
661 if (rev != ti_gpio_rev()) {
662 device_printf(dev, "Warning: could not determine the revision "
663 "of GPIO module %d (revision:0x%08x)\n", bank, rev);
667 /* Disable interrupts for all pins. */
668 ti_gpio_intr_clr(sc, bank, 0xffffffff);
670 /* Init OE register based on pads configuration. */
672 for (pin = 0; pin < PINS_PER_BANK; pin++) {
673 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags);
674 if (flags & GPIO_PIN_OUTPUT)
675 reg_oe &= ~(1UL << pin);
677 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
683 * ti_gpio_attach - attach function for the driver
684 * @dev: gpio device handle
686 * Allocates and sets up the driver context for all GPIO banks. This function
687 * expects the memory ranges and IRQs to already be allocated to the driver.
696 ti_gpio_attach(device_t dev)
698 struct ti_gpio_softc *sc;
702 sc = device_get_softc(dev);
704 TI_GPIO_LOCK_INIT(sc);
705 ti_gpio_pin_max(dev, &sc->sc_maxpin);
707 /* There are up to 6 different GPIO register sets located in different
708 * memory areas on the chip. The memory range should have been set for
709 * the driver when it was added as a child.
711 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
712 device_printf(dev, "Error: could not allocate mem resources\n");
716 /* Request the IRQ resources */
717 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
718 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
719 device_printf(dev, "Error: could not allocate irq resources\n");
723 /* Setup the IRQ resources */
724 if (ti_gpio_attach_intr(dev) != 0) {
725 ti_gpio_detach_intr(dev);
726 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
727 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
731 /* We need to go through each block and ensure the clocks are running and
732 * the module is enabled. It might be better to do this only when the
733 * pins are configured which would result in less power used if the GPIO
734 * pins weren't used ...
736 for (i = 0; i < ti_max_gpio_banks(); i++) {
737 if (sc->sc_mem_res[i] != NULL) {
738 /* Initialize the GPIO module. */
739 err = ti_gpio_bank_init(dev, i);
741 ti_gpio_detach_intr(dev);
742 bus_release_resources(dev, ti_gpio_irq_spec,
744 bus_release_resources(dev, ti_gpio_mem_spec,
751 /* Finish of the probe call */
752 device_add_child(dev, "gpioc", -1);
753 device_add_child(dev, "gpiobus", -1);
755 return (bus_generic_attach(dev));
759 * ti_gpio_detach - detach function for the driver
760 * @dev: scm device handle
762 * Allocates and sets up the driver context, this simply entails creating a
763 * bus mappings for the SCM register set.
772 ti_gpio_detach(device_t dev)
774 struct ti_gpio_softc *sc = device_get_softc(dev);
777 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
779 /* Disable all interrupts */
780 for (i = 0; i < ti_max_gpio_banks(); i++) {
781 if (sc->sc_mem_res[i] != NULL)
782 ti_gpio_intr_clr(sc, i, 0xffffffff);
785 bus_generic_detach(dev);
787 /* Release the memory and IRQ resources. */
788 ti_gpio_detach_intr(dev);
789 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
790 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
792 TI_GPIO_LOCK_DESTROY(sc);
798 ti_gpio_get_node(device_t bus, device_t dev)
801 /* We only have one child, the GPIO bus, which needs our own node. */
802 return (ofw_bus_get_node(bus));
805 static device_method_t ti_gpio_methods[] = {
806 DEVMETHOD(device_attach, ti_gpio_attach),
807 DEVMETHOD(device_detach, ti_gpio_detach),
810 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
811 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
812 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
813 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
814 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
815 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
816 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
817 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
819 /* ofw_bus interface */
820 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
825 driver_t ti_gpio_driver = {
828 sizeof(struct ti_gpio_softc),