2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/interrupt.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
51 #include <arm/ti/ti_cpuid.h>
52 #include <arm/ti/ti_gpio.h>
53 #include <arm/ti/ti_scm.h>
54 #include <arm/ti/ti_prcm.h>
55 #include <arm/ti/ti_hwmods.h>
57 #include <dev/fdt/fdt_common.h>
58 #include <dev/gpio/gpiobusvar.h>
59 #include <dev/ofw/openfirm.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
64 #include "ti_gpio_if.h"
66 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
70 /* Register definitions */
71 #define TI_GPIO_REVISION 0x0000
72 #define TI_GPIO_SYSCONFIG 0x0010
73 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
74 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
75 #define TI_GPIO_IRQSTATUS_0 0x002C
76 #define TI_GPIO_IRQSTATUS_1 0x0030
77 #define TI_GPIO_IRQSTATUS_SET_0 0x0034
78 #define TI_GPIO_IRQSTATUS_SET_1 0x0038
79 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C
80 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040
81 #define TI_GPIO_IRQWAKEN_0 0x0044
82 #define TI_GPIO_IRQWAKEN_1 0x0048
83 #define TI_GPIO_SYSSTATUS 0x0114
84 #define TI_GPIO_IRQSTATUS1 0x0118
85 #define TI_GPIO_IRQENABLE1 0x011C
86 #define TI_GPIO_WAKEUPENABLE 0x0120
87 #define TI_GPIO_IRQSTATUS2 0x0128
88 #define TI_GPIO_IRQENABLE2 0x012C
89 #define TI_GPIO_CTRL 0x0130
90 #define TI_GPIO_OE 0x0134
91 #define TI_GPIO_DATAIN 0x0138
92 #define TI_GPIO_DATAOUT 0x013C
93 #define TI_GPIO_LEVELDETECT0 0x0140
94 #define TI_GPIO_LEVELDETECT1 0x0144
95 #define TI_GPIO_RISINGDETECT 0x0148
96 #define TI_GPIO_FALLINGDETECT 0x014C
97 #define TI_GPIO_DEBOUNCENABLE 0x0150
98 #define TI_GPIO_DEBOUNCINGTIME 0x0154
99 #define TI_GPIO_CLEARWKUPENA 0x0180
100 #define TI_GPIO_SETWKUENA 0x0184
101 #define TI_GPIO_CLEARDATAOUT 0x0190
102 #define TI_GPIO_SETDATAOUT 0x0194
104 /* Other SoC Specific definitions */
105 #define OMAP4_FIRST_GPIO_BANK 1
106 #define OMAP4_INTR_PER_BANK 1
107 #define OMAP4_GPIO_REV 0x50600801
108 #define AM335X_FIRST_GPIO_BANK 0
109 #define AM335X_INTR_PER_BANK 2
110 #define AM335X_GPIO_REV 0x50600801
111 #define PINS_PER_BANK 32
112 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
114 static int ti_gpio_detach(device_t);
117 ti_first_gpio_bank(void)
122 return (OMAP4_FIRST_GPIO_BANK);
126 return (AM335X_FIRST_GPIO_BANK);
138 return (OMAP4_GPIO_REV);
142 return (AM335X_GPIO_REV);
149 * Macros for driver mutex locking
151 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
152 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
153 #define TI_GPIO_LOCK_INIT(_sc) \
154 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
156 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
157 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
158 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
161 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
162 * @sc: GPIO device context
163 * @bank: The bank to read from
164 * @off: The offset of a register from the GPIO register address range
168 * 32-bit value read from the register.
170 static inline uint32_t
171 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
173 return (bus_read_4(sc->sc_mem_res, off));
177 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
178 * @sc: GPIO device context
179 * @bank: The bank to write to
180 * @off: The offset of a register from the GPIO register address range
181 * @val: The value to write into the register
187 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
190 bus_write_4(sc->sc_mem_res, off, val);
194 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
197 /* We clear both set of registers. */
198 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
199 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
203 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
207 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
208 * also activate only the first interrupt.
210 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
214 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
218 * Acknowledge the interrupt on both registers even if we use only
221 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
222 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
225 static inline uint32_t
226 ti_gpio_intr_status(struct ti_gpio_softc *sc)
230 /* Get the status from both registers. */
231 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
232 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
238 ti_gpio_get_bus(device_t dev)
240 struct ti_gpio_softc *sc;
242 sc = device_get_softc(dev);
244 return (sc->sc_busdev);
248 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
249 * @dev: gpio device handle
250 * @maxpin: pointer to a value that upon return will contain the maximum number
251 * of pins in the device.
255 * No locking required, returns static data.
258 * Returns 0 on success otherwise an error code
261 ti_gpio_pin_max(device_t dev, int *maxpin)
264 *maxpin = PINS_PER_BANK - 1;
270 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
273 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
280 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
281 * @dev: gpio device handle
282 * @pin: the number of the pin
283 * @caps: pointer to a value that upon return will contain the capabilities
285 * Currently all pins have the same capability, notably:
289 * - GPIO_PIN_PULLDOWN
292 * No locking required, returns static data.
295 * Returns 0 on success otherwise an error code
298 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
300 struct ti_gpio_softc *sc;
302 sc = device_get_softc(dev);
303 if (ti_gpio_valid_pin(sc, pin) != 0)
306 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
313 * ti_gpio_pin_getflags - Gets the current flags of a given pin
314 * @dev: gpio device handle
315 * @pin: the number of the pin
316 * @flags: upon return will contain the current flags of the pin
318 * Reads the current flags of a given pin, here we actually read the H/W
319 * registers to determine the flags, rather than storing the value in the
323 * Internally locks the context
326 * Returns 0 on success otherwise an error code
329 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
331 struct ti_gpio_softc *sc;
333 sc = device_get_softc(dev);
334 if (ti_gpio_valid_pin(sc, pin) != 0)
337 /* Get the current pin state */
339 TI_GPIO_GET_FLAGS(dev, pin, flags);
346 * ti_gpio_pin_getname - Gets the name of a given pin
347 * @dev: gpio device handle
348 * @pin: the number of the pin
349 * @name: buffer to put the name in
351 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
355 * No locking required, returns static data.
358 * Returns 0 on success otherwise an error code
361 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
363 struct ti_gpio_softc *sc;
365 sc = device_get_softc(dev);
366 if (ti_gpio_valid_pin(sc, pin) != 0)
369 /* Set a very simple name */
370 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
371 name[GPIOMAXNAME - 1] = '\0';
377 * ti_gpio_pin_setflags - Sets the flags for a given pin
378 * @dev: gpio device handle
379 * @pin: the number of the pin
380 * @flags: the flags to set
382 * The flags of the pin correspond to things like input/output mode, pull-ups,
383 * pull-downs, etc. This driver doesn't support all flags, only the following:
387 * - GPIO_PIN_PULLDOWN
390 * Internally locks the context
393 * Returns 0 on success otherwise an error code
396 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
398 struct ti_gpio_softc *sc;
401 sc = device_get_softc(dev);
402 if (ti_gpio_valid_pin(sc, pin) != 0)
405 /* Set the GPIO mode and state */
407 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
412 /* If configuring as an output set the "output enable" bit */
413 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
414 if (flags & GPIO_PIN_INPUT)
415 oe |= TI_GPIO_MASK(pin);
417 oe &= ~TI_GPIO_MASK(pin);
418 ti_gpio_write_4(sc, TI_GPIO_OE, oe);
425 * ti_gpio_pin_set - Sets the current level on a GPIO pin
426 * @dev: gpio device handle
427 * @pin: the number of the pin
428 * @value: non-zero value will drive the pin high, otherwise the pin is
433 * Internally locks the context
436 * Returns 0 on success otherwise a error code
439 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
441 struct ti_gpio_softc *sc;
444 sc = device_get_softc(dev);
445 if (ti_gpio_valid_pin(sc, pin) != 0)
449 if (value == GPIO_PIN_LOW)
450 reg = TI_GPIO_CLEARDATAOUT;
452 reg = TI_GPIO_SETDATAOUT;
453 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
460 * ti_gpio_pin_get - Gets the current level on a GPIO pin
461 * @dev: gpio device handle
462 * @pin: the number of the pin
463 * @value: pointer to a value that upond return will contain the pin value
465 * The pin must be configured as an input pin beforehand, otherwise this
466 * function will fail.
469 * Internally locks the context
472 * Returns 0 on success otherwise a error code
475 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
477 struct ti_gpio_softc *sc;
478 uint32_t oe, reg, val;
480 sc = device_get_softc(dev);
481 if (ti_gpio_valid_pin(sc, pin) != 0)
485 * Return data from output latch when set as output and from the
486 * input register otherwise.
489 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
490 if (oe & TI_GPIO_MASK(pin))
491 reg = TI_GPIO_DATAIN;
493 reg = TI_GPIO_DATAOUT;
494 val = ti_gpio_read_4(sc, reg);
495 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
502 * ti_gpio_pin_toggle - Toggles a given GPIO pin
503 * @dev: gpio device handle
504 * @pin: the number of the pin
508 * Internally locks the context
511 * Returns 0 on success otherwise a error code
514 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
516 struct ti_gpio_softc *sc;
519 sc = device_get_softc(dev);
520 if (ti_gpio_valid_pin(sc, pin) != 0)
525 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
526 if (val & TI_GPIO_MASK(pin))
527 reg = TI_GPIO_CLEARDATAOUT;
529 reg = TI_GPIO_SETDATAOUT;
530 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
537 * ti_gpio_intr - ISR for all GPIO modules
538 * @arg: the soft context pointer
541 * Internally locks the context
545 ti_gpio_intr(void *arg)
548 struct intr_event *event;
549 struct ti_gpio_softc *sc;
552 sc = (struct ti_gpio_softc *)arg;
554 reg = 0; /* squelch bogus gcc warning */
555 reg = ti_gpio_intr_status(sc);
556 for (irq = 0; irq < sc->sc_maxpin; irq++) {
557 if ((reg & TI_GPIO_MASK(irq)) == 0)
559 event = sc->sc_events[irq];
560 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
561 intr_event_handle(event, NULL);
563 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq);
564 /* Ack the IRQ Status bit. */
565 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq));
568 return (FILTER_HANDLED);
572 ti_gpio_bank_init(device_t dev)
575 struct ti_gpio_softc *sc;
576 uint32_t flags, reg_oe, rev;
579 sc = device_get_softc(dev);
581 /* Enable the interface and functional clocks for the module. */
582 clk = ti_hwmods_get_clock(dev);
583 if (clk == INVALID_CLK_IDENT) {
584 device_printf(dev, "failed to get device id based on ti,hwmods\n");
588 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank();
589 ti_prcm_clk_enable(clk);
592 * Read the revision number of the module. TI don't publish the
593 * actual revision numbers, so instead the values have been
594 * determined by experimentation.
596 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION);
598 /* Check the revision. */
599 if (rev != ti_gpio_rev()) {
600 device_printf(dev, "Warning: could not determine the revision "
601 "of GPIO module (revision:0x%08x)\n", rev);
605 /* Disable interrupts for all pins. */
606 ti_gpio_intr_clr(sc, 0xffffffff);
608 /* Init OE register based on pads configuration. */
610 for (pin = 0; pin < PINS_PER_BANK; pin++) {
611 TI_GPIO_GET_FLAGS(dev, pin, &flags);
612 if (flags & GPIO_PIN_OUTPUT)
613 reg_oe &= ~(1UL << pin);
615 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
621 * ti_gpio_attach - attach function for the driver
622 * @dev: gpio device handle
624 * Allocates and sets up the driver context for all GPIO banks. This function
625 * expects the memory ranges and IRQs to already be allocated to the driver.
634 ti_gpio_attach(device_t dev)
636 struct ti_gpio_softc *sc;
640 sc = device_get_softc(dev);
642 TI_GPIO_LOCK_INIT(sc);
643 ti_gpio_pin_max(dev, &sc->sc_maxpin);
647 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
648 &sc->sc_mem_rid, RF_ACTIVE);
649 if (!sc->sc_mem_res) {
650 device_printf(dev, "Error: could not allocate mem resources\n");
656 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
657 &sc->sc_irq_rid, RF_ACTIVE);
658 if (!sc->sc_irq_res) {
659 device_printf(dev, "Error: could not allocate irq resources\n");
665 * Register our interrupt filter for each of the IRQ resources.
667 if (bus_setup_intr(dev, sc->sc_irq_res,
668 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
669 &sc->sc_irq_hdl) != 0) {
671 "WARNING: unable to register interrupt filter\n");
677 * Initialize the interrupt settings. The default is active-low
680 sc->sc_irq_trigger = malloc(
681 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin,
682 M_DEVBUF, M_WAITOK | M_ZERO);
683 sc->sc_irq_polarity = malloc(
684 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin,
685 M_DEVBUF, M_WAITOK | M_ZERO);
686 for (i = 0; i < sc->sc_maxpin; i++) {
687 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
688 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
691 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin,
692 M_DEVBUF, M_WAITOK | M_ZERO);
694 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin,
695 M_DEVBUF, M_WAITOK | M_ZERO);
697 /* We need to go through each block and ensure the clocks are running and
698 * the module is enabled. It might be better to do this only when the
699 * pins are configured which would result in less power used if the GPIO
700 * pins weren't used ...
702 if (sc->sc_mem_res != NULL) {
703 /* Initialize the GPIO module. */
704 err = ti_gpio_bank_init(dev);
711 sc->sc_busdev = gpiobus_attach_bus(dev);
712 if (sc->sc_busdev == NULL) {
721 * ti_gpio_detach - detach function for the driver
722 * @dev: scm device handle
724 * Allocates and sets up the driver context, this simply entails creating a
725 * bus mappings for the SCM register set.
734 ti_gpio_detach(device_t dev)
736 struct ti_gpio_softc *sc = device_get_softc(dev);
738 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
740 /* Disable all interrupts */
741 if (sc->sc_mem_res != NULL)
742 ti_gpio_intr_clr(sc, 0xffffffff);
743 gpiobus_detach_bus(dev);
745 free(sc->sc_events, M_DEVBUF);
746 if (sc->sc_mask_args)
747 free(sc->sc_mask_args, M_DEVBUF);
748 if (sc->sc_irq_polarity)
749 free(sc->sc_irq_polarity, M_DEVBUF);
750 if (sc->sc_irq_trigger)
751 free(sc->sc_irq_trigger, M_DEVBUF);
752 /* Release the memory and IRQ resources. */
753 if (sc->sc_irq_hdl) {
754 bus_teardown_intr(dev, sc->sc_irq_res,
757 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
759 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
761 TI_GPIO_LOCK_DESTROY(sc);
767 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
770 if (ti_gpio_valid_pin(sc, irq) != 0)
773 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) {
774 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
775 return (TI_GPIO_LEVELDETECT0);
776 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
777 return (TI_GPIO_LEVELDETECT1);
778 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) {
779 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
780 return (TI_GPIO_FALLINGDETECT);
781 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
782 return (TI_GPIO_RISINGDETECT);
789 ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq)
793 if (ti_gpio_valid_pin(sc, irq) != 0)
797 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq));
798 reg = ti_gpio_intr_reg(sc, irq);
800 val = ti_gpio_read_4(sc, reg);
801 val &= ~TI_GPIO_MASK(irq);
802 ti_gpio_write_4(sc, reg, val);
808 ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq)
812 if (ti_gpio_valid_pin(sc, irq) != 0)
816 reg = ti_gpio_intr_reg(sc, irq);
818 val = ti_gpio_read_4(sc, reg);
819 val |= TI_GPIO_MASK(irq);
820 ti_gpio_write_4(sc, reg, val);
821 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq));
827 ti_gpio_mask_irq(void *source)
829 struct ti_gpio_mask_arg *arg = source;
831 ti_gpio_mask_irq_internal(arg->softc, arg->pin);
835 ti_gpio_unmask_irq(void *source)
837 struct ti_gpio_mask_arg *arg = source;
839 ti_gpio_unmask_irq_internal(arg->softc, arg->pin);
843 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid,
844 struct resource *res)
848 if (type != SYS_RES_IRQ)
851 /* Unmask the interrupt. */
852 pin = rman_get_start(res);
853 ti_gpio_unmask_irq((void *)(uintptr_t)pin);
859 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid,
860 struct resource *res)
864 if (type != SYS_RES_IRQ)
867 /* Mask the interrupt. */
868 pin = rman_get_start(res);
869 ti_gpio_mask_irq((void *)(uintptr_t)pin);
875 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig,
876 enum intr_polarity pol)
878 struct ti_gpio_softc *sc;
879 uint32_t oldreg, reg, val;
881 sc = device_get_softc(dev);
882 if (ti_gpio_valid_pin(sc, irq) != 0)
885 /* There is no standard trigger or polarity. */
886 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
891 * TRM recommends add the new event before remove the old one to
892 * avoid losing interrupts.
894 oldreg = ti_gpio_intr_reg(sc, irq);
895 sc->sc_irq_trigger[irq] = trig;
896 sc->sc_irq_polarity[irq] = pol;
897 reg = ti_gpio_intr_reg(sc, irq);
899 /* Apply the new settings. */
900 val = ti_gpio_read_4(sc, reg);
901 val |= TI_GPIO_MASK(irq);
902 ti_gpio_write_4(sc, reg, val);
904 if (reg != oldreg && oldreg != 0) {
905 /* Remove the old settings. */
906 val = ti_gpio_read_4(sc, oldreg);
907 val &= ~TI_GPIO_MASK(irq);
908 ti_gpio_write_4(sc, oldreg, val);
916 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires,
917 int flags, driver_filter_t *filt, driver_intr_t *handler,
918 void *arg, void **cookiep)
920 struct ti_gpio_softc *sc;
921 struct intr_event *event;
924 sc = device_get_softc(dev);
925 pin = rman_get_start(ires);
926 if (ti_gpio_valid_pin(sc, pin) != 0)
927 panic("%s: bad pin %d", __func__, pin);
929 event = sc->sc_events[pin];
931 sc->sc_mask_args[pin].softc = sc;
932 sc->sc_mask_args[pin].pin = pin;
933 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0,
934 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL,
935 "gpio%d pin%d:", device_get_unit(dev), pin);
938 sc->sc_events[pin] = event;
940 intr_event_add_handler(event, device_get_nameunit(child), filt,
941 handler, arg, intr_priority(flags), flags, cookiep);
947 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires,
950 struct ti_gpio_softc *sc;
953 sc = device_get_softc(dev);
954 pin = rman_get_start(ires);
955 if (ti_gpio_valid_pin(sc, pin) != 0)
956 panic("%s: bad pin %d", __func__, pin);
957 if (sc->sc_events[pin] == NULL)
958 panic("Trying to teardown unoccupied IRQ");
959 err = intr_event_remove_handler(cookie);
961 sc->sc_events[pin] = NULL;
967 ti_gpio_get_node(device_t bus, device_t dev)
970 /* We only have one child, the GPIO bus, which needs our own node. */
971 return (ofw_bus_get_node(bus));
974 static device_method_t ti_gpio_methods[] = {
975 DEVMETHOD(device_attach, ti_gpio_attach),
976 DEVMETHOD(device_detach, ti_gpio_detach),
979 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
980 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
981 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
982 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
983 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
984 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
985 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
986 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
987 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
990 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource),
991 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource),
992 DEVMETHOD(bus_config_intr, ti_gpio_config_intr),
993 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr),
994 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr),
996 /* ofw_bus interface */
997 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
1002 driver_t ti_gpio_driver = {
1005 sizeof(struct ti_gpio_softc),