3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's.
31 * Currently this driver only does the basics, get a value on a pin & set a
32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic
33 * and support interrupts and other various bits on the SoC can do ... in the
34 * meantime this is all you get.
36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
53 #include <sys/mutex.h>
56 #include <machine/bus.h>
57 #include <machine/resource.h>
59 #include <arm/ti/ti_cpuid.h>
60 #include <arm/ti/ti_gpio.h>
61 #include <arm/ti/ti_scm.h>
62 #include <arm/ti/ti_prcm.h>
64 #include <dev/fdt/fdt_common.h>
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
70 #include "ti_gpio_if.h"
72 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
76 /* Register definitions */
77 #define TI_GPIO_REVISION 0x0000
78 #define TI_GPIO_SYSCONFIG 0x0010
79 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
80 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
81 #define TI_GPIO_IRQSTATUS_0 0x002C
82 #define TI_GPIO_IRQSTATUS_1 0x0030
83 #define TI_GPIO_IRQSTATUS_SET_0 0x0034
84 #define TI_GPIO_IRQSTATUS_SET_1 0x0038
85 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C
86 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040
87 #define TI_GPIO_IRQWAKEN_0 0x0044
88 #define TI_GPIO_IRQWAKEN_1 0x0048
89 #define TI_GPIO_SYSSTATUS 0x0114
90 #define TI_GPIO_IRQSTATUS1 0x0118
91 #define TI_GPIO_IRQENABLE1 0x011C
92 #define TI_GPIO_WAKEUPENABLE 0x0120
93 #define TI_GPIO_IRQSTATUS2 0x0128
94 #define TI_GPIO_IRQENABLE2 0x012C
95 #define TI_GPIO_CTRL 0x0130
96 #define TI_GPIO_OE 0x0134
97 #define TI_GPIO_DATAIN 0x0138
98 #define TI_GPIO_DATAOUT 0x013C
99 #define TI_GPIO_LEVELDETECT0 0x0140
100 #define TI_GPIO_LEVELDETECT1 0x0144
101 #define TI_GPIO_RISINGDETECT 0x0148
102 #define TI_GPIO_FALLINGDETECT 0x014C
103 #define TI_GPIO_DEBOUNCENABLE 0x0150
104 #define TI_GPIO_DEBOUNCINGTIME 0x0154
105 #define TI_GPIO_CLEARWKUPENA 0x0180
106 #define TI_GPIO_SETWKUENA 0x0184
107 #define TI_GPIO_CLEARDATAOUT 0x0190
108 #define TI_GPIO_SETDATAOUT 0x0194
110 /* Other SoC Specific definitions */
111 #define OMAP4_MAX_GPIO_BANKS 6
112 #define OMAP4_FIRST_GPIO_BANK 1
113 #define OMAP4_INTR_PER_BANK 1
114 #define OMAP4_GPIO_REV 0x50600801
115 #define AM335X_MAX_GPIO_BANKS 4
116 #define AM335X_FIRST_GPIO_BANK 0
117 #define AM335X_INTR_PER_BANK 2
118 #define AM335X_GPIO_REV 0x50600801
119 #define PINS_PER_BANK 32
122 ti_max_gpio_banks(void)
127 return (OMAP4_MAX_GPIO_BANKS);
131 return (AM335X_MAX_GPIO_BANKS);
138 ti_max_gpio_intrs(void)
143 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK);
147 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK);
154 ti_first_gpio_bank(void)
159 return (OMAP4_FIRST_GPIO_BANK);
163 return (AM335X_FIRST_GPIO_BANK);
175 return (OMAP4_GPIO_REV);
179 return (AM335X_GPIO_REV);
186 * ti_gpio_mem_spec - Resource specification used when allocating resources
187 * ti_gpio_irq_spec - Resource specification used when allocating resources
189 * This driver module can have up to six independent memory regions, each
190 * region typically controls 32 GPIO pins.
192 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
193 * but there are two set of registers which control the interrupt delivery
194 * to internal subsystems. The first set of registers control the
195 * interrupts delivery to the MPU and the second set control the
196 * interrupts delivery to the DSP.
198 * On AM335x there are two physical interrupt lines for each GPIO module.
199 * Each interrupt line is controlled by a set of registers.
201 static struct resource_spec ti_gpio_mem_spec[] = {
202 { SYS_RES_MEMORY, 0, RF_ACTIVE },
203 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
204 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
205 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
206 #if !defined(SOC_TI_AM335X)
207 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
208 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
212 static struct resource_spec ti_gpio_irq_spec[] = {
213 { SYS_RES_IRQ, 0, RF_ACTIVE },
214 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
215 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
216 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
217 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
218 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
219 #if defined(SOC_TI_AM335X)
220 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
221 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
227 * Macros for driver mutex locking
229 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
230 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
231 #define TI_GPIO_LOCK_INIT(_sc) \
232 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
234 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
235 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
236 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
239 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers
240 * @sc: GPIO device context
241 * @bank: The bank to read from
242 * @off: The offset of a register from the GPIO register address range
246 * 32-bit value read from the register.
248 static inline uint32_t
249 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
251 return (bus_read_4(sc->sc_mem_res[bank], off));
255 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers
256 * @sc: GPIO device context
257 * @bank: The bank to write to
258 * @off: The offset of a register from the GPIO register address range
259 * @val: The value to write into the register
265 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
268 bus_write_4(sc->sc_mem_res[bank], off, val);
272 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
275 /* We clear both set of registers. */
276 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
277 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
281 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
282 * @dev: gpio device handle
283 * @maxpin: pointer to a value that upon return will contain the maximum number
284 * of pins in the device.
288 * No locking required, returns static data.
291 * Returns 0 on success otherwise an error code
294 ti_gpio_pin_max(device_t dev, int *maxpin)
297 *maxpin = ti_max_gpio_banks() * PINS_PER_BANK - 1;
303 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
304 * @dev: gpio device handle
305 * @pin: the number of the pin
306 * @caps: pointer to a value that upon return will contain the capabilities
308 * Currently all pins have the same capability, notably:
312 * - GPIO_PIN_PULLDOWN
315 * No locking required, returns static data.
318 * Returns 0 on success otherwise an error code
321 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
323 struct ti_gpio_softc *sc = device_get_softc(dev);
324 uint32_t bank = (pin / PINS_PER_BANK);
326 /* Sanity check the pin number is valid */
327 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
330 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
337 * ti_gpio_pin_getflags - Gets the current flags of a given pin
338 * @dev: gpio device handle
339 * @pin: the number of the pin
340 * @flags: upon return will contain the current flags of the pin
342 * Reads the current flags of a given pin, here we actually read the H/W
343 * registers to determine the flags, rather than storing the value in the
347 * Internally locks the context
350 * Returns 0 on success otherwise an error code
353 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
355 struct ti_gpio_softc *sc = device_get_softc(dev);
356 uint32_t bank = (pin / PINS_PER_BANK);
358 /* Sanity check the pin number is valid */
359 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
362 /* Get the current pin state */
364 TI_GPIO_GET_FLAGS(dev, pin, flags);
371 * ti_gpio_pin_getname - Gets the name of a given pin
372 * @dev: gpio device handle
373 * @pin: the number of the pin
374 * @name: buffer to put the name in
376 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
380 * No locking required, returns static data.
383 * Returns 0 on success otherwise an error code
386 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
388 struct ti_gpio_softc *sc = device_get_softc(dev);
389 uint32_t bank = (pin / PINS_PER_BANK);
391 /* Sanity check the pin number is valid */
392 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
395 /* Set a very simple name */
396 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
397 name[GPIOMAXNAME - 1] = '\0';
403 * ti_gpio_pin_setflags - Sets the flags for a given pin
404 * @dev: gpio device handle
405 * @pin: the number of the pin
406 * @flags: the flags to set
408 * The flags of the pin correspond to things like input/output mode, pull-ups,
409 * pull-downs, etc. This driver doesn't support all flags, only the following:
413 * - GPIO_PIN_PULLDOWN
416 * Internally locks the context
419 * Returns 0 on success otherwise an error code
422 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
424 struct ti_gpio_softc *sc = device_get_softc(dev);
425 uint32_t bank = (pin / PINS_PER_BANK);
426 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
429 /* Sanity check the pin number is valid */
430 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
433 /* Set the GPIO mode and state */
435 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
440 /* If configuring as an output set the "output enable" bit */
441 oe = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
442 if (flags & GPIO_PIN_INPUT)
446 ti_gpio_write_4(sc, bank, TI_GPIO_OE, oe);
453 * ti_gpio_pin_set - Sets the current level on a GPIO pin
454 * @dev: gpio device handle
455 * @pin: the number of the pin
456 * @value: non-zero value will drive the pin high, otherwise the pin is
461 * Internally locks the context
464 * Returns 0 on success otherwise a error code
467 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
469 struct ti_gpio_softc *sc = device_get_softc(dev);
470 uint32_t bank = (pin / PINS_PER_BANK);
471 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
474 /* Sanity check the pin number is valid */
475 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
479 if (value == GPIO_PIN_LOW)
480 reg = TI_GPIO_CLEARDATAOUT;
482 reg = TI_GPIO_SETDATAOUT;
483 ti_gpio_write_4(sc, bank, reg, mask);
490 * ti_gpio_pin_get - Gets the current level on a GPIO pin
491 * @dev: gpio device handle
492 * @pin: the number of the pin
493 * @value: pointer to a value that upond return will contain the pin value
495 * The pin must be configured as an input pin beforehand, otherwise this
496 * function will fail.
499 * Internally locks the context
502 * Returns 0 on success otherwise a error code
505 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
507 struct ti_gpio_softc *sc = device_get_softc(dev);
508 uint32_t bank = (pin / PINS_PER_BANK);
509 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
512 /* Sanity check the pin number is valid */
513 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
517 * Return data from output latch when set as output and from the
518 * input register otherwise.
521 oe = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
523 reg = TI_GPIO_DATAIN;
525 reg = TI_GPIO_DATAOUT;
526 *value = (ti_gpio_read_4(sc, bank, reg) & mask) ? 1 : 0;
533 * ti_gpio_pin_toggle - Toggles a given GPIO pin
534 * @dev: gpio device handle
535 * @pin: the number of the pin
539 * Internally locks the context
542 * Returns 0 on success otherwise a error code
545 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
547 struct ti_gpio_softc *sc = device_get_softc(dev);
548 uint32_t bank = (pin / PINS_PER_BANK);
549 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
552 /* Sanity check the pin number is valid */
553 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL))
558 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
560 reg = TI_GPIO_CLEARDATAOUT;
562 reg = TI_GPIO_SETDATAOUT;
563 ti_gpio_write_4(sc, bank, reg, mask);
570 * ti_gpio_intr - ISR for all GPIO modules
571 * @arg: the soft context pointer
576 * Internally locks the context
580 ti_gpio_intr(void *arg)
582 struct ti_gpio_softc *sc = arg;
585 /* TODO: something useful */
590 ti_gpio_attach_intr(device_t dev)
593 struct ti_gpio_softc *sc;
595 sc = device_get_softc(dev);
596 for (i = 0; i < ti_max_gpio_intrs(); i++) {
597 if (sc->sc_irq_res[i] == NULL)
601 * Register our interrupt handler for each of the IRQ resources.
603 if (bus_setup_intr(dev, sc->sc_irq_res[i],
604 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
605 &sc->sc_irq_hdl[i]) != 0) {
607 "WARNING: unable to register interrupt handler\n");
616 ti_gpio_detach_intr(device_t dev)
619 struct ti_gpio_softc *sc;
621 /* Teardown our interrupt handlers. */
622 sc = device_get_softc(dev);
623 for (i = 0; i < ti_max_gpio_intrs(); i++) {
624 if (sc->sc_irq_res[i] == NULL)
627 if (sc->sc_irq_hdl[i]) {
628 bus_teardown_intr(dev, sc->sc_irq_res[i],
637 ti_gpio_bank_init(device_t dev, int bank)
640 struct ti_gpio_softc *sc;
641 uint32_t flags, reg_oe;
643 sc = device_get_softc(dev);
645 /* Enable the interface and functional clocks for the module. */
646 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank);
649 * Read the revision number of the module. TI don't publish the
650 * actual revision numbers, so instead the values have been
651 * determined by experimentation.
653 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
655 /* Check the revision. */
656 if (sc->sc_revision[bank] != ti_gpio_rev()) {
657 device_printf(dev, "Warning: could not determine the revision "
658 "of %u GPIO module (revision:0x%08x)\n",
659 bank, sc->sc_revision[bank]);
663 /* Disable interrupts for all pins. */
664 ti_gpio_intr_clr(sc, bank, 0xffffffff);
666 /* Init OE register based on pads configuration. */
668 for (pin = 0; pin < PINS_PER_BANK; pin++) {
669 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags);
670 if (flags & GPIO_PIN_OUTPUT)
671 reg_oe &= ~(1UL << pin);
673 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
679 * ti_gpio_attach - attach function for the driver
680 * @dev: gpio device handle
682 * Allocates and sets up the driver context for all GPIO banks. This function
683 * expects the memory ranges and IRQs to already be allocated to the driver.
692 ti_gpio_attach(device_t dev)
694 struct ti_gpio_softc *sc;
698 sc = device_get_softc(dev);
701 TI_GPIO_LOCK_INIT(sc);
703 /* There are up to 6 different GPIO register sets located in different
704 * memory areas on the chip. The memory range should have been set for
705 * the driver when it was added as a child.
707 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
708 device_printf(dev, "Error: could not allocate mem resources\n");
712 /* Request the IRQ resources */
713 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
714 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
715 device_printf(dev, "Error: could not allocate irq resources\n");
719 /* Setup the IRQ resources */
720 if (ti_gpio_attach_intr(dev) != 0) {
721 ti_gpio_detach_intr(dev);
722 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
723 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
727 /* We need to go through each block and ensure the clocks are running and
728 * the module is enabled. It might be better to do this only when the
729 * pins are configured which would result in less power used if the GPIO
730 * pins weren't used ...
732 for (i = 0; i < ti_max_gpio_banks(); i++) {
733 if (sc->sc_mem_res[i] != NULL) {
734 /* Initialize the GPIO module. */
735 err = ti_gpio_bank_init(dev, i);
737 ti_gpio_detach_intr(dev);
738 bus_release_resources(dev, ti_gpio_irq_spec,
740 bus_release_resources(dev, ti_gpio_mem_spec,
747 /* Finish of the probe call */
748 device_add_child(dev, "gpioc", -1);
749 device_add_child(dev, "gpiobus", -1);
751 return (bus_generic_attach(dev));
755 * ti_gpio_detach - detach function for the driver
756 * @dev: scm device handle
758 * Allocates and sets up the driver context, this simply entails creating a
759 * bus mappings for the SCM register set.
768 ti_gpio_detach(device_t dev)
770 struct ti_gpio_softc *sc = device_get_softc(dev);
773 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
775 /* Disable all interrupts */
776 for (i = 0; i < ti_max_gpio_banks(); i++) {
777 if (sc->sc_mem_res[i] != NULL)
778 ti_gpio_intr_clr(sc, i, 0xffffffff);
781 bus_generic_detach(dev);
783 /* Release the memory and IRQ resources. */
784 ti_gpio_detach_intr(dev);
785 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
786 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
788 TI_GPIO_LOCK_DESTROY(sc);
794 ti_gpio_get_node(device_t bus, device_t dev)
797 /* We only have one child, the GPIO bus, which needs our own node. */
798 return (ofw_bus_get_node(bus));
801 static device_method_t ti_gpio_methods[] = {
802 DEVMETHOD(device_attach, ti_gpio_attach),
803 DEVMETHOD(device_detach, ti_gpio_detach),
806 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
807 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
808 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
809 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
810 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
811 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
812 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
813 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
815 /* ofw_bus interface */
816 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
821 driver_t ti_gpio_driver = {
824 sizeof(struct ti_gpio_softc),