2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
47 #include <sys/mutex.h>
49 #include <sys/interrupt.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
53 #include <machine/resource.h>
55 #include <arm/ti/ti_cpuid.h>
56 #include <arm/ti/ti_gpio.h>
57 #include <arm/ti/ti_scm.h>
58 #include <arm/ti/ti_prcm.h>
59 #include <arm/ti/ti_hwmods.h>
61 #include <dev/fdt/fdt_common.h>
62 #include <dev/gpio/gpiobusvar.h>
63 #include <dev/ofw/openfirm.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
68 #include "ti_gpio_if.h"
73 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
77 /* Register definitions */
78 #define TI_GPIO_REVISION 0x0000
79 #define TI_GPIO_SYSCONFIG 0x0010
80 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
81 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
82 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */
83 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */
84 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */
85 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */
86 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */
87 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */
88 #define TI_GPIO_IRQWAKEN_0 0x0044
89 #define TI_GPIO_IRQWAKEN_1 0x0048
90 #define TI_GPIO_SYSSTATUS 0x0114
91 #define TI_GPIO_IRQSTATUS1 0x0118
92 #define TI_GPIO_IRQENABLE1 0x011C
93 #define TI_GPIO_WAKEUPENABLE 0x0120
94 #define TI_GPIO_IRQSTATUS2 0x0128
95 #define TI_GPIO_IRQENABLE2 0x012C
96 #define TI_GPIO_CTRL 0x0130
97 #define TI_GPIO_OE 0x0134
98 #define TI_GPIO_DATAIN 0x0138
99 #define TI_GPIO_DATAOUT 0x013C
100 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */
101 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */
102 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */
103 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */
104 #define TI_GPIO_DEBOUNCENABLE 0x0150
105 #define TI_GPIO_DEBOUNCINGTIME 0x0154
106 #define TI_GPIO_CLEARWKUPENA 0x0180
107 #define TI_GPIO_SETWKUENA 0x0184
108 #define TI_GPIO_CLEARDATAOUT 0x0190
109 #define TI_GPIO_SETDATAOUT 0x0194
111 /* Other SoC Specific definitions */
112 #define OMAP4_FIRST_GPIO_BANK 1
113 #define OMAP4_INTR_PER_BANK 1
114 #define OMAP4_GPIO_REV 0x50600801
115 #define AM335X_FIRST_GPIO_BANK 0
116 #define AM335X_INTR_PER_BANK 2
117 #define AM335X_GPIO_REV 0x50600801
118 #define PINS_PER_BANK 32
119 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
121 static int ti_gpio_intr(void *arg);
122 static int ti_gpio_detach(device_t);
125 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc);
126 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc);
130 ti_first_gpio_bank(void)
135 return (OMAP4_FIRST_GPIO_BANK);
139 return (AM335X_FIRST_GPIO_BANK);
151 return (OMAP4_GPIO_REV);
155 return (AM335X_GPIO_REV);
162 * Macros for driver mutex locking
164 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
165 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
166 #define TI_GPIO_LOCK_INIT(_sc) \
167 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
169 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
170 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
171 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
174 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
175 * @sc: GPIO device context
176 * @bank: The bank to read from
177 * @off: The offset of a register from the GPIO register address range
181 * 32-bit value read from the register.
183 static inline uint32_t
184 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
186 return (bus_read_4(sc->sc_mem_res, off));
190 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
191 * @sc: GPIO device context
192 * @bank: The bank to write to
193 * @off: The offset of a register from the GPIO register address range
194 * @val: The value to write into the register
200 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
203 bus_write_4(sc->sc_mem_res, off, val);
207 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
210 /* We clear both set of registers. */
211 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
212 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
216 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
220 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
221 * also activate only the first interrupt.
223 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
227 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
231 * Acknowledge the interrupt on both registers even if we use only
234 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
235 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
238 static inline uint32_t
239 ti_gpio_intr_status(struct ti_gpio_softc *sc)
243 /* Get the status from both registers. */
244 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
245 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
251 ti_gpio_get_bus(device_t dev)
253 struct ti_gpio_softc *sc;
255 sc = device_get_softc(dev);
257 return (sc->sc_busdev);
261 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
262 * @dev: gpio device handle
263 * @maxpin: pointer to a value that upon return will contain the maximum number
264 * of pins in the device.
268 * No locking required, returns static data.
271 * Returns 0 on success otherwise an error code
274 ti_gpio_pin_max(device_t dev, int *maxpin)
277 *maxpin = PINS_PER_BANK - 1;
283 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
286 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
293 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin
294 * @dev: gpio device handle
295 * @pin: the number of the pin
296 * @caps: pointer to a value that upon return will contain the capabilities
298 * Currently all pins have the same capability, notably:
302 * - GPIO_PIN_PULLDOWN
303 * - GPIO_INTR_LEVEL_LOW
304 * - GPIO_INTR_LEVEL_HIGH
305 * - GPIO_INTR_EDGE_RISING
306 * - GPIO_INTR_EDGE_FALLING
307 * - GPIO_INTR_EDGE_BOTH
310 * No locking required, returns static data.
313 * Returns 0 on success otherwise an error code
316 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
318 struct ti_gpio_softc *sc;
320 sc = device_get_softc(dev);
321 if (ti_gpio_valid_pin(sc, pin) != 0)
325 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
326 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
327 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
328 GPIO_INTR_EDGE_BOTH);
330 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
338 * ti_gpio_pin_getflags - Gets the current flags of a given pin
339 * @dev: gpio device handle
340 * @pin: the number of the pin
341 * @flags: upon return will contain the current flags of the pin
343 * Reads the current flags of a given pin, here we actually read the H/W
344 * registers to determine the flags, rather than storing the value in the
348 * Internally locks the context
351 * Returns 0 on success otherwise an error code
354 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
356 struct ti_gpio_softc *sc;
358 sc = device_get_softc(dev);
359 if (ti_gpio_valid_pin(sc, pin) != 0)
362 /* Get the current pin state */
364 TI_GPIO_GET_FLAGS(dev, pin, flags);
371 * ti_gpio_pin_getname - Gets the name of a given pin
372 * @dev: gpio device handle
373 * @pin: the number of the pin
374 * @name: buffer to put the name in
376 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
380 * No locking required, returns static data.
383 * Returns 0 on success otherwise an error code
386 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
388 struct ti_gpio_softc *sc;
390 sc = device_get_softc(dev);
391 if (ti_gpio_valid_pin(sc, pin) != 0)
394 /* Set a very simple name */
395 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
396 name[GPIOMAXNAME - 1] = '\0';
402 * ti_gpio_pin_setflags - Sets the flags for a given pin
403 * @dev: gpio device handle
404 * @pin: the number of the pin
405 * @flags: the flags to set
407 * The flags of the pin correspond to things like input/output mode, pull-ups,
408 * pull-downs, etc. This driver doesn't support all flags, only the following:
412 * - GPIO_PIN_PULLDOWN
415 * Internally locks the context
418 * Returns 0 on success otherwise an error code
421 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
423 struct ti_gpio_softc *sc;
426 sc = device_get_softc(dev);
427 if (ti_gpio_valid_pin(sc, pin) != 0)
430 /* Set the GPIO mode and state */
432 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
437 /* If configuring as an output set the "output enable" bit */
438 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
439 if (flags & GPIO_PIN_INPUT)
440 oe |= TI_GPIO_MASK(pin);
442 oe &= ~TI_GPIO_MASK(pin);
443 ti_gpio_write_4(sc, TI_GPIO_OE, oe);
450 * ti_gpio_pin_set - Sets the current level on a GPIO pin
451 * @dev: gpio device handle
452 * @pin: the number of the pin
453 * @value: non-zero value will drive the pin high, otherwise the pin is
458 * Internally locks the context
461 * Returns 0 on success otherwise a error code
464 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
466 struct ti_gpio_softc *sc;
469 sc = device_get_softc(dev);
470 if (ti_gpio_valid_pin(sc, pin) != 0)
474 if (value == GPIO_PIN_LOW)
475 reg = TI_GPIO_CLEARDATAOUT;
477 reg = TI_GPIO_SETDATAOUT;
478 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
485 * ti_gpio_pin_get - Gets the current level on a GPIO pin
486 * @dev: gpio device handle
487 * @pin: the number of the pin
488 * @value: pointer to a value that upond return will contain the pin value
490 * The pin must be configured as an input pin beforehand, otherwise this
491 * function will fail.
494 * Internally locks the context
497 * Returns 0 on success otherwise a error code
500 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
502 struct ti_gpio_softc *sc;
503 uint32_t oe, reg, val;
505 sc = device_get_softc(dev);
506 if (ti_gpio_valid_pin(sc, pin) != 0)
510 * Return data from output latch when set as output and from the
511 * input register otherwise.
514 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
515 if (oe & TI_GPIO_MASK(pin))
516 reg = TI_GPIO_DATAIN;
518 reg = TI_GPIO_DATAOUT;
519 val = ti_gpio_read_4(sc, reg);
520 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
527 * ti_gpio_pin_toggle - Toggles a given GPIO pin
528 * @dev: gpio device handle
529 * @pin: the number of the pin
533 * Internally locks the context
536 * Returns 0 on success otherwise a error code
539 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
541 struct ti_gpio_softc *sc;
544 sc = device_get_softc(dev);
545 if (ti_gpio_valid_pin(sc, pin) != 0)
550 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
551 if (val & TI_GPIO_MASK(pin))
552 reg = TI_GPIO_CLEARDATAOUT;
554 reg = TI_GPIO_SETDATAOUT;
555 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
563 * ti_gpio_intr - ISR for all GPIO modules
564 * @arg: the soft context pointer
567 * Internally locks the context
571 ti_gpio_intr(void *arg)
574 struct intr_event *event;
575 struct ti_gpio_softc *sc;
578 sc = (struct ti_gpio_softc *)arg;
580 reg = 0; /* squelch bogus gcc warning */
581 reg = ti_gpio_intr_status(sc);
582 for (irq = 0; irq < sc->sc_maxpin; irq++) {
583 if ((reg & TI_GPIO_MASK(irq)) == 0)
585 event = sc->sc_events[irq];
586 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
587 intr_event_handle(event, NULL);
589 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq);
590 /* Ack the IRQ Status bit. */
591 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq));
594 return (FILTER_HANDLED);
599 ti_gpio_bank_init(device_t dev)
602 struct ti_gpio_softc *sc;
603 uint32_t flags, reg_oe, reg_set, rev;
606 sc = device_get_softc(dev);
608 /* Enable the interface and functional clocks for the module. */
609 clk = ti_hwmods_get_clock(dev);
610 if (clk == INVALID_CLK_IDENT) {
611 device_printf(dev, "failed to get device id based on ti,hwmods\n");
615 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank();
616 ti_prcm_clk_enable(clk);
619 * Read the revision number of the module. TI don't publish the
620 * actual revision numbers, so instead the values have been
621 * determined by experimentation.
623 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION);
625 /* Check the revision. */
626 if (rev != ti_gpio_rev()) {
627 device_printf(dev, "Warning: could not determine the revision "
628 "of GPIO module (revision:0x%08x)\n", rev);
632 /* Disable interrupts for all pins. */
633 ti_gpio_intr_clr(sc, 0xffffffff);
635 /* Init OE register based on pads configuration. */
638 for (pin = 0; pin < PINS_PER_BANK; pin++) {
639 TI_GPIO_GET_FLAGS(dev, pin, &flags);
640 if (flags & GPIO_PIN_OUTPUT) {
641 reg_oe &= ~(1UL << pin);
642 if (flags & GPIO_PIN_PULLUP)
643 reg_set |= (1UL << pin);
646 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
648 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set);
654 * ti_gpio_attach - attach function for the driver
655 * @dev: gpio device handle
657 * Allocates and sets up the driver context for all GPIO banks. This function
658 * expects the memory ranges and IRQs to already be allocated to the driver.
667 ti_gpio_attach(device_t dev)
669 struct ti_gpio_softc *sc;
675 sc = device_get_softc(dev);
677 TI_GPIO_LOCK_INIT(sc);
678 ti_gpio_pin_max(dev, &sc->sc_maxpin);
682 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
683 &sc->sc_mem_rid, RF_ACTIVE);
684 if (!sc->sc_mem_res) {
685 device_printf(dev, "Error: could not allocate mem resources\n");
691 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
692 &sc->sc_irq_rid, RF_ACTIVE);
693 if (!sc->sc_irq_res) {
694 device_printf(dev, "Error: could not allocate irq resources\n");
700 * Register our interrupt filter for each of the IRQ resources.
702 if (bus_setup_intr(dev, sc->sc_irq_res,
703 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
704 &sc->sc_irq_hdl) != 0) {
706 "WARNING: unable to register interrupt filter\n");
712 if (ti_gpio_pic_attach(sc) != 0) {
713 device_printf(dev, "WARNING: unable to attach PIC\n");
719 * Initialize the interrupt settings. The default is active-low
722 sc->sc_irq_trigger = malloc(
723 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin,
724 M_DEVBUF, M_WAITOK | M_ZERO);
725 sc->sc_irq_polarity = malloc(
726 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin,
727 M_DEVBUF, M_WAITOK | M_ZERO);
728 for (i = 0; i < sc->sc_maxpin; i++) {
729 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
730 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
733 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin,
734 M_DEVBUF, M_WAITOK | M_ZERO);
736 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin,
737 M_DEVBUF, M_WAITOK | M_ZERO);
739 /* We need to go through each block and ensure the clocks are running and
740 * the module is enabled. It might be better to do this only when the
741 * pins are configured which would result in less power used if the GPIO
742 * pins weren't used ...
744 if (sc->sc_mem_res != NULL) {
745 /* Initialize the GPIO module. */
746 err = ti_gpio_bank_init(dev);
753 sc->sc_busdev = gpiobus_attach_bus(dev);
754 if (sc->sc_busdev == NULL) {
763 * ti_gpio_detach - detach function for the driver
764 * @dev: scm device handle
766 * Allocates and sets up the driver context, this simply entails creating a
767 * bus mappings for the SCM register set.
776 ti_gpio_detach(device_t dev)
778 struct ti_gpio_softc *sc = device_get_softc(dev);
780 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
782 /* Disable all interrupts */
783 if (sc->sc_mem_res != NULL)
784 ti_gpio_intr_clr(sc, 0xffffffff);
785 gpiobus_detach_bus(dev);
787 if (sc->sc_isrcs != NULL)
788 ti_gpio_pic_detach(sc);
791 free(sc->sc_events, M_DEVBUF);
792 if (sc->sc_mask_args)
793 free(sc->sc_mask_args, M_DEVBUF);
794 if (sc->sc_irq_polarity)
795 free(sc->sc_irq_polarity, M_DEVBUF);
796 if (sc->sc_irq_trigger)
797 free(sc->sc_irq_trigger, M_DEVBUF);
799 /* Release the memory and IRQ resources. */
800 if (sc->sc_irq_hdl) {
801 bus_teardown_intr(dev, sc->sc_irq_res,
804 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
806 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
808 TI_GPIO_LOCK_DESTROY(sc);
815 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask,
820 value = ti_gpio_read_4(sc, reg);
821 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask);
825 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
828 /* Writing a 0 has no effect. */
829 ti_gpio_intr_clr(sc, tgi->tgi_mask);
833 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
836 /* Writing a 0 has no effect. */
837 ti_gpio_intr_set(sc, tgi->tgi_mask);
841 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
844 /* Writing a 0 has no effect. */
845 ti_gpio_intr_ack(sc, tgi->tgi_mask);
849 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi)
852 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW ||
853 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH);
857 ti_gpio_intr(void *arg)
861 struct ti_gpio_softc *sc;
862 struct trapframe *tf;
863 struct ti_gpio_irqsrc *tgi;
865 sc = (struct ti_gpio_softc *)arg;
866 tf = curthread->td_intr_frame;
868 reg = ti_gpio_intr_status(sc);
869 for (irq = 0; irq < sc->sc_maxpin; irq++) {
870 tgi = &sc->sc_isrcs[irq];
871 if ((reg & tgi->tgi_mask) == 0)
873 if (!ti_gpio_isrc_is_level(tgi))
874 ti_gpio_isrc_eoi(sc, tgi);
875 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {
876 ti_gpio_isrc_mask(sc, tgi);
877 if (ti_gpio_isrc_is_level(tgi))
878 ti_gpio_isrc_eoi(sc, tgi);
879 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
883 return (FILTER_HANDLED);
887 ti_gpio_pic_attach(struct ti_gpio_softc *sc)
893 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF,
896 name = device_get_nameunit(sc->sc_dev);
897 for (irq = 0; irq < sc->sc_maxpin; irq++) {
898 sc->sc_isrcs[irq].tgi_irq = irq;
899 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq);
900 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM;
902 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc,
903 sc->sc_dev, 0, "%s,%u", name, irq);
905 return (error); /* XXX deregister ISRCs */
907 if (intr_pic_register(sc->sc_dev,
908 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL)
915 ti_gpio_pic_detach(struct ti_gpio_softc *sc)
919 * There has not been established any procedure yet
920 * how to detach PIC from living system correctly.
922 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
927 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi,
932 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask,
933 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH);
934 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask,
935 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH);
936 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask,
937 mode == GPIO_INTR_LEVEL_HIGH);
938 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask,
939 mode == GPIO_INTR_LEVEL_LOW);
940 tgi->tgi_mode = mode;
945 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
947 struct ti_gpio_softc *sc = device_get_softc(dev);
948 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
950 ti_gpio_isrc_mask(sc, tgi);
954 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
956 struct ti_gpio_softc *sc = device_get_softc(dev);
957 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
959 arm_irq_memory_barrier(tgi->tgi_irq);
960 ti_gpio_isrc_unmask(sc, tgi);
964 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf,
965 u_int *irqp, uint32_t *modep)
970 * The first cell is the interrupt number.
971 * The second cell is used to specify flags:
972 * bits[3:0] trigger type and level flags:
973 * 1 = low-to-high edge triggered.
974 * 2 = high-to-low edge triggered.
975 * 4 = active high level-sensitive.
976 * 8 = active low level-sensitive.
978 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin)
981 /* Only reasonable modes are supported. */
982 if (daf->cells[1] == 1)
983 mode = GPIO_INTR_EDGE_RISING;
984 else if (daf->cells[1] == 2)
985 mode = GPIO_INTR_EDGE_FALLING;
986 else if (daf->cells[1] == 3)
987 mode = GPIO_INTR_EDGE_BOTH;
988 else if (daf->cells[1] == 4)
989 mode = GPIO_INTR_LEVEL_HIGH;
990 else if (daf->cells[1] == 8)
991 mode = GPIO_INTR_LEVEL_LOW;
995 *irqp = daf->cells[0];
1002 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag,
1003 u_int *irqp, uint32_t *modep)
1007 if (dag->gpio_pin_num >= sc->sc_maxpin)
1010 mode = dag->gpio_intr_mode;
1011 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH &&
1012 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING &&
1013 mode != GPIO_INTR_EDGE_BOTH)
1016 *irqp = dag->gpio_pin_num;
1023 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data,
1024 u_int *irqp, uint32_t *modep)
1027 switch (data->type) {
1028 case INTR_MAP_DATA_FDT:
1029 return (ti_gpio_pic_map_fdt(sc,
1030 (struct intr_map_data_fdt *)data, irqp, modep));
1031 case INTR_MAP_DATA_GPIO:
1032 return (ti_gpio_pic_map_gpio(sc,
1033 (struct intr_map_data_gpio *)data, irqp, modep));
1040 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1041 struct intr_irqsrc **isrcp)
1045 struct ti_gpio_softc *sc = device_get_softc(dev);
1047 error = ti_gpio_pic_map(sc, data, &irq, NULL);
1049 *isrcp = &sc->sc_isrcs[irq].tgi_isrc;
1054 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1056 struct ti_gpio_softc *sc = device_get_softc(dev);
1057 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1059 if (ti_gpio_isrc_is_level(tgi))
1060 ti_gpio_isrc_eoi(sc, tgi);
1064 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1067 ti_gpio_pic_enable_intr(dev, isrc);
1071 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1073 struct ti_gpio_softc *sc = device_get_softc(dev);
1074 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1076 ti_gpio_isrc_mask(sc, tgi);
1077 if (ti_gpio_isrc_is_level(tgi))
1078 ti_gpio_isrc_eoi(sc, tgi);
1082 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1083 struct resource *res, struct intr_map_data *data)
1087 struct ti_gpio_softc *sc;
1088 struct ti_gpio_irqsrc *tgi;
1093 sc = device_get_softc(dev);
1094 tgi = (struct ti_gpio_irqsrc *)isrc;
1096 /* Get and check config for an interrupt. */
1097 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq)
1101 * If this is a setup for another handler,
1102 * only check that its configuration match.
1104 if (isrc->isrc_handlers != 0)
1105 return (tgi->tgi_mode == mode ? 0 : EINVAL);
1107 ti_gpio_pic_config_intr(sc, tgi, mode);
1112 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1113 struct resource *res, struct intr_map_data *data)
1115 struct ti_gpio_softc *sc = device_get_softc(dev);
1116 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1118 if (isrc->isrc_handlers == 0)
1119 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM);
1125 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
1128 if (ti_gpio_valid_pin(sc, irq) != 0)
1131 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) {
1132 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1133 return (TI_GPIO_LEVELDETECT0);
1134 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1135 return (TI_GPIO_LEVELDETECT1);
1136 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) {
1137 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1138 return (TI_GPIO_FALLINGDETECT);
1139 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1140 return (TI_GPIO_RISINGDETECT);
1147 ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq)
1151 if (ti_gpio_valid_pin(sc, irq) != 0)
1155 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq));
1156 reg = ti_gpio_intr_reg(sc, irq);
1158 val = ti_gpio_read_4(sc, reg);
1159 val &= ~TI_GPIO_MASK(irq);
1160 ti_gpio_write_4(sc, reg, val);
1166 ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq)
1170 if (ti_gpio_valid_pin(sc, irq) != 0)
1174 reg = ti_gpio_intr_reg(sc, irq);
1176 val = ti_gpio_read_4(sc, reg);
1177 val |= TI_GPIO_MASK(irq);
1178 ti_gpio_write_4(sc, reg, val);
1179 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq));
1185 ti_gpio_mask_irq(void *source)
1187 struct ti_gpio_mask_arg *arg = source;
1189 ti_gpio_mask_irq_internal(arg->softc, arg->pin);
1193 ti_gpio_unmask_irq(void *source)
1195 struct ti_gpio_mask_arg *arg = source;
1197 ti_gpio_unmask_irq_internal(arg->softc, arg->pin);
1201 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid,
1202 struct resource *res)
1204 struct ti_gpio_mask_arg mask_arg;
1206 if (type != SYS_RES_IRQ)
1209 /* Unmask the interrupt. */
1210 mask_arg.pin = rman_get_start(res);
1211 mask_arg.softc = device_get_softc(dev);
1213 ti_gpio_unmask_irq((void *)&mask_arg);
1219 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid,
1220 struct resource *res)
1224 if (type != SYS_RES_IRQ)
1227 /* Mask the interrupt. */
1228 pin = rman_get_start(res);
1229 ti_gpio_mask_irq((void *)(uintptr_t)pin);
1235 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig,
1236 enum intr_polarity pol)
1238 struct ti_gpio_softc *sc;
1239 uint32_t oldreg, reg, val;
1241 sc = device_get_softc(dev);
1242 if (ti_gpio_valid_pin(sc, irq) != 0)
1245 /* There is no standard trigger or polarity. */
1246 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
1251 * TRM recommends add the new event before remove the old one to
1252 * avoid losing interrupts.
1254 oldreg = ti_gpio_intr_reg(sc, irq);
1255 sc->sc_irq_trigger[irq] = trig;
1256 sc->sc_irq_polarity[irq] = pol;
1257 reg = ti_gpio_intr_reg(sc, irq);
1259 /* Apply the new settings. */
1260 val = ti_gpio_read_4(sc, reg);
1261 val |= TI_GPIO_MASK(irq);
1262 ti_gpio_write_4(sc, reg, val);
1264 if (reg != oldreg && oldreg != 0) {
1265 /* Remove the old settings. */
1266 val = ti_gpio_read_4(sc, oldreg);
1267 val &= ~TI_GPIO_MASK(irq);
1268 ti_gpio_write_4(sc, oldreg, val);
1276 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires,
1277 int flags, driver_filter_t *filt, driver_intr_t *handler,
1278 void *arg, void **cookiep)
1280 struct ti_gpio_softc *sc;
1281 struct intr_event *event;
1284 sc = device_get_softc(dev);
1285 pin = rman_get_start(ires);
1286 if (ti_gpio_valid_pin(sc, pin) != 0)
1287 panic("%s: bad pin %d", __func__, pin);
1289 event = sc->sc_events[pin];
1290 if (event == NULL) {
1291 sc->sc_mask_args[pin].softc = sc;
1292 sc->sc_mask_args[pin].pin = pin;
1293 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0,
1294 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL,
1295 "gpio%d pin%d:", device_get_unit(dev), pin);
1298 sc->sc_events[pin] = event;
1300 intr_event_add_handler(event, device_get_nameunit(child), filt,
1301 handler, arg, intr_priority(flags), flags, cookiep);
1307 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires,
1310 struct ti_gpio_softc *sc;
1313 sc = device_get_softc(dev);
1314 pin = rman_get_start(ires);
1315 if (ti_gpio_valid_pin(sc, pin) != 0)
1316 panic("%s: bad pin %d", __func__, pin);
1317 if (sc->sc_events[pin] == NULL)
1318 panic("Trying to teardown unoccupied IRQ");
1319 err = intr_event_remove_handler(cookie);
1321 sc->sc_events[pin] = NULL;
1328 ti_gpio_get_node(device_t bus, device_t dev)
1331 /* We only have one child, the GPIO bus, which needs our own node. */
1332 return (ofw_bus_get_node(bus));
1335 static device_method_t ti_gpio_methods[] = {
1336 DEVMETHOD(device_attach, ti_gpio_attach),
1337 DEVMETHOD(device_detach, ti_gpio_detach),
1340 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
1341 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
1342 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
1343 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
1344 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
1345 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
1346 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
1347 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
1348 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
1351 /* Interrupt controller interface */
1352 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr),
1353 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr),
1354 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr),
1355 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr),
1356 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr),
1357 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter),
1358 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread),
1359 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread),
1362 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource),
1363 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource),
1364 DEVMETHOD(bus_config_intr, ti_gpio_config_intr),
1365 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr),
1366 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr),
1369 /* ofw_bus interface */
1370 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
1375 driver_t ti_gpio_driver = {
1378 sizeof(struct ti_gpio_softc),