2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
47 #include <sys/mutex.h>
49 #include <sys/interrupt.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
53 #include <machine/resource.h>
55 #include <arm/ti/ti_cpuid.h>
56 #include <arm/ti/ti_gpio.h>
57 #include <arm/ti/ti_scm.h>
58 #include <arm/ti/ti_prcm.h>
59 #include <arm/ti/ti_hwmods.h>
61 #include <dev/gpio/gpiobusvar.h>
62 #include <dev/ofw/openfirm.h>
63 #include <dev/ofw/ofw_bus.h>
64 #include <dev/ofw/ofw_bus_subr.h>
67 #include "ti_gpio_if.h"
70 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
74 /* Register definitions */
75 #define TI_GPIO_REVISION 0x0000
76 #define TI_GPIO_SYSCONFIG 0x0010
77 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
78 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
79 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */
80 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */
81 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */
82 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */
83 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */
84 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */
85 #define TI_GPIO_IRQWAKEN_0 0x0044
86 #define TI_GPIO_IRQWAKEN_1 0x0048
87 #define TI_GPIO_SYSSTATUS 0x0114
88 #define TI_GPIO_IRQSTATUS1 0x0118
89 #define TI_GPIO_IRQENABLE1 0x011C
90 #define TI_GPIO_WAKEUPENABLE 0x0120
91 #define TI_GPIO_IRQSTATUS2 0x0128
92 #define TI_GPIO_IRQENABLE2 0x012C
93 #define TI_GPIO_CTRL 0x0130
94 #define TI_GPIO_OE 0x0134
95 #define TI_GPIO_DATAIN 0x0138
96 #define TI_GPIO_DATAOUT 0x013C
97 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */
98 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */
99 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */
100 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */
101 #define TI_GPIO_DEBOUNCENABLE 0x0150
102 #define TI_GPIO_DEBOUNCINGTIME 0x0154
103 #define TI_GPIO_CLEARWKUPENA 0x0180
104 #define TI_GPIO_SETWKUENA 0x0184
105 #define TI_GPIO_CLEARDATAOUT 0x0190
106 #define TI_GPIO_SETDATAOUT 0x0194
108 /* Other SoC Specific definitions */
109 #define OMAP4_FIRST_GPIO_BANK 1
110 #define OMAP4_INTR_PER_BANK 1
111 #define OMAP4_GPIO_REV 0x50600801
112 #define AM335X_FIRST_GPIO_BANK 0
113 #define AM335X_INTR_PER_BANK 2
114 #define AM335X_GPIO_REV 0x50600801
115 #define PINS_PER_BANK 32
116 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
118 static int ti_gpio_intr(void *arg);
119 static int ti_gpio_detach(device_t);
121 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc);
122 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc);
125 ti_first_gpio_bank(void)
130 return (OMAP4_FIRST_GPIO_BANK);
134 return (AM335X_FIRST_GPIO_BANK);
146 return (OMAP4_GPIO_REV);
150 return (AM335X_GPIO_REV);
157 * Macros for driver mutex locking
159 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
160 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
161 #define TI_GPIO_LOCK_INIT(_sc) \
162 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
164 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
165 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
166 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
169 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
170 * @sc: GPIO device context
171 * @bank: The bank to read from
172 * @off: The offset of a register from the GPIO register address range
176 * 32-bit value read from the register.
178 static inline uint32_t
179 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
181 return (bus_read_4(sc->sc_mem_res, off));
185 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
186 * @sc: GPIO device context
187 * @bank: The bank to write to
188 * @off: The offset of a register from the GPIO register address range
189 * @val: The value to write into the register
195 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
198 bus_write_4(sc->sc_mem_res, off, val);
202 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
205 /* We clear both set of registers. */
206 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
207 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
211 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
215 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
216 * also activate only the first interrupt.
218 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
222 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
226 * Acknowledge the interrupt on both registers even if we use only
229 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
230 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
233 static inline uint32_t
234 ti_gpio_intr_status(struct ti_gpio_softc *sc)
238 /* Get the status from both registers. */
239 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
240 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
246 ti_gpio_get_bus(device_t dev)
248 struct ti_gpio_softc *sc;
250 sc = device_get_softc(dev);
252 return (sc->sc_busdev);
256 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
257 * @dev: gpio device handle
258 * @maxpin: pointer to a value that upon return will contain the maximum number
259 * of pins in the device.
263 * No locking required, returns static data.
266 * Returns 0 on success otherwise an error code
269 ti_gpio_pin_max(device_t dev, int *maxpin)
272 *maxpin = PINS_PER_BANK - 1;
278 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
281 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
288 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin
289 * @dev: gpio device handle
290 * @pin: the number of the pin
291 * @caps: pointer to a value that upon return will contain the capabilities
293 * Currently all pins have the same capability, notably:
297 * - GPIO_PIN_PULLDOWN
298 * - GPIO_INTR_LEVEL_LOW
299 * - GPIO_INTR_LEVEL_HIGH
300 * - GPIO_INTR_EDGE_RISING
301 * - GPIO_INTR_EDGE_FALLING
302 * - GPIO_INTR_EDGE_BOTH
305 * No locking required, returns static data.
308 * Returns 0 on success otherwise an error code
311 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
313 struct ti_gpio_softc *sc;
315 sc = device_get_softc(dev);
316 if (ti_gpio_valid_pin(sc, pin) != 0)
319 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
320 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
321 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
322 GPIO_INTR_EDGE_BOTH);
328 * ti_gpio_pin_getflags - Gets the current flags of a given pin
329 * @dev: gpio device handle
330 * @pin: the number of the pin
331 * @flags: upon return will contain the current flags of the pin
333 * Reads the current flags of a given pin, here we actually read the H/W
334 * registers to determine the flags, rather than storing the value in the
338 * Internally locks the context
341 * Returns 0 on success otherwise an error code
344 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
346 struct ti_gpio_softc *sc;
348 sc = device_get_softc(dev);
349 if (ti_gpio_valid_pin(sc, pin) != 0)
352 /* Get the current pin state */
354 TI_GPIO_GET_FLAGS(dev, pin, flags);
361 * ti_gpio_pin_getname - Gets the name of a given pin
362 * @dev: gpio device handle
363 * @pin: the number of the pin
364 * @name: buffer to put the name in
366 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
370 * No locking required, returns static data.
373 * Returns 0 on success otherwise an error code
376 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
378 struct ti_gpio_softc *sc;
380 sc = device_get_softc(dev);
381 if (ti_gpio_valid_pin(sc, pin) != 0)
384 /* Set a very simple name */
385 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
386 name[GPIOMAXNAME - 1] = '\0';
392 * ti_gpio_pin_setflags - Sets the flags for a given pin
393 * @dev: gpio device handle
394 * @pin: the number of the pin
395 * @flags: the flags to set
397 * The flags of the pin correspond to things like input/output mode, pull-ups,
398 * pull-downs, etc. This driver doesn't support all flags, only the following:
402 * - GPIO_PIN_PULLDOWN
405 * Internally locks the context
408 * Returns 0 on success otherwise an error code
411 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
413 struct ti_gpio_softc *sc;
416 sc = device_get_softc(dev);
417 if (ti_gpio_valid_pin(sc, pin) != 0)
420 /* Set the GPIO mode and state */
422 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
427 /* If configuring as an output set the "output enable" bit */
428 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
429 if (flags & GPIO_PIN_INPUT)
430 oe |= TI_GPIO_MASK(pin);
432 oe &= ~TI_GPIO_MASK(pin);
433 ti_gpio_write_4(sc, TI_GPIO_OE, oe);
440 * ti_gpio_pin_set - Sets the current level on a GPIO pin
441 * @dev: gpio device handle
442 * @pin: the number of the pin
443 * @value: non-zero value will drive the pin high, otherwise the pin is
448 * Internally locks the context
451 * Returns 0 on success otherwise a error code
454 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
456 struct ti_gpio_softc *sc;
459 sc = device_get_softc(dev);
460 if (ti_gpio_valid_pin(sc, pin) != 0)
464 if (value == GPIO_PIN_LOW)
465 reg = TI_GPIO_CLEARDATAOUT;
467 reg = TI_GPIO_SETDATAOUT;
468 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
475 * ti_gpio_pin_get - Gets the current level on a GPIO pin
476 * @dev: gpio device handle
477 * @pin: the number of the pin
478 * @value: pointer to a value that upond return will contain the pin value
480 * The pin must be configured as an input pin beforehand, otherwise this
481 * function will fail.
484 * Internally locks the context
487 * Returns 0 on success otherwise a error code
490 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
492 struct ti_gpio_softc *sc;
493 uint32_t oe, reg, val;
495 sc = device_get_softc(dev);
496 if (ti_gpio_valid_pin(sc, pin) != 0)
500 * Return data from output latch when set as output and from the
501 * input register otherwise.
504 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
505 if (oe & TI_GPIO_MASK(pin))
506 reg = TI_GPIO_DATAIN;
508 reg = TI_GPIO_DATAOUT;
509 val = ti_gpio_read_4(sc, reg);
510 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
517 * ti_gpio_pin_toggle - Toggles a given GPIO pin
518 * @dev: gpio device handle
519 * @pin: the number of the pin
523 * Internally locks the context
526 * Returns 0 on success otherwise a error code
529 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
531 struct ti_gpio_softc *sc;
534 sc = device_get_softc(dev);
535 if (ti_gpio_valid_pin(sc, pin) != 0)
540 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
541 if (val & TI_GPIO_MASK(pin))
542 reg = TI_GPIO_CLEARDATAOUT;
544 reg = TI_GPIO_SETDATAOUT;
545 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
552 ti_gpio_bank_init(device_t dev)
555 struct ti_gpio_softc *sc;
556 uint32_t flags, reg_oe, reg_set, rev;
559 sc = device_get_softc(dev);
561 /* Enable the interface and functional clocks for the module. */
562 clk = ti_hwmods_get_clock(dev);
563 if (clk == INVALID_CLK_IDENT) {
564 device_printf(dev, "failed to get device id based on ti,hwmods\n");
568 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank();
569 ti_prcm_clk_enable(clk);
572 * Read the revision number of the module. TI don't publish the
573 * actual revision numbers, so instead the values have been
574 * determined by experimentation.
576 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION);
578 /* Check the revision. */
579 if (rev != ti_gpio_rev()) {
580 device_printf(dev, "Warning: could not determine the revision "
581 "of GPIO module (revision:0x%08x)\n", rev);
585 /* Disable interrupts for all pins. */
586 ti_gpio_intr_clr(sc, 0xffffffff);
588 /* Init OE register based on pads configuration. */
591 for (pin = 0; pin < PINS_PER_BANK; pin++) {
592 TI_GPIO_GET_FLAGS(dev, pin, &flags);
593 if (flags & GPIO_PIN_OUTPUT) {
594 reg_oe &= ~(1UL << pin);
595 if (flags & GPIO_PIN_PULLUP)
596 reg_set |= (1UL << pin);
599 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
601 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set);
607 * ti_gpio_attach - attach function for the driver
608 * @dev: gpio device handle
610 * Allocates and sets up the driver context for all GPIO banks. This function
611 * expects the memory ranges and IRQs to already be allocated to the driver.
620 ti_gpio_attach(device_t dev)
622 struct ti_gpio_softc *sc;
625 sc = device_get_softc(dev);
627 TI_GPIO_LOCK_INIT(sc);
628 ti_gpio_pin_max(dev, &sc->sc_maxpin);
632 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
633 &sc->sc_mem_rid, RF_ACTIVE);
634 if (!sc->sc_mem_res) {
635 device_printf(dev, "Error: could not allocate mem resources\n");
641 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
642 &sc->sc_irq_rid, RF_ACTIVE);
643 if (!sc->sc_irq_res) {
644 device_printf(dev, "Error: could not allocate irq resources\n");
650 * Register our interrupt filter for each of the IRQ resources.
652 if (bus_setup_intr(dev, sc->sc_irq_res,
653 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
654 &sc->sc_irq_hdl) != 0) {
656 "WARNING: unable to register interrupt filter\n");
661 if (ti_gpio_pic_attach(sc) != 0) {
662 device_printf(dev, "WARNING: unable to attach PIC\n");
667 /* We need to go through each block and ensure the clocks are running and
668 * the module is enabled. It might be better to do this only when the
669 * pins are configured which would result in less power used if the GPIO
670 * pins weren't used ...
672 if (sc->sc_mem_res != NULL) {
673 /* Initialize the GPIO module. */
674 err = ti_gpio_bank_init(dev);
681 sc->sc_busdev = gpiobus_attach_bus(dev);
682 if (sc->sc_busdev == NULL) {
691 * ti_gpio_detach - detach function for the driver
692 * @dev: scm device handle
694 * Allocates and sets up the driver context, this simply entails creating a
695 * bus mappings for the SCM register set.
704 ti_gpio_detach(device_t dev)
706 struct ti_gpio_softc *sc = device_get_softc(dev);
708 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
710 /* Disable all interrupts */
711 if (sc->sc_mem_res != NULL)
712 ti_gpio_intr_clr(sc, 0xffffffff);
713 if (sc->sc_busdev != NULL)
714 gpiobus_detach_bus(dev);
715 if (sc->sc_isrcs != NULL)
716 ti_gpio_pic_detach(sc);
717 /* Release the memory and IRQ resources. */
718 if (sc->sc_irq_hdl) {
719 bus_teardown_intr(dev, sc->sc_irq_res,
723 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
726 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
728 TI_GPIO_LOCK_DESTROY(sc);
734 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask,
739 value = ti_gpio_read_4(sc, reg);
740 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask);
744 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
747 /* Writing a 0 has no effect. */
748 ti_gpio_intr_clr(sc, tgi->tgi_mask);
752 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
755 /* Writing a 0 has no effect. */
756 ti_gpio_intr_set(sc, tgi->tgi_mask);
760 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
763 /* Writing a 0 has no effect. */
764 ti_gpio_intr_ack(sc, tgi->tgi_mask);
768 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi)
771 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW ||
772 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH);
776 ti_gpio_intr(void *arg)
780 struct ti_gpio_softc *sc;
781 struct trapframe *tf;
782 struct ti_gpio_irqsrc *tgi;
784 sc = (struct ti_gpio_softc *)arg;
785 tf = curthread->td_intr_frame;
787 reg = ti_gpio_intr_status(sc);
788 for (irq = 0; irq < sc->sc_maxpin; irq++) {
789 tgi = &sc->sc_isrcs[irq];
790 if ((reg & tgi->tgi_mask) == 0)
792 if (!ti_gpio_isrc_is_level(tgi))
793 ti_gpio_isrc_eoi(sc, tgi);
794 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {
795 ti_gpio_isrc_mask(sc, tgi);
796 if (ti_gpio_isrc_is_level(tgi))
797 ti_gpio_isrc_eoi(sc, tgi);
798 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
802 return (FILTER_HANDLED);
806 ti_gpio_pic_attach(struct ti_gpio_softc *sc)
812 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF,
815 name = device_get_nameunit(sc->sc_dev);
816 for (irq = 0; irq < sc->sc_maxpin; irq++) {
817 sc->sc_isrcs[irq].tgi_irq = irq;
818 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq);
819 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM;
821 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc,
822 sc->sc_dev, 0, "%s,%u", name, irq);
824 return (error); /* XXX deregister ISRCs */
826 if (intr_pic_register(sc->sc_dev,
827 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL)
834 ti_gpio_pic_detach(struct ti_gpio_softc *sc)
838 * There has not been established any procedure yet
839 * how to detach PIC from living system correctly.
841 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
846 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi,
851 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask,
852 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH);
853 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask,
854 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH);
855 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask,
856 mode == GPIO_INTR_LEVEL_HIGH);
857 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask,
858 mode == GPIO_INTR_LEVEL_LOW);
859 tgi->tgi_mode = mode;
864 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
866 struct ti_gpio_softc *sc = device_get_softc(dev);
867 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
869 ti_gpio_isrc_mask(sc, tgi);
873 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
875 struct ti_gpio_softc *sc = device_get_softc(dev);
876 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
878 arm_irq_memory_barrier(tgi->tgi_irq);
879 ti_gpio_isrc_unmask(sc, tgi);
883 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf,
884 u_int *irqp, uint32_t *modep)
889 * The first cell is the interrupt number.
890 * The second cell is used to specify flags:
891 * bits[3:0] trigger type and level flags:
892 * 1 = low-to-high edge triggered.
893 * 2 = high-to-low edge triggered.
894 * 4 = active high level-sensitive.
895 * 8 = active low level-sensitive.
897 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin)
900 /* Only reasonable modes are supported. */
901 if (daf->cells[1] == 1)
902 mode = GPIO_INTR_EDGE_RISING;
903 else if (daf->cells[1] == 2)
904 mode = GPIO_INTR_EDGE_FALLING;
905 else if (daf->cells[1] == 3)
906 mode = GPIO_INTR_EDGE_BOTH;
907 else if (daf->cells[1] == 4)
908 mode = GPIO_INTR_LEVEL_HIGH;
909 else if (daf->cells[1] == 8)
910 mode = GPIO_INTR_LEVEL_LOW;
914 *irqp = daf->cells[0];
921 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag,
922 u_int *irqp, uint32_t *modep)
926 if (dag->gpio_pin_num >= sc->sc_maxpin)
929 mode = dag->gpio_intr_mode;
930 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH &&
931 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING &&
932 mode != GPIO_INTR_EDGE_BOTH)
935 *irqp = dag->gpio_pin_num;
942 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data,
943 u_int *irqp, uint32_t *modep)
946 switch (data->type) {
947 case INTR_MAP_DATA_FDT:
948 return (ti_gpio_pic_map_fdt(sc,
949 (struct intr_map_data_fdt *)data, irqp, modep));
950 case INTR_MAP_DATA_GPIO:
951 return (ti_gpio_pic_map_gpio(sc,
952 (struct intr_map_data_gpio *)data, irqp, modep));
959 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
960 struct intr_irqsrc **isrcp)
964 struct ti_gpio_softc *sc = device_get_softc(dev);
966 error = ti_gpio_pic_map(sc, data, &irq, NULL);
968 *isrcp = &sc->sc_isrcs[irq].tgi_isrc;
973 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
975 struct ti_gpio_softc *sc = device_get_softc(dev);
976 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
978 if (ti_gpio_isrc_is_level(tgi))
979 ti_gpio_isrc_eoi(sc, tgi);
983 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
986 ti_gpio_pic_enable_intr(dev, isrc);
990 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
992 struct ti_gpio_softc *sc = device_get_softc(dev);
993 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
995 ti_gpio_isrc_mask(sc, tgi);
996 if (ti_gpio_isrc_is_level(tgi))
997 ti_gpio_isrc_eoi(sc, tgi);
1001 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1002 struct resource *res, struct intr_map_data *data)
1006 struct ti_gpio_softc *sc;
1007 struct ti_gpio_irqsrc *tgi;
1012 sc = device_get_softc(dev);
1013 tgi = (struct ti_gpio_irqsrc *)isrc;
1015 /* Get and check config for an interrupt. */
1016 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq)
1020 * If this is a setup for another handler,
1021 * only check that its configuration match.
1023 if (isrc->isrc_handlers != 0)
1024 return (tgi->tgi_mode == mode ? 0 : EINVAL);
1026 ti_gpio_pic_config_intr(sc, tgi, mode);
1031 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1032 struct resource *res, struct intr_map_data *data)
1034 struct ti_gpio_softc *sc = device_get_softc(dev);
1035 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1037 if (isrc->isrc_handlers == 0)
1038 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM);
1043 ti_gpio_get_node(device_t bus, device_t dev)
1046 /* We only have one child, the GPIO bus, which needs our own node. */
1047 return (ofw_bus_get_node(bus));
1050 static device_method_t ti_gpio_methods[] = {
1051 DEVMETHOD(device_attach, ti_gpio_attach),
1052 DEVMETHOD(device_detach, ti_gpio_detach),
1055 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
1056 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
1057 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
1058 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
1059 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
1060 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
1061 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
1062 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
1063 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
1065 /* Interrupt controller interface */
1066 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr),
1067 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr),
1068 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr),
1069 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr),
1070 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr),
1071 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter),
1072 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread),
1073 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread),
1075 /* ofw_bus interface */
1076 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
1081 driver_t ti_gpio_driver = {
1084 sizeof(struct ti_gpio_softc),