2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Driver for the I2C module on the TI SoC.
31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
34 * 32 bit data access is not allowed and can corrupt register content.
36 * This driver currently doesn't use DMA for the transfer, although I hope to
37 * incorporate that sometime in the future. The idea being that for transaction
38 * larger than a certain size the DMA engine is used, for anything less the
39 * normal interrupt/fifo driven option is used.
42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions,
43 * which means you can't do a transaction during startup before the interrupts
44 * have been enabled. Hint - the freebsd function config_intrhook_establish().
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
50 #include <sys/param.h>
51 #include <sys/systm.h>
54 #include <sys/kernel.h>
57 #include <sys/malloc.h>
58 #include <sys/module.h>
59 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
62 #include <machine/bus.h>
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
68 #include <arm/ti/ti_cpuid.h>
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_i2c.h>
72 #include <dev/iicbus/iiconf.h>
73 #include <dev/iicbus/iicbus.h>
75 #include "iicbus_if.h"
78 * I2C device driver context, a pointer to this is stored in the device
85 struct resource* sc_irq_res;
86 struct resource* sc_mem_res;
93 struct iic_msg* sc_buffer;
103 struct ti_i2c_clock_config
105 u_int frequency; /* Bus frequency in Hz */
106 uint8_t psc; /* Fast/Standard mode prescale divider */
107 uint8_t scll; /* Fast/Standard mode SCL low time */
108 uint8_t sclh; /* Fast/Standard mode SCL high time */
109 uint8_t hsscll; /* High Speed mode SCL low time */
110 uint8_t hssclh; /* High Speed mode SCL high time */
113 #if defined(SOC_OMAP4)
115 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
116 * The prescaler values for 100KHz and 400KHz modes come from the table in the
117 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
119 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
120 { 100000, 23, 13, 15, 0, 0},
121 { 400000, 9, 5, 7, 0, 0},
122 { 1000000, 5, 1, 3, 0, 0},
123 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
124 { 0 /* Table terminator */ }
128 #if defined(SOC_TI_AM335X)
130 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
131 * In all cases we prescale the clock to 24MHz as recommended in the manual.
133 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
134 { 100000, 1, 111, 117, 0, 0},
135 { 400000, 1, 23, 25, 0, 0},
136 { 1000000, 1, 5, 7, 0, 0},
137 { 0 /* Table terminator */ }
142 * Locking macros used throughout the driver
144 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
145 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
146 #define TI_I2C_LOCK_INIT(_sc) \
147 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
149 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
150 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
151 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
154 #define ti_i2c_dbg(_sc, fmt, args...) \
155 device_printf((_sc)->sc_dev, fmt, ##args)
157 #define ti_i2c_dbg(_sc, fmt, args...)
161 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
162 * @sc: I2C device context
163 * @off: the byte offset within the register bank to read from.
167 * No locking required
170 * 16-bit value read from the register.
172 static inline uint16_t
173 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
176 return (bus_read_2(sc->sc_mem_res, off));
180 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
181 * @sc: I2C device context
182 * @off: the byte offset within the register bank to read from.
183 * @val: the value to write into the register
186 * No locking required
189 * 16-bit value read from the register.
192 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
195 bus_write_2(sc->sc_mem_res, off, val);
199 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
205 /* Check for the error conditions. */
206 if (status & I2C_STAT_NACK) {
207 /* No ACK from slave. */
208 ti_i2c_dbg(sc, "NACK\n");
209 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
210 sc->sc_error = ENXIO;
211 } else if (status & I2C_STAT_AL) {
212 /* Arbitration lost. */
213 ti_i2c_dbg(sc, "Arbitration lost\n");
214 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
215 sc->sc_error = ENXIO;
218 /* Check if we have finished. */
219 if (status & I2C_STAT_ARDY) {
220 /* Register access ready - transaction complete basically. */
221 ti_i2c_dbg(sc, "ARDY transaction complete\n");
222 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
223 ti_i2c_write_2(sc, I2C_REG_CON,
224 sc->sc_con_reg | I2C_CON_STP);
226 ti_i2c_write_2(sc, I2C_REG_STATUS,
227 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
228 I2C_STAT_XDR | I2C_STAT_XRDY);
232 if (sc->sc_buffer->flags & IIC_M_RD) {
233 /* Read some data. */
234 if (status & I2C_STAT_RDR) {
236 * Receive draining interrupt - last data received.
237 * The set FIFO threshold wont be reached to trigger
240 ti_i2c_dbg(sc, "Receive draining interrupt\n");
243 * Drain the FIFO. Read the pending data in the FIFO.
245 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
246 } else if (status & I2C_STAT_RRDY) {
248 * Receive data ready interrupt - FIFO has reached the
251 ti_i2c_dbg(sc, "Receive data ready interrupt\n");
253 amount = min(sc->sc_fifo_trsh,
254 sc->sc_buffer->len - sc->sc_buffer_pos);
257 /* Read the bytes from the fifo. */
258 for (i = 0; i < amount; i++)
259 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
260 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
262 if (status & I2C_STAT_RDR)
263 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
264 if (status & I2C_STAT_RRDY)
265 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
268 /* Write some data. */
269 if (status & I2C_STAT_XDR) {
271 * Transmit draining interrupt - FIFO level is below
272 * the set threshold and the amount of data still to
273 * be transferred wont reach the set FIFO threshold.
275 ti_i2c_dbg(sc, "Transmit draining interrupt\n");
278 * Drain the TX data. Write the pending data in the
281 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
282 } else if (status & I2C_STAT_XRDY) {
284 * Transmit data ready interrupt - the FIFO level
285 * is below the set threshold.
287 ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
289 amount = min(sc->sc_fifo_trsh,
290 sc->sc_buffer->len - sc->sc_buffer_pos);
293 /* Write the bytes from the fifo. */
294 for (i = 0; i < amount; i++)
295 ti_i2c_write_2(sc, I2C_REG_DATA,
296 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
298 if (status & I2C_STAT_XDR)
299 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
300 if (status & I2C_STAT_XRDY)
301 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
308 * ti_i2c_intr - interrupt handler for the I2C module
309 * @dev: i2c device handle
314 * Called from timer context
317 * EH_HANDLED or EH_NOT_HANDLED
320 ti_i2c_intr(void *arg)
323 struct ti_i2c_softc *sc;
324 uint16_t events, status;
326 sc = (struct ti_i2c_softc *)arg;
330 status = ti_i2c_read_2(sc, I2C_REG_STATUS);
336 /* Save enabled interrupts. */
337 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
339 /* We only care about enabled interrupts. */
344 if (sc->sc_buffer != NULL)
345 done = ti_i2c_transfer_intr(sc, status);
347 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
348 sc->sc_error = EINVAL;
353 /* Wakeup the process that started the transaction. */
360 * ti_i2c_transfer - called to perform the transfer
361 * @dev: i2c device handle
362 * @msgs: the messages to send/receive
363 * @nmsgs: the number of messages in the msgs array
370 * 0 on function succeeded
371 * EINVAL if invalid message is passed as an arg
374 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
376 int err, i, repstart, timeout;
377 struct ti_i2c_softc *sc;
380 sc = device_get_softc(dev);
383 /* If the controller is busy wait until it is available. */
384 while (sc->sc_bus_inuse == 1)
385 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
387 /* Now we have control over the I2C controller. */
388 sc->sc_bus_inuse = 1;
392 for (i = 0; i < nmsgs; i++) {
394 sc->sc_buffer = &msgs[i];
395 sc->sc_buffer_pos = 0;
398 /* Zero byte transfers aren't allowed. */
399 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
400 sc->sc_buffer->len == 0) {
405 /* Check if the i2c bus is free. */
408 * On repeated start we send the START condition while
412 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
413 if (timeout++ > 100) {
423 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
426 /* Set the slave address. */
427 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
429 /* Write the data length. */
430 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
432 /* Clear the RX and the TX FIFO. */
433 reg = ti_i2c_read_2(sc, I2C_REG_BUF);
434 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
435 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
437 reg = sc->sc_con_reg | I2C_CON_STT;
440 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
442 ti_i2c_write_2(sc, I2C_REG_CON, reg);
444 /* Wait for an event. */
445 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", hz);
455 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
461 /* Put the controller in master mode again. */
462 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
463 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
465 sc->sc_buffer = NULL;
466 sc->sc_bus_inuse = 0;
468 /* Wake up the processes that are waiting for the bus. */
477 * ti_i2c_callback - as we only provide iicbus_transfer() interface
478 * we don't need to implement the serialization here.
479 * @dev: i2c device handle
484 * Called from timer context
487 * EH_HANDLED or EH_NOT_HANDLED
490 ti_i2c_callback(device_t dev, int index, caddr_t data)
495 case IIC_REQUEST_BUS:
498 case IIC_RELEASE_BUS:
509 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
512 struct ti_i2c_clock_config *clkcfg;
514 uint16_t fifo_trsh, reg, scll, sclh;
519 clkcfg = ti_omap4_i2c_clock_configs;
524 clkcfg = ti_am335x_i2c_clock_configs;
528 panic("Unknown Ti SoC, unable to reset the i2c");
532 * If we haven't attached the bus yet, just init at the default slow
533 * speed. This lets us get the hardware initialized enough to attach
534 * the bus which is where the real speed configuration is handled. After
535 * the bus is attached, get the configured speed from it. Search the
536 * configuration table for the best speed we can do that doesn't exceed
537 * the requested speed.
539 if (sc->sc_iicbus == NULL)
542 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
544 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
550 * 23.1.4.3 - HS I2C Software Reset
551 * From OMAP4 TRM at page 4068.
553 * 1. Ensure that the module is disabled.
556 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
558 /* 2. Issue a softreset to the controller. */
559 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
562 * 3. Enable the module.
563 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
564 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
566 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
568 /* 4. Wait for the software reset to complete. */
570 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
577 * Disable the I2C controller once again, now that the reset has
580 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
583 * The following sequence is taken from the OMAP4 TRM at page 4077.
585 * 1. Enable the functional and interface clocks (see Section
586 * 23.1.5.1.1.1.1). Done at ti_i2c_activate().
588 * 2. Program the prescaler to obtain an approximately 12MHz internal
589 * sampling clock (I2Ci_INTERNAL_CLK) by programming the
590 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
591 * This value depends on the frequency of the functional clock
592 * (I2Ci_FCLK). Because this frequency is 96MHz, the
593 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
595 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
598 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
599 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
600 * These values depend on the internal sampling clock frequency
603 scll = clkcfg->scll & I2C_SCLL_MASK;
604 sclh = clkcfg->sclh & I2C_SCLH_MASK;
607 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
608 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
609 * 400K bps or 3.4M bps (for the second phase of HS mode). These
610 * values depend on the internal sampling clock frequency (see
613 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
614 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
615 * Multiplexing and Configuration).
620 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
621 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
622 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
623 sc->sc_con_reg |= I2C_CON_OPMODE_HS;
629 /* Write the selected bit rate. */
630 ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
631 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
634 * 6. Configure the Own Address of the I2C controller by storing it in
635 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
636 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
637 * for each I2C controller.
639 * Note: For a 10-bit address, set the corresponding expand Own Address
640 * bit in the I2Ci.I2C_CON register.
642 * Driver currently always in single master mode so ignore this step.
646 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
647 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
648 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
649 * threshold - 1), where the TX and RX thresholds are greater than
652 * The threshold is set to 5 for now.
654 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
655 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
656 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
659 * 8. Take the I2C controller out of reset by setting the
660 * I2Ci.I2C_CON[15] I2C_EN bit to 1.
662 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
664 * To initialize the I2C controller, perform the following steps:
666 * 1. Configure the I2Ci.I2C_CON register:
667 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
668 * (0: slave, 1: master).
669 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
670 * bit (0: receiver, 1: transmitter).
673 /* Enable the I2C controller in master mode. */
674 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
675 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
678 * 2. If using an interrupt to transmit/receive data, set the
679 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
680 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
681 * bit for the receive interrupt).
684 /* Set the interrupts we want to be notified. */
685 reg = I2C_IE_XDR | /* Transmit draining interrupt. */
686 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
687 I2C_IE_RDR | /* Receive draining interrupt. */
688 I2C_IE_RRDY | /* Receive Data Ready interrupt. */
689 I2C_IE_ARDY | /* Register Access Ready interrupt. */
690 I2C_IE_NACK | /* No Acknowledgment interrupt. */
691 I2C_IE_AL; /* Arbitration lost interrupt. */
693 /* Enable the interrupts. */
694 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
697 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
698 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
699 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
700 * for the transmit DMA channel).
702 * Not using DMA for now, so ignore this.
709 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
711 struct ti_i2c_softc *sc;
714 sc = device_get_softc(dev);
716 err = ti_i2c_reset(sc, speed);
721 return (IIC_ENOADDR);
725 ti_i2c_activate(device_t dev)
729 struct ti_i2c_softc *sc;
731 sc = (struct ti_i2c_softc*)device_get_softc(dev);
734 * 1. Enable the functional and interface clocks (see Section
737 clk = I2C0_CLK + sc->device_id;
738 err = ti_prcm_clk_enable(clk);
742 return (ti_i2c_reset(sc, IIC_UNKNOWN));
746 * ti_i2c_deactivate - deactivates the controller and releases resources
747 * @dev: i2c device handle
752 * Assumed called in an atomic context.
758 ti_i2c_deactivate(device_t dev)
760 struct ti_i2c_softc *sc = device_get_softc(dev);
763 /* Disable the controller - cancel all transactions. */
764 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
765 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
766 ti_i2c_write_2(sc, I2C_REG_CON, 0);
768 /* Release the interrupt handler. */
769 if (sc->sc_irq_h != NULL) {
770 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
774 bus_generic_detach(sc->sc_dev);
776 /* Unmap the I2C controller registers. */
777 if (sc->sc_mem_res != NULL) {
778 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
779 sc->sc_mem_res = NULL;
782 /* Release the IRQ resource. */
783 if (sc->sc_irq_res != NULL) {
784 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
785 sc->sc_irq_res = NULL;
788 /* Finally disable the functional and interface clocks. */
789 clk = I2C0_CLK + sc->device_id;
790 ti_prcm_clk_disable(clk);
794 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
797 int clk, psc, sclh, scll;
798 struct ti_i2c_softc *sc;
800 dev = (device_t)arg1;
801 sc = device_get_softc(dev);
804 /* Get the system prescaler value. */
805 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
807 /* Get the bitrate. */
808 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
809 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
811 clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
814 return (sysctl_handle_int(oidp, &clk, 0, req));
818 ti_i2c_probe(device_t dev)
821 if (!ofw_bus_status_okay(dev))
823 if (!ofw_bus_is_compatible(dev, "ti,i2c"))
825 device_set_desc(dev, "TI I2C Controller");
831 ti_i2c_attach(device_t dev)
835 struct ti_i2c_softc *sc;
836 struct sysctl_ctx_list *ctx;
837 struct sysctl_oid_list *tree;
840 sc = device_get_softc(dev);
843 /* Get the i2c device id from FDT. */
844 node = ofw_bus_get_node(dev);
845 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id,
846 sizeof(sc->device_id))) <= 0) {
847 device_printf(dev, "missing i2c-device-id attribute in FDT\n");
851 /* Get the memory resource for the register mapping. */
853 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
855 if (sc->sc_mem_res == NULL) {
856 device_printf(dev, "Cannot map registers.\n");
860 /* Allocate our IRQ resource. */
862 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
863 RF_ACTIVE | RF_SHAREABLE);
864 if (sc->sc_irq_res == NULL) {
865 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
866 device_printf(dev, "Cannot allocate interrupt.\n");
870 TI_I2C_LOCK_INIT(sc);
872 /* First of all, we _must_ activate the H/W. */
873 err = ti_i2c_activate(dev);
875 device_printf(dev, "ti_i2c_activate failed\n");
879 /* Read the version number of the I2C module */
880 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
882 /* Get the fifo size. */
883 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
884 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
885 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
887 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
888 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
890 /* Set the FIFO threshold to 5 for now. */
891 sc->sc_fifo_trsh = 5;
893 ctx = device_get_sysctl_ctx(dev);
894 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
895 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
896 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, dev, 0,
897 ti_i2c_sysctl_clk, "IU", "I2C bus clock");
899 /* Activate the interrupt. */
900 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
901 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
905 /* Attach the iicbus. */
906 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
907 device_printf(dev, "could not allocate iicbus instance\n");
912 /* Probe and attach the iicbus */
913 bus_generic_attach(dev);
917 ti_i2c_deactivate(dev);
918 TI_I2C_LOCK_DESTROY(sc);
925 ti_i2c_detach(device_t dev)
927 struct ti_i2c_softc *sc;
930 sc = device_get_softc(dev);
931 ti_i2c_deactivate(dev);
932 TI_I2C_LOCK_DESTROY(sc);
934 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
941 ti_i2c_get_node(device_t bus, device_t dev)
944 /* Share controller node with iibus device. */
945 return (ofw_bus_get_node(bus));
948 static device_method_t ti_i2c_methods[] = {
949 /* Device interface */
950 DEVMETHOD(device_probe, ti_i2c_probe),
951 DEVMETHOD(device_attach, ti_i2c_attach),
952 DEVMETHOD(device_detach, ti_i2c_detach),
955 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
957 /* iicbus interface */
958 DEVMETHOD(iicbus_callback, ti_i2c_callback),
959 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
960 DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
965 static driver_t ti_i2c_driver = {
968 sizeof(struct ti_i2c_softc),
971 static devclass_t ti_i2c_devclass;
973 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0);
974 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0);
976 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1);
977 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);