2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Driver for the I2C module on the TI SoC.
31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
34 * 32 bit data access is not allowed and can corrupt register content.
36 * This driver currently doesn't use DMA for the transfer, although I hope to
37 * incorporate that sometime in the future. The idea being that for transaction
38 * larger than a certain size the DMA engine is used, for anything less the
39 * normal interrupt/fifo driven option is used.
42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions,
43 * which means you can't do a transaction during startup before the interrupts
44 * have been enabled. Hint - the freebsd function config_intrhook_establish().
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
50 #include <sys/param.h>
51 #include <sys/systm.h>
54 #include <sys/kernel.h>
57 #include <sys/malloc.h>
58 #include <sys/module.h>
59 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
62 #include <machine/bus.h>
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
68 #include <arm/ti/ti_cpuid.h>
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_hwmods.h>
71 #include <arm/ti/ti_i2c.h>
73 #include <dev/iicbus/iiconf.h>
74 #include <dev/iicbus/iicbus.h>
76 #include "iicbus_if.h"
79 * I2C device driver context, a pointer to this is stored in the device
86 struct resource* sc_irq_res;
87 struct resource* sc_mem_res;
94 struct iic_msg* sc_buffer;
105 struct ti_i2c_clock_config
107 u_int frequency; /* Bus frequency in Hz */
108 uint8_t psc; /* Fast/Standard mode prescale divider */
109 uint8_t scll; /* Fast/Standard mode SCL low time */
110 uint8_t sclh; /* Fast/Standard mode SCL high time */
111 uint8_t hsscll; /* High Speed mode SCL low time */
112 uint8_t hssclh; /* High Speed mode SCL high time */
115 #if defined(SOC_OMAP4)
117 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
118 * The prescaler values for 100KHz and 400KHz modes come from the table in the
119 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
121 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
122 { 100000, 23, 13, 15, 0, 0},
123 { 400000, 9, 5, 7, 0, 0},
124 { 1000000, 3, 5, 7, 0, 0},
125 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
126 { 0 /* Table terminator */ }
130 #if defined(SOC_TI_AM335X)
132 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
133 * In all cases we prescale the clock to 24MHz as recommended in the manual.
135 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
136 { 100000, 1, 111, 117, 0, 0},
137 { 400000, 1, 23, 25, 0, 0},
138 { 1000000, 1, 5, 7, 0, 0},
139 { 0 /* Table terminator */ }
144 * Locking macros used throughout the driver
146 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
147 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
148 #define TI_I2C_LOCK_INIT(_sc) \
149 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
151 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
152 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
153 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
156 #define ti_i2c_dbg(_sc, fmt, args...) \
157 device_printf((_sc)->sc_dev, fmt, ##args)
159 #define ti_i2c_dbg(_sc, fmt, args...)
163 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
164 * @sc: I2C device context
165 * @off: the byte offset within the register bank to read from.
169 * No locking required
172 * 16-bit value read from the register.
174 static inline uint16_t
175 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
178 return (bus_read_2(sc->sc_mem_res, off));
182 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
183 * @sc: I2C device context
184 * @off: the byte offset within the register bank to read from.
185 * @val: the value to write into the register
188 * No locking required
191 * 16-bit value read from the register.
194 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
197 bus_write_2(sc->sc_mem_res, off, val);
201 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
207 /* Check for the error conditions. */
208 if (status & I2C_STAT_NACK) {
209 /* No ACK from slave. */
210 ti_i2c_dbg(sc, "NACK\n");
211 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
212 sc->sc_error = ENXIO;
213 } else if (status & I2C_STAT_AL) {
214 /* Arbitration lost. */
215 ti_i2c_dbg(sc, "Arbitration lost\n");
216 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
217 sc->sc_error = ENXIO;
220 /* Check if we have finished. */
221 if (status & I2C_STAT_ARDY) {
222 /* Register access ready - transaction complete basically. */
223 ti_i2c_dbg(sc, "ARDY transaction complete\n");
224 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
225 ti_i2c_write_2(sc, I2C_REG_CON,
226 sc->sc_con_reg | I2C_CON_STP);
228 ti_i2c_write_2(sc, I2C_REG_STATUS,
229 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
230 I2C_STAT_XDR | I2C_STAT_XRDY);
234 if (sc->sc_buffer->flags & IIC_M_RD) {
235 /* Read some data. */
236 if (status & I2C_STAT_RDR) {
238 * Receive draining interrupt - last data received.
239 * The set FIFO threshold wont be reached to trigger
242 ti_i2c_dbg(sc, "Receive draining interrupt\n");
245 * Drain the FIFO. Read the pending data in the FIFO.
247 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
248 } else if (status & I2C_STAT_RRDY) {
250 * Receive data ready interrupt - FIFO has reached the
253 ti_i2c_dbg(sc, "Receive data ready interrupt\n");
255 amount = min(sc->sc_fifo_trsh,
256 sc->sc_buffer->len - sc->sc_buffer_pos);
259 /* Read the bytes from the fifo. */
260 for (i = 0; i < amount; i++)
261 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
262 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
264 if (status & I2C_STAT_RDR)
265 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
266 if (status & I2C_STAT_RRDY)
267 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
270 /* Write some data. */
271 if (status & I2C_STAT_XDR) {
273 * Transmit draining interrupt - FIFO level is below
274 * the set threshold and the amount of data still to
275 * be transferred wont reach the set FIFO threshold.
277 ti_i2c_dbg(sc, "Transmit draining interrupt\n");
280 * Drain the TX data. Write the pending data in the
283 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
284 } else if (status & I2C_STAT_XRDY) {
286 * Transmit data ready interrupt - the FIFO level
287 * is below the set threshold.
289 ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
291 amount = min(sc->sc_fifo_trsh,
292 sc->sc_buffer->len - sc->sc_buffer_pos);
295 /* Write the bytes from the fifo. */
296 for (i = 0; i < amount; i++)
297 ti_i2c_write_2(sc, I2C_REG_DATA,
298 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
300 if (status & I2C_STAT_XDR)
301 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
302 if (status & I2C_STAT_XRDY)
303 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
310 * ti_i2c_intr - interrupt handler for the I2C module
311 * @dev: i2c device handle
316 * Called from timer context
319 * EH_HANDLED or EH_NOT_HANDLED
322 ti_i2c_intr(void *arg)
325 struct ti_i2c_softc *sc;
326 uint16_t events, status;
328 sc = (struct ti_i2c_softc *)arg;
332 status = ti_i2c_read_2(sc, I2C_REG_STATUS);
338 /* Save enabled interrupts. */
339 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
341 /* We only care about enabled interrupts. */
346 if (sc->sc_buffer != NULL)
347 done = ti_i2c_transfer_intr(sc, status);
349 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
350 sc->sc_error = EINVAL;
355 /* Wakeup the process that started the transaction. */
362 * ti_i2c_transfer - called to perform the transfer
363 * @dev: i2c device handle
364 * @msgs: the messages to send/receive
365 * @nmsgs: the number of messages in the msgs array
372 * 0 on function succeeded
373 * EINVAL if invalid message is passed as an arg
376 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
378 int err, i, repstart, timeout;
379 struct ti_i2c_softc *sc;
382 sc = device_get_softc(dev);
385 /* If the controller is busy wait until it is available. */
386 while (sc->sc_bus_inuse == 1)
387 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
389 /* Now we have control over the I2C controller. */
390 sc->sc_bus_inuse = 1;
394 for (i = 0; i < nmsgs; i++) {
396 sc->sc_buffer = &msgs[i];
397 sc->sc_buffer_pos = 0;
400 /* Zero byte transfers aren't allowed. */
401 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
402 sc->sc_buffer->len == 0) {
407 /* Check if the i2c bus is free. */
410 * On repeated start we send the START condition while
414 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
415 if (timeout++ > 100) {
425 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
428 /* Set the slave address. */
429 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
431 /* Write the data length. */
432 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
434 /* Clear the RX and the TX FIFO. */
435 reg = ti_i2c_read_2(sc, I2C_REG_BUF);
436 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
437 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
439 reg = sc->sc_con_reg | I2C_CON_STT;
442 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
444 ti_i2c_write_2(sc, I2C_REG_CON, reg);
446 /* Wait for an event. */
447 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
457 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
463 /* Put the controller in master mode again. */
464 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
465 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
467 sc->sc_buffer = NULL;
468 sc->sc_bus_inuse = 0;
470 /* Wake up the processes that are waiting for the bus. */
479 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
482 struct ti_i2c_clock_config *clkcfg;
484 uint16_t fifo_trsh, reg, scll, sclh;
489 clkcfg = ti_omap4_i2c_clock_configs;
494 clkcfg = ti_am335x_i2c_clock_configs;
498 panic("Unknown Ti SoC, unable to reset the i2c");
502 * If we haven't attached the bus yet, just init at the default slow
503 * speed. This lets us get the hardware initialized enough to attach
504 * the bus which is where the real speed configuration is handled. After
505 * the bus is attached, get the configured speed from it. Search the
506 * configuration table for the best speed we can do that doesn't exceed
507 * the requested speed.
509 if (sc->sc_iicbus == NULL)
512 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
514 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
520 * 23.1.4.3 - HS I2C Software Reset
521 * From OMAP4 TRM at page 4068.
523 * 1. Ensure that the module is disabled.
526 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
528 /* 2. Issue a softreset to the controller. */
529 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
532 * 3. Enable the module.
533 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
534 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
536 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
538 /* 4. Wait for the software reset to complete. */
540 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
547 * Disable the I2C controller once again, now that the reset has
550 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
553 * The following sequence is taken from the OMAP4 TRM at page 4077.
555 * 1. Enable the functional and interface clocks (see Section
556 * 23.1.5.1.1.1.1). Done at ti_i2c_activate().
558 * 2. Program the prescaler to obtain an approximately 12MHz internal
559 * sampling clock (I2Ci_INTERNAL_CLK) by programming the
560 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
561 * This value depends on the frequency of the functional clock
562 * (I2Ci_FCLK). Because this frequency is 96MHz, the
563 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
565 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
568 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
569 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
570 * These values depend on the internal sampling clock frequency
573 scll = clkcfg->scll & I2C_SCLL_MASK;
574 sclh = clkcfg->sclh & I2C_SCLH_MASK;
577 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
578 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
579 * 400K bps or 3.4M bps (for the second phase of HS mode). These
580 * values depend on the internal sampling clock frequency (see
583 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
584 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
585 * Multiplexing and Configuration).
590 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
591 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
592 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
593 sc->sc_con_reg |= I2C_CON_OPMODE_HS;
599 /* Write the selected bit rate. */
600 ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
601 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
604 * 6. Configure the Own Address of the I2C controller by storing it in
605 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
606 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
607 * for each I2C controller.
609 * Note: For a 10-bit address, set the corresponding expand Own Address
610 * bit in the I2Ci.I2C_CON register.
612 * Driver currently always in single master mode so ignore this step.
616 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
617 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
618 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
619 * threshold - 1), where the TX and RX thresholds are greater than
622 * The threshold is set to 5 for now.
624 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
625 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
626 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
629 * 8. Take the I2C controller out of reset by setting the
630 * I2Ci.I2C_CON[15] I2C_EN bit to 1.
632 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
634 * To initialize the I2C controller, perform the following steps:
636 * 1. Configure the I2Ci.I2C_CON register:
637 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
638 * (0: slave, 1: master).
639 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
640 * bit (0: receiver, 1: transmitter).
643 /* Enable the I2C controller in master mode. */
644 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
645 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
648 * 2. If using an interrupt to transmit/receive data, set the
649 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
650 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
651 * bit for the receive interrupt).
654 /* Set the interrupts we want to be notified. */
655 reg = I2C_IE_XDR | /* Transmit draining interrupt. */
656 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
657 I2C_IE_RDR | /* Receive draining interrupt. */
658 I2C_IE_RRDY | /* Receive Data Ready interrupt. */
659 I2C_IE_ARDY | /* Register Access Ready interrupt. */
660 I2C_IE_NACK | /* No Acknowledgment interrupt. */
661 I2C_IE_AL; /* Arbitration lost interrupt. */
663 /* Enable the interrupts. */
664 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
667 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
668 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
669 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
670 * for the transmit DMA channel).
672 * Not using DMA for now, so ignore this.
679 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
681 struct ti_i2c_softc *sc;
684 sc = device_get_softc(dev);
686 err = ti_i2c_reset(sc, speed);
691 return (IIC_ENOADDR);
695 ti_i2c_activate(device_t dev)
698 struct ti_i2c_softc *sc;
700 sc = (struct ti_i2c_softc*)device_get_softc(dev);
703 * 1. Enable the functional and interface clocks (see Section
706 err = ti_prcm_clk_enable(sc->clk_id);
710 return (ti_i2c_reset(sc, IIC_UNKNOWN));
714 * ti_i2c_deactivate - deactivates the controller and releases resources
715 * @dev: i2c device handle
720 * Assumed called in an atomic context.
726 ti_i2c_deactivate(device_t dev)
728 struct ti_i2c_softc *sc = device_get_softc(dev);
730 /* Disable the controller - cancel all transactions. */
731 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
732 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
733 ti_i2c_write_2(sc, I2C_REG_CON, 0);
735 /* Release the interrupt handler. */
736 if (sc->sc_irq_h != NULL) {
737 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
741 bus_generic_detach(sc->sc_dev);
743 /* Unmap the I2C controller registers. */
744 if (sc->sc_mem_res != NULL) {
745 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
746 sc->sc_mem_res = NULL;
749 /* Release the IRQ resource. */
750 if (sc->sc_irq_res != NULL) {
751 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
752 sc->sc_irq_res = NULL;
755 /* Finally disable the functional and interface clocks. */
756 ti_prcm_clk_disable(sc->clk_id);
760 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
762 int clk, psc, sclh, scll;
763 struct ti_i2c_softc *sc;
768 /* Get the system prescaler value. */
769 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
771 /* Get the bitrate. */
772 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
773 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
775 clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
778 return (sysctl_handle_int(oidp, &clk, 0, req));
782 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)
784 struct ti_i2c_softc *sc;
791 * MTX_DEF lock can't be held while doing uimove in
795 val = sc->sc_timeout;
798 err = sysctl_handle_int(oidp, &val, 0, req);
800 if ((err == 0) && (req->newptr != NULL)) {
802 sc->sc_timeout = val;
810 ti_i2c_probe(device_t dev)
813 if (!ofw_bus_status_okay(dev))
815 if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))
817 device_set_desc(dev, "TI I2C Controller");
823 ti_i2c_attach(device_t dev)
827 struct ti_i2c_softc *sc;
828 struct sysctl_ctx_list *ctx;
829 struct sysctl_oid_list *tree;
832 sc = device_get_softc(dev);
835 /* Get the i2c device id from FDT. */
836 node = ofw_bus_get_node(dev);
837 /* i2c ti,hwmods bindings is special: it start with index 1 */
838 sc->clk_id = ti_hwmods_get_clock(dev);
839 if (sc->clk_id == INVALID_CLK_IDENT) {
840 device_printf(dev, "failed to get device id using ti,hwmod\n");
844 /* Get the memory resource for the register mapping. */
846 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
848 if (sc->sc_mem_res == NULL) {
849 device_printf(dev, "Cannot map registers.\n");
853 /* Allocate our IRQ resource. */
855 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
856 RF_ACTIVE | RF_SHAREABLE);
857 if (sc->sc_irq_res == NULL) {
858 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
859 device_printf(dev, "Cannot allocate interrupt.\n");
863 TI_I2C_LOCK_INIT(sc);
865 /* First of all, we _must_ activate the H/W. */
866 err = ti_i2c_activate(dev);
868 device_printf(dev, "ti_i2c_activate failed\n");
872 /* Read the version number of the I2C module */
873 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
875 /* Get the fifo size. */
876 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
877 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
878 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
880 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
881 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
883 /* Set the FIFO threshold to 5 for now. */
884 sc->sc_fifo_trsh = 5;
886 /* Set I2C bus timeout */
887 sc->sc_timeout = 5*hz;
889 ctx = device_get_sysctl_ctx(dev);
890 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
891 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
892 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
893 ti_i2c_sysctl_clk, "IU", "I2C bus clock");
895 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout",
896 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
897 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)");
899 /* Activate the interrupt. */
900 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
901 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
905 /* Attach the iicbus. */
906 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
907 device_printf(dev, "could not allocate iicbus instance\n");
912 /* Probe and attach the iicbus */
913 bus_generic_attach(dev);
917 ti_i2c_deactivate(dev);
918 TI_I2C_LOCK_DESTROY(sc);
925 ti_i2c_detach(device_t dev)
927 struct ti_i2c_softc *sc;
930 sc = device_get_softc(dev);
931 ti_i2c_deactivate(dev);
932 TI_I2C_LOCK_DESTROY(sc);
934 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
941 ti_i2c_get_node(device_t bus, device_t dev)
944 /* Share controller node with iibus device. */
945 return (ofw_bus_get_node(bus));
948 static device_method_t ti_i2c_methods[] = {
949 /* Device interface */
950 DEVMETHOD(device_probe, ti_i2c_probe),
951 DEVMETHOD(device_attach, ti_i2c_attach),
952 DEVMETHOD(device_detach, ti_i2c_detach),
955 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
956 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
957 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
958 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
959 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
960 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
961 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
962 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
963 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
966 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
968 /* iicbus interface */
969 DEVMETHOD(iicbus_callback, iicbus_null_callback),
970 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
971 DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
976 static driver_t ti_i2c_driver = {
979 sizeof(struct ti_i2c_softc),
982 static devclass_t ti_i2c_devclass;
984 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0);
985 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0);
987 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1);
988 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);