2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Driver for the I2C module on the TI SoC.
31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
34 * 32 bit data access is not allowed and can corrupt register content.
36 * This driver currently doesn't use DMA for the transfer, although I hope to
37 * incorporate that sometime in the future. The idea being that for transaction
38 * larger than a certain size the DMA engine is used, for anything less the
39 * normal interrupt/fifo driven option is used.
42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions,
43 * which means you can't do a transaction during startup before the interrupts
44 * have been enabled. Hint - the freebsd function config_intrhook_establish().
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
50 #include <sys/param.h>
51 #include <sys/systm.h>
54 #include <sys/kernel.h>
57 #include <sys/malloc.h>
58 #include <sys/module.h>
59 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
62 #include <machine/bus.h>
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
68 #include <arm/ti/ti_cpuid.h>
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_i2c.h>
72 #include <dev/iicbus/iiconf.h>
73 #include <dev/iicbus/iicbus.h>
75 #include "iicbus_if.h"
78 * I2C device driver context, a pointer to this is stored in the device
85 struct resource* sc_irq_res;
86 struct resource* sc_mem_res;
93 struct iic_msg* sc_buffer;
104 struct ti_i2c_clock_config
106 u_int frequency; /* Bus frequency in Hz */
107 uint8_t psc; /* Fast/Standard mode prescale divider */
108 uint8_t scll; /* Fast/Standard mode SCL low time */
109 uint8_t sclh; /* Fast/Standard mode SCL high time */
110 uint8_t hsscll; /* High Speed mode SCL low time */
111 uint8_t hssclh; /* High Speed mode SCL high time */
114 #if defined(SOC_OMAP4)
116 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
117 * The prescaler values for 100KHz and 400KHz modes come from the table in the
118 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
120 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
121 { 100000, 23, 13, 15, 0, 0},
122 { 400000, 9, 5, 7, 0, 0},
123 { 1000000, 3, 5, 7, 0, 0},
124 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
125 { 0 /* Table terminator */ }
129 #if defined(SOC_TI_AM335X)
131 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
132 * In all cases we prescale the clock to 24MHz as recommended in the manual.
134 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
135 { 100000, 1, 111, 117, 0, 0},
136 { 400000, 1, 23, 25, 0, 0},
137 { 1000000, 1, 5, 7, 0, 0},
138 { 0 /* Table terminator */ }
143 * Locking macros used throughout the driver
145 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
146 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
147 #define TI_I2C_LOCK_INIT(_sc) \
148 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
150 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
151 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
152 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
155 #define ti_i2c_dbg(_sc, fmt, args...) \
156 device_printf((_sc)->sc_dev, fmt, ##args)
158 #define ti_i2c_dbg(_sc, fmt, args...)
162 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
163 * @sc: I2C device context
164 * @off: the byte offset within the register bank to read from.
168 * No locking required
171 * 16-bit value read from the register.
173 static inline uint16_t
174 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
177 return (bus_read_2(sc->sc_mem_res, off));
181 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
182 * @sc: I2C device context
183 * @off: the byte offset within the register bank to read from.
184 * @val: the value to write into the register
187 * No locking required
190 * 16-bit value read from the register.
193 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
196 bus_write_2(sc->sc_mem_res, off, val);
200 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
206 /* Check for the error conditions. */
207 if (status & I2C_STAT_NACK) {
208 /* No ACK from slave. */
209 ti_i2c_dbg(sc, "NACK\n");
210 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
211 sc->sc_error = ENXIO;
212 } else if (status & I2C_STAT_AL) {
213 /* Arbitration lost. */
214 ti_i2c_dbg(sc, "Arbitration lost\n");
215 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
216 sc->sc_error = ENXIO;
219 /* Check if we have finished. */
220 if (status & I2C_STAT_ARDY) {
221 /* Register access ready - transaction complete basically. */
222 ti_i2c_dbg(sc, "ARDY transaction complete\n");
223 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
224 ti_i2c_write_2(sc, I2C_REG_CON,
225 sc->sc_con_reg | I2C_CON_STP);
227 ti_i2c_write_2(sc, I2C_REG_STATUS,
228 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
229 I2C_STAT_XDR | I2C_STAT_XRDY);
233 if (sc->sc_buffer->flags & IIC_M_RD) {
234 /* Read some data. */
235 if (status & I2C_STAT_RDR) {
237 * Receive draining interrupt - last data received.
238 * The set FIFO threshold wont be reached to trigger
241 ti_i2c_dbg(sc, "Receive draining interrupt\n");
244 * Drain the FIFO. Read the pending data in the FIFO.
246 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
247 } else if (status & I2C_STAT_RRDY) {
249 * Receive data ready interrupt - FIFO has reached the
252 ti_i2c_dbg(sc, "Receive data ready interrupt\n");
254 amount = min(sc->sc_fifo_trsh,
255 sc->sc_buffer->len - sc->sc_buffer_pos);
258 /* Read the bytes from the fifo. */
259 for (i = 0; i < amount; i++)
260 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
261 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
263 if (status & I2C_STAT_RDR)
264 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
265 if (status & I2C_STAT_RRDY)
266 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
269 /* Write some data. */
270 if (status & I2C_STAT_XDR) {
272 * Transmit draining interrupt - FIFO level is below
273 * the set threshold and the amount of data still to
274 * be transferred wont reach the set FIFO threshold.
276 ti_i2c_dbg(sc, "Transmit draining interrupt\n");
279 * Drain the TX data. Write the pending data in the
282 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
283 } else if (status & I2C_STAT_XRDY) {
285 * Transmit data ready interrupt - the FIFO level
286 * is below the set threshold.
288 ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
290 amount = min(sc->sc_fifo_trsh,
291 sc->sc_buffer->len - sc->sc_buffer_pos);
294 /* Write the bytes from the fifo. */
295 for (i = 0; i < amount; i++)
296 ti_i2c_write_2(sc, I2C_REG_DATA,
297 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
299 if (status & I2C_STAT_XDR)
300 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
301 if (status & I2C_STAT_XRDY)
302 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
309 * ti_i2c_intr - interrupt handler for the I2C module
310 * @dev: i2c device handle
315 * Called from timer context
318 * EH_HANDLED or EH_NOT_HANDLED
321 ti_i2c_intr(void *arg)
324 struct ti_i2c_softc *sc;
325 uint16_t events, status;
327 sc = (struct ti_i2c_softc *)arg;
331 status = ti_i2c_read_2(sc, I2C_REG_STATUS);
337 /* Save enabled interrupts. */
338 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
340 /* We only care about enabled interrupts. */
345 if (sc->sc_buffer != NULL)
346 done = ti_i2c_transfer_intr(sc, status);
348 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
349 sc->sc_error = EINVAL;
354 /* Wakeup the process that started the transaction. */
361 * ti_i2c_transfer - called to perform the transfer
362 * @dev: i2c device handle
363 * @msgs: the messages to send/receive
364 * @nmsgs: the number of messages in the msgs array
371 * 0 on function succeeded
372 * EINVAL if invalid message is passed as an arg
375 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
377 int err, i, repstart, timeout;
378 struct ti_i2c_softc *sc;
381 sc = device_get_softc(dev);
384 /* If the controller is busy wait until it is available. */
385 while (sc->sc_bus_inuse == 1)
386 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
388 /* Now we have control over the I2C controller. */
389 sc->sc_bus_inuse = 1;
393 for (i = 0; i < nmsgs; i++) {
395 sc->sc_buffer = &msgs[i];
396 sc->sc_buffer_pos = 0;
399 /* Zero byte transfers aren't allowed. */
400 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
401 sc->sc_buffer->len == 0) {
406 /* Check if the i2c bus is free. */
409 * On repeated start we send the START condition while
413 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
414 if (timeout++ > 100) {
424 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
427 /* Set the slave address. */
428 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
430 /* Write the data length. */
431 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
433 /* Clear the RX and the TX FIFO. */
434 reg = ti_i2c_read_2(sc, I2C_REG_BUF);
435 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
436 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
438 reg = sc->sc_con_reg | I2C_CON_STT;
441 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
443 ti_i2c_write_2(sc, I2C_REG_CON, reg);
445 /* Wait for an event. */
446 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
456 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
462 /* Put the controller in master mode again. */
463 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
464 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
466 sc->sc_buffer = NULL;
467 sc->sc_bus_inuse = 0;
469 /* Wake up the processes that are waiting for the bus. */
478 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
481 struct ti_i2c_clock_config *clkcfg;
483 uint16_t fifo_trsh, reg, scll, sclh;
488 clkcfg = ti_omap4_i2c_clock_configs;
493 clkcfg = ti_am335x_i2c_clock_configs;
497 panic("Unknown Ti SoC, unable to reset the i2c");
501 * If we haven't attached the bus yet, just init at the default slow
502 * speed. This lets us get the hardware initialized enough to attach
503 * the bus which is where the real speed configuration is handled. After
504 * the bus is attached, get the configured speed from it. Search the
505 * configuration table for the best speed we can do that doesn't exceed
506 * the requested speed.
508 if (sc->sc_iicbus == NULL)
511 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
513 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
519 * 23.1.4.3 - HS I2C Software Reset
520 * From OMAP4 TRM at page 4068.
522 * 1. Ensure that the module is disabled.
525 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
527 /* 2. Issue a softreset to the controller. */
528 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
531 * 3. Enable the module.
532 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
533 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
535 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
537 /* 4. Wait for the software reset to complete. */
539 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
546 * Disable the I2C controller once again, now that the reset has
549 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
552 * The following sequence is taken from the OMAP4 TRM at page 4077.
554 * 1. Enable the functional and interface clocks (see Section
555 * 23.1.5.1.1.1.1). Done at ti_i2c_activate().
557 * 2. Program the prescaler to obtain an approximately 12MHz internal
558 * sampling clock (I2Ci_INTERNAL_CLK) by programming the
559 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
560 * This value depends on the frequency of the functional clock
561 * (I2Ci_FCLK). Because this frequency is 96MHz, the
562 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
564 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
567 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
568 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
569 * These values depend on the internal sampling clock frequency
572 scll = clkcfg->scll & I2C_SCLL_MASK;
573 sclh = clkcfg->sclh & I2C_SCLH_MASK;
576 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
577 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
578 * 400K bps or 3.4M bps (for the second phase of HS mode). These
579 * values depend on the internal sampling clock frequency (see
582 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
583 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
584 * Multiplexing and Configuration).
589 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
590 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
591 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
592 sc->sc_con_reg |= I2C_CON_OPMODE_HS;
598 /* Write the selected bit rate. */
599 ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
600 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
603 * 6. Configure the Own Address of the I2C controller by storing it in
604 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
605 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
606 * for each I2C controller.
608 * Note: For a 10-bit address, set the corresponding expand Own Address
609 * bit in the I2Ci.I2C_CON register.
611 * Driver currently always in single master mode so ignore this step.
615 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
616 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
617 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
618 * threshold - 1), where the TX and RX thresholds are greater than
621 * The threshold is set to 5 for now.
623 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
624 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
625 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
628 * 8. Take the I2C controller out of reset by setting the
629 * I2Ci.I2C_CON[15] I2C_EN bit to 1.
631 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
633 * To initialize the I2C controller, perform the following steps:
635 * 1. Configure the I2Ci.I2C_CON register:
636 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
637 * (0: slave, 1: master).
638 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
639 * bit (0: receiver, 1: transmitter).
642 /* Enable the I2C controller in master mode. */
643 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
644 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
647 * 2. If using an interrupt to transmit/receive data, set the
648 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
649 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
650 * bit for the receive interrupt).
653 /* Set the interrupts we want to be notified. */
654 reg = I2C_IE_XDR | /* Transmit draining interrupt. */
655 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
656 I2C_IE_RDR | /* Receive draining interrupt. */
657 I2C_IE_RRDY | /* Receive Data Ready interrupt. */
658 I2C_IE_ARDY | /* Register Access Ready interrupt. */
659 I2C_IE_NACK | /* No Acknowledgment interrupt. */
660 I2C_IE_AL; /* Arbitration lost interrupt. */
662 /* Enable the interrupts. */
663 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
666 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
667 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
668 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
669 * for the transmit DMA channel).
671 * Not using DMA for now, so ignore this.
678 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
680 struct ti_i2c_softc *sc;
683 sc = device_get_softc(dev);
685 err = ti_i2c_reset(sc, speed);
690 return (IIC_ENOADDR);
694 ti_i2c_activate(device_t dev)
698 struct ti_i2c_softc *sc;
700 sc = (struct ti_i2c_softc*)device_get_softc(dev);
703 * 1. Enable the functional and interface clocks (see Section
706 clk = I2C0_CLK + sc->device_id;
707 err = ti_prcm_clk_enable(clk);
711 return (ti_i2c_reset(sc, IIC_UNKNOWN));
715 * ti_i2c_deactivate - deactivates the controller and releases resources
716 * @dev: i2c device handle
721 * Assumed called in an atomic context.
727 ti_i2c_deactivate(device_t dev)
729 struct ti_i2c_softc *sc = device_get_softc(dev);
732 /* Disable the controller - cancel all transactions. */
733 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
734 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
735 ti_i2c_write_2(sc, I2C_REG_CON, 0);
737 /* Release the interrupt handler. */
738 if (sc->sc_irq_h != NULL) {
739 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
743 bus_generic_detach(sc->sc_dev);
745 /* Unmap the I2C controller registers. */
746 if (sc->sc_mem_res != NULL) {
747 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
748 sc->sc_mem_res = NULL;
751 /* Release the IRQ resource. */
752 if (sc->sc_irq_res != NULL) {
753 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
754 sc->sc_irq_res = NULL;
757 /* Finally disable the functional and interface clocks. */
758 clk = I2C0_CLK + sc->device_id;
759 ti_prcm_clk_disable(clk);
763 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
765 int clk, psc, sclh, scll;
766 struct ti_i2c_softc *sc;
771 /* Get the system prescaler value. */
772 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
774 /* Get the bitrate. */
775 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
776 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
778 clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
781 return (sysctl_handle_int(oidp, &clk, 0, req));
785 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)
787 struct ti_i2c_softc *sc;
794 * MTX_DEF lock can't be held while doing uimove in
798 val = sc->sc_timeout;
801 err = sysctl_handle_int(oidp, &val, 0, req);
803 if ((err == 0) && (req->newptr != NULL)) {
805 sc->sc_timeout = val;
813 ti_i2c_probe(device_t dev)
816 if (!ofw_bus_status_okay(dev))
818 if (!ofw_bus_is_compatible(dev, "ti,i2c"))
820 device_set_desc(dev, "TI I2C Controller");
826 ti_i2c_attach(device_t dev)
830 struct ti_i2c_softc *sc;
831 struct sysctl_ctx_list *ctx;
832 struct sysctl_oid_list *tree;
835 sc = device_get_softc(dev);
838 /* Get the i2c device id from FDT. */
839 node = ofw_bus_get_node(dev);
840 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id,
841 sizeof(sc->device_id))) <= 0) {
842 device_printf(dev, "missing i2c-device-id attribute in FDT\n");
846 /* Get the memory resource for the register mapping. */
848 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
850 if (sc->sc_mem_res == NULL) {
851 device_printf(dev, "Cannot map registers.\n");
855 /* Allocate our IRQ resource. */
857 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
858 RF_ACTIVE | RF_SHAREABLE);
859 if (sc->sc_irq_res == NULL) {
860 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
861 device_printf(dev, "Cannot allocate interrupt.\n");
865 TI_I2C_LOCK_INIT(sc);
867 /* First of all, we _must_ activate the H/W. */
868 err = ti_i2c_activate(dev);
870 device_printf(dev, "ti_i2c_activate failed\n");
874 /* Read the version number of the I2C module */
875 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
877 /* Get the fifo size. */
878 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
879 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
880 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
882 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
883 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
885 /* Set the FIFO threshold to 5 for now. */
886 sc->sc_fifo_trsh = 5;
888 /* Set I2C bus timeout */
889 sc->sc_timeout = 5*hz;
891 ctx = device_get_sysctl_ctx(dev);
892 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
893 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
894 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
895 ti_i2c_sysctl_clk, "IU", "I2C bus clock");
897 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout",
898 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
899 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)");
901 /* Activate the interrupt. */
902 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
903 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
907 /* Attach the iicbus. */
908 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
909 device_printf(dev, "could not allocate iicbus instance\n");
914 /* Probe and attach the iicbus */
915 bus_generic_attach(dev);
919 ti_i2c_deactivate(dev);
920 TI_I2C_LOCK_DESTROY(sc);
927 ti_i2c_detach(device_t dev)
929 struct ti_i2c_softc *sc;
932 sc = device_get_softc(dev);
933 ti_i2c_deactivate(dev);
934 TI_I2C_LOCK_DESTROY(sc);
936 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
943 ti_i2c_get_node(device_t bus, device_t dev)
946 /* Share controller node with iibus device. */
947 return (ofw_bus_get_node(bus));
950 static device_method_t ti_i2c_methods[] = {
951 /* Device interface */
952 DEVMETHOD(device_probe, ti_i2c_probe),
953 DEVMETHOD(device_attach, ti_i2c_attach),
954 DEVMETHOD(device_detach, ti_i2c_detach),
957 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
959 /* iicbus interface */
960 DEVMETHOD(iicbus_callback, iicbus_null_callback),
961 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
962 DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
967 static driver_t ti_i2c_driver = {
970 sizeof(struct ti_i2c_softc),
973 static devclass_t ti_i2c_devclass;
975 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0);
976 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0);
978 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1);
979 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);