2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/mmc/bridge.h>
53 #include <dev/mmc/mmcreg.h>
54 #include <dev/mmc/mmcbrvar.h>
56 #include <dev/sdhci/sdhci.h>
57 #include <dev/sdhci/sdhci_fdt_gpio.h>
60 #include <arm/ti/ti_cpuid.h>
61 #include <arm/ti/ti_prcm.h>
62 #include <arm/ti/ti_hwmods.h>
65 #include "opt_mmccam.h"
67 struct ti_sdhci_softc {
69 struct sdhci_fdt_gpio * gpio;
70 struct resource * mem_res;
71 struct resource * irq_res;
73 struct sdhci_slot slot;
74 clk_ident_t mmchs_clk_id;
75 uint32_t mmchs_reg_off;
76 uint32_t sdhci_reg_off;
78 uint32_t cmd_and_mode;
79 uint32_t sdhci_clkdiv;
80 boolean_t disable_highspeed;
81 boolean_t force_card_present;
82 boolean_t disable_readonly;
86 * Table of supported FDT compat strings.
88 * Note that "ti,mmchs" is our own invention, and should be phased out in favor
89 * of the documented names.
91 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
93 static struct ofw_compat_data compat_data[] = {
94 {"ti,omap3-hsmmc", 1},
95 {"ti,omap4-hsmmc", 1},
101 * The MMCHS hardware has a few control and status registers at the beginning of
102 * the device's memory map, followed by the standard sdhci register block.
103 * Different SoCs have the register blocks at different offsets from the
104 * beginning of the device. Define some constants to map out the registers we
105 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
106 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
108 #define OMAP3_MMCHS_REG_OFFSET 0x000
109 #define OMAP4_MMCHS_REG_OFFSET 0x100
110 #define AM335X_MMCHS_REG_OFFSET 0x100
111 #define SDHCI_REG_OFFSET 0x100
113 #define MMCHS_SYSCONFIG 0x010
114 #define MMCHS_SYSCONFIG_RESET (1 << 1)
115 #define MMCHS_SYSSTATUS 0x014
116 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
117 #define MMCHS_CON 0x02C
118 #define MMCHS_CON_DW8 (1 << 5)
119 #define MMCHS_CON_DVAL_8_4MS (3 << 9)
120 #define MMCHS_CON_OD (1 << 0)
121 #define MMCHS_SYSCTL 0x12C
122 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF
123 #define MMCHS_SYSCTL_CLKD_SHIFT 6
124 #define MMCHS_SD_CAPA 0x140
125 #define MMCHS_SD_CAPA_VS18 (1 << 26)
126 #define MMCHS_SD_CAPA_VS30 (1 << 25)
127 #define MMCHS_SD_CAPA_VS33 (1 << 24)
129 /* Forward declarations, CAM-relataed */
130 // static void ti_sdhci_cam_poll(struct cam_sim *);
131 // static void ti_sdhci_cam_action(struct cam_sim *, union ccb *);
132 // static int ti_sdhci_cam_settran_settings(struct ti_sdhci_softc *sc, union ccb *);
134 static inline uint32_t
135 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
138 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
142 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
145 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
148 static inline uint32_t
149 RD4(struct ti_sdhci_softc *sc, bus_size_t off)
152 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
156 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
159 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
163 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
165 struct ti_sdhci_softc *sc = device_get_softc(dev);
167 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
171 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
173 struct ti_sdhci_softc *sc = device_get_softc(dev);
174 uint32_t clkdiv, val32;
177 * The MMCHS hardware has a non-standard interpretation of the sdclock
178 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6)
179 * but doesn't split them into low:high fields. Instead they're a
180 * single number in the range 0..1023 and the number is exactly the
181 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
182 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking
183 * here extracts the MMCHS representation from the hardware word, cleans
184 * those bits out, applies the 2N adjustment, and plugs the result into
185 * the bit positions for the 2.0 or 3.0 divisor in the returned register
186 * value. The ti_sdhci_write_2() routine performs the opposite
187 * transformation when the SDHCI driver writes to the register.
189 if (off == SDHCI_CLOCK_CONTROL) {
190 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
191 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
192 MMCHS_SYSCTL_CLKD_MASK) / 2;
193 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
194 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
195 if (slot->version >= SDHCI_SPEC_300)
196 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
197 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
198 return (val32 & 0xffff);
202 * Standard 32-bit handling of command and transfer mode.
204 if (off == SDHCI_TRANSFER_MODE) {
205 return (sc->cmd_and_mode >> 16);
206 } else if (off == SDHCI_COMMAND_FLAGS) {
207 return (sc->cmd_and_mode & 0x0000ffff);
210 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
214 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
216 struct ti_sdhci_softc *sc = device_get_softc(dev);
219 val32 = RD4(sc, off);
222 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip
223 * that flag from the returned capabilities.
225 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
226 val32 &= ~SDHCI_CAN_DO_HISPD;
229 * Force the card-present state if necessary.
231 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
232 val32 |= SDHCI_CARD_PRESENT;
238 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
239 uint32_t *data, bus_size_t count)
241 struct ti_sdhci_softc *sc = device_get_softc(dev);
243 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
247 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
250 struct ti_sdhci_softc *sc = device_get_softc(dev);
255 if (off == SDHCI_HOST_CONTROL) {
256 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
258 if (val & SDHCI_CTRL_8BITBUS) {
259 device_printf(dev, "Custom-enabling 8-bit bus\n");
260 newval32 |= MMCHS_CON_DW8;
262 device_printf(dev, "Custom-disabling 8-bit bus\n");
263 newval32 &= ~MMCHS_CON_DW8;
265 if (newval32 != val32)
266 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
269 val32 = RD4(sc, off & ~3);
270 val32 &= ~(0xff << (off & 3) * 8);
271 val32 |= (val << (off & 3) * 8);
273 WR4(sc, off & ~3, val32);
277 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
280 struct ti_sdhci_softc *sc = device_get_softc(dev);
281 uint32_t clkdiv, val32;
284 * Translate between the hardware and SDHCI 2.0 or 3.0 representations
285 * of the clock divisor. See the comments in ti_sdhci_read_2() for
288 if (off == SDHCI_CLOCK_CONTROL) {
289 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
290 if (slot->version >= SDHCI_SPEC_300)
291 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
292 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
294 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
295 clkdiv = MMCHS_SYSCTL_CLKD_MASK;
296 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
298 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
299 MMCHS_SYSCTL_CLKD_SHIFT);
300 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
301 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
306 * Standard 32-bit handling of command and transfer mode.
308 if (off == SDHCI_TRANSFER_MODE) {
309 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
310 ((uint32_t)val & 0x0000ffff);
312 } else if (off == SDHCI_COMMAND_FLAGS) {
313 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
314 ((uint32_t)val << 16);
315 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
319 val32 = RD4(sc, off & ~3);
320 val32 &= ~(0xffff << (off & 3) * 8);
321 val32 |= ((val & 0xffff) << (off & 3) * 8);
322 WR4(sc, off & ~3, val32);
326 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
329 struct ti_sdhci_softc *sc = device_get_softc(dev);
335 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
336 uint32_t *data, bus_size_t count)
338 struct ti_sdhci_softc *sc = device_get_softc(dev);
340 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
344 ti_sdhci_intr(void *arg)
346 struct ti_sdhci_softc *sc = arg;
348 sdhci_generic_intr(&sc->slot);
352 ti_sdhci_update_ios(device_t brdev, device_t reqdev)
354 struct ti_sdhci_softc *sc = device_get_softc(brdev);
355 struct sdhci_slot *slot;
357 uint32_t val32, newval32;
359 slot = device_get_ivars(reqdev);
360 ios = &slot->host.ios;
363 * There is an 8-bit-bus bit in the MMCHS control register which, when
364 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
365 * registers. Set that bit first according to whether an 8-bit bus is
366 * requested, then let the standard driver handle everything else.
368 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
371 if (ios->bus_width == bus_width_8)
372 newval32 |= MMCHS_CON_DW8;
374 newval32 &= ~MMCHS_CON_DW8;
376 if (ios->bus_mode == opendrain)
377 newval32 |= MMCHS_CON_OD;
378 else /* if (ios->bus_mode == pushpull) */
379 newval32 &= ~MMCHS_CON_OD;
381 if (newval32 != val32)
382 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
384 return (sdhci_generic_update_ios(brdev, reqdev));
388 ti_sdhci_get_ro(device_t brdev, device_t reqdev)
390 struct ti_sdhci_softc *sc = device_get_softc(brdev);
392 if (sc->disable_readonly)
395 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
399 ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
401 struct ti_sdhci_softc *sc = device_get_softc(dev);
403 return (sdhci_fdt_gpio_get_present(sc->gpio));
407 ti_sdhci_detach(device_t dev)
410 /* sdhci_fdt_gpio_teardown(sc->gpio); */
416 ti_sdhci_hw_init(device_t dev)
418 struct ti_sdhci_softc *sc = device_get_softc(dev);
420 unsigned long timeout;
422 /* Enable the controller and interface/functional clocks */
423 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) {
424 device_printf(dev, "Error: failed to enable MMC clock\n");
428 /* Get the frequency of the source clock */
429 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id,
430 &sc->baseclk_hz) != 0) {
431 device_printf(dev, "Error: failed to get source clock freq\n");
435 /* Issue a softreset to the controller */
436 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
438 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
439 MMCHS_SYSSTATUS_RESETDONE)) {
440 if (--timeout == 0) {
442 "Error: Controller reset operation timed out\n");
449 * Reset the command and data state machines and also other aspects of
450 * the controller such as bus clock and power.
452 * If we read the software reset register too fast after writing it we
453 * can get back a zero that means the reset hasn't started yet rather
454 * than that the reset is complete. Per TI recommendations, work around
455 * it by reading until we see the reset bit asserted, then read until
456 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
457 * so that the main sdhci driver uses this same logic in its resets.
459 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
461 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
462 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
463 if (--timeout == 0) {
469 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
471 if (--timeout == 0) {
473 "Error: Software reset operation timed out\n");
480 * The attach() routine has examined fdt data and set flags in
481 * slot.host.caps to reflect what voltages we can handle. Set those
482 * values in the CAPA register. The manual says that these values can
483 * only be set once, "before initialization" whatever that means, and
484 * that they survive a reset. So maybe doing this will be a no-op if
485 * u-boot has already initialized the hardware.
487 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
488 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
489 regval |= MMCHS_SD_CAPA_VS18;
490 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
491 regval |= MMCHS_SD_CAPA_VS30;
492 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
494 /* Set initial host configuration (1-bit, std speed, pwr off). */
495 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
496 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
498 /* Set the initial controller configuration. */
499 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
503 ti_sdhci_attach(device_t dev)
505 struct ti_sdhci_softc *sc = device_get_softc(dev);
513 * Get the MMCHS device id from FDT. If it's not there use the newbus
514 * unit number (which will work as long as the devices are in order and
515 * none are skipped in the fdt). Note that this is a property we made
516 * up and added in freebsd, it doesn't exist in the published bindings.
518 node = ofw_bus_get_node(dev);
519 sc->mmchs_clk_id = ti_hwmods_get_clock(dev);
520 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) {
521 device_printf(dev, "failed to get clock based on hwmods property\n");
525 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
526 * device, and only 1p8v on other devices unless an external transceiver
527 * is used. The only way we could know about a transceiver is fdt data.
528 * Note that we have to do this before calling ti_sdhci_hw_init() so
529 * that it can set the right values in the CAPA register, which can only
530 * be done once and never reset.
532 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
533 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) {
534 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
538 * Set the offset from the device's memory start to the MMCHS registers.
539 * Also for OMAP4 disable high speed mode due to erratum ID i626.
544 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
545 sc->disable_highspeed = true;
550 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
554 panic("Unknown OMAP device\n");
558 * The standard SDHCI registers are at a fixed offset (the same on all
559 * SoCs) beyond the MMCHS registers.
561 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
563 /* Resource setup. */
565 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
568 device_printf(dev, "cannot allocate memory window\n");
574 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
577 device_printf(dev, "cannot allocate interrupt\n");
582 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
583 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
584 device_printf(dev, "cannot setup interrupt handler\n");
590 * Set up handling of card-detect and write-protect gpio lines.
592 * If there is no write protect info in the fdt data, fall back to the
593 * historical practice of assuming that the card is writable. This
594 * works around bad fdt data from the upstream source. The alternative
595 * would be to trust the sdhci controller's PRESENT_STATE register WP
596 * bit, but it may say write protect is in effect when it's not if the
597 * pinmux setup doesn't route the WP signal into the sdchi block.
599 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
601 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable"))
602 sc->disable_readonly = true;
604 /* Initialise the MMCHS hardware. */
605 ti_sdhci_hw_init(dev);
608 * The capabilities register can only express base clock frequencies in
609 * the range of 0-63MHz for a v2.0 controller. Since our clock runs
610 * faster than that, the hardware sets the frequency to zero in the
611 * register. When the register contains zero, the sdhci driver expects
612 * slot.max_clk to already have the right value in it.
614 sc->slot.max_clk = sc->baseclk_hz;
617 * The MMCHS timeout counter is based on the output sdclock. Tell the
618 * sdhci driver to recalculate the timeout clock whenever the output
619 * sdclock frequency changes.
621 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
624 * The MMCHS hardware shifts the 136-bit response data (in violation of
625 * the spec), so tell the sdhci driver not to do the same in software.
627 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
630 * Reset bits are broken, have to wait to see the bits asserted
631 * before waiting to see them de-asserted.
633 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
636 * The controller waits for busy responses.
638 sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
641 * DMA is not really broken, I just haven't implemented it yet.
643 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
646 * Set up the hardware and go. Note that this sets many of the
647 * slot.host.* fields, so we have to do this before overriding any of
648 * those values based on fdt data, below.
650 sdhci_init_slot(dev, &sc->slot, 0);
653 * The SDHCI controller doesn't realize it, but we can support 8-bit
654 * even though we're not a v3.0 controller. If there's an fdt bus-width
655 * property, honor it.
657 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
658 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA |
662 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
665 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
670 device_printf(dev, "Bad bus-width value %u\n", prop);
676 * If the slot is flagged with the non-removable property, set our flag
677 * to always force the SDHCI_CARD_PRESENT bit on.
679 node = ofw_bus_get_node(dev);
680 if (OF_hasprop(node, "non-removable"))
681 sc->force_card_present = true;
683 bus_generic_probe(dev);
684 bus_generic_attach(dev);
687 sdhci_cam_start_slot(&sc->slot);
689 sdhci_start_slot(&sc->slot);
695 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
697 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
699 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
705 ti_sdhci_probe(device_t dev)
708 if (!ofw_bus_status_okay(dev))
711 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
712 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
713 return (BUS_PROBE_DEFAULT);
719 static device_method_t ti_sdhci_methods[] = {
720 /* Device interface */
721 DEVMETHOD(device_probe, ti_sdhci_probe),
722 DEVMETHOD(device_attach, ti_sdhci_attach),
723 DEVMETHOD(device_detach, ti_sdhci_detach),
726 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
727 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
729 /* MMC bridge interface */
730 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios),
731 DEVMETHOD(mmcbr_request, sdhci_generic_request),
732 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro),
733 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
734 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
736 /* SDHCI registers accessors */
737 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1),
738 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2),
739 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4),
740 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4),
741 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1),
742 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2),
743 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4),
744 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4),
745 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present),
750 static devclass_t ti_sdhci_devclass;
752 static driver_t ti_sdhci_driver = {
755 sizeof(struct ti_sdhci_softc),
758 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL,
760 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
763 MMC_DECLARE_BRIDGE(sdhci_ti);