2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/resource.h>
42 #include <sys/sysctl.h>
43 #include <sys/taskqueue.h>
45 #include <sys/mutex.h>
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49 #include <machine/intr.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/mmc/bridge.h>
55 #include <dev/mmc/mmcreg.h>
56 #include <dev/mmc/mmcbrvar.h>
58 #include <dev/sdhci/sdhci.h>
59 #include <dev/sdhci/sdhci_fdt_gpio.h>
62 #include <arm/ti/ti_cpuid.h>
63 #include <arm/ti/ti_prcm.h>
64 #include <arm/ti/ti_hwmods.h>
67 #include "opt_mmccam.h"
69 struct ti_sdhci_softc {
71 struct sdhci_fdt_gpio * gpio;
72 struct resource * mem_res;
73 struct resource * irq_res;
75 struct sdhci_slot slot;
76 clk_ident_t mmchs_clk_id;
77 uint32_t mmchs_reg_off;
78 uint32_t sdhci_reg_off;
80 uint32_t cmd_and_mode;
81 uint32_t sdhci_clkdiv;
82 boolean_t disable_highspeed;
83 boolean_t force_card_present;
84 boolean_t disable_readonly;
88 * Table of supported FDT compat strings.
90 * Note that "ti,mmchs" is our own invention, and should be phased out in favor
91 * of the documented names.
93 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
95 static struct ofw_compat_data compat_data[] = {
96 {"ti,omap3-hsmmc", 1},
97 {"ti,omap4-hsmmc", 1},
103 * The MMCHS hardware has a few control and status registers at the beginning of
104 * the device's memory map, followed by the standard sdhci register block.
105 * Different SoCs have the register blocks at different offsets from the
106 * beginning of the device. Define some constants to map out the registers we
107 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
108 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
110 #define OMAP3_MMCHS_REG_OFFSET 0x000
111 #define OMAP4_MMCHS_REG_OFFSET 0x100
112 #define AM335X_MMCHS_REG_OFFSET 0x100
113 #define SDHCI_REG_OFFSET 0x100
115 #define MMCHS_SYSCONFIG 0x010
116 #define MMCHS_SYSCONFIG_RESET (1 << 1)
117 #define MMCHS_SYSSTATUS 0x014
118 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
119 #define MMCHS_CON 0x02C
120 #define MMCHS_CON_DW8 (1 << 5)
121 #define MMCHS_CON_DVAL_8_4MS (3 << 9)
122 #define MMCHS_CON_OD (1 << 0)
123 #define MMCHS_SYSCTL 0x12C
124 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF
125 #define MMCHS_SYSCTL_CLKD_SHIFT 6
126 #define MMCHS_SD_CAPA 0x140
127 #define MMCHS_SD_CAPA_VS18 (1 << 26)
128 #define MMCHS_SD_CAPA_VS30 (1 << 25)
129 #define MMCHS_SD_CAPA_VS33 (1 << 24)
131 /* Forward declarations, CAM-relataed */
132 // static void ti_sdhci_cam_poll(struct cam_sim *);
133 // static void ti_sdhci_cam_action(struct cam_sim *, union ccb *);
134 // static int ti_sdhci_cam_settran_settings(struct ti_sdhci_softc *sc, union ccb *);
136 static inline uint32_t
137 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
140 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
144 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
147 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
150 static inline uint32_t
151 RD4(struct ti_sdhci_softc *sc, bus_size_t off)
154 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
158 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
161 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
165 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
167 struct ti_sdhci_softc *sc = device_get_softc(dev);
169 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
173 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
175 struct ti_sdhci_softc *sc = device_get_softc(dev);
176 uint32_t clkdiv, val32;
179 * The MMCHS hardware has a non-standard interpretation of the sdclock
180 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6)
181 * but doesn't split them into low:high fields. Instead they're a
182 * single number in the range 0..1023 and the number is exactly the
183 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
184 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking
185 * here extracts the MMCHS representation from the hardware word, cleans
186 * those bits out, applies the 2N adjustment, and plugs the result into
187 * the bit positions for the 2.0 or 3.0 divisor in the returned register
188 * value. The ti_sdhci_write_2() routine performs the opposite
189 * transformation when the SDHCI driver writes to the register.
191 if (off == SDHCI_CLOCK_CONTROL) {
192 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
193 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
194 MMCHS_SYSCTL_CLKD_MASK) / 2;
195 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
196 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
197 if (slot->version >= SDHCI_SPEC_300)
198 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
199 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
200 return (val32 & 0xffff);
204 * Standard 32-bit handling of command and transfer mode.
206 if (off == SDHCI_TRANSFER_MODE) {
207 return (sc->cmd_and_mode >> 16);
208 } else if (off == SDHCI_COMMAND_FLAGS) {
209 return (sc->cmd_and_mode & 0x0000ffff);
212 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
216 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
218 struct ti_sdhci_softc *sc = device_get_softc(dev);
221 val32 = RD4(sc, off);
224 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip
225 * that flag from the returned capabilities.
227 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
228 val32 &= ~SDHCI_CAN_DO_HISPD;
231 * Force the card-present state if necessary.
233 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
234 val32 |= SDHCI_CARD_PRESENT;
240 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
241 uint32_t *data, bus_size_t count)
243 struct ti_sdhci_softc *sc = device_get_softc(dev);
245 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
249 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
252 struct ti_sdhci_softc *sc = device_get_softc(dev);
257 if (off == SDHCI_HOST_CONTROL) {
258 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
260 if (val & SDHCI_CTRL_8BITBUS) {
261 device_printf(dev, "Custom-enabling 8-bit bus\n");
262 newval32 |= MMCHS_CON_DW8;
264 device_printf(dev, "Custom-disabling 8-bit bus\n");
265 newval32 &= ~MMCHS_CON_DW8;
267 if (newval32 != val32)
268 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
271 val32 = RD4(sc, off & ~3);
272 val32 &= ~(0xff << (off & 3) * 8);
273 val32 |= (val << (off & 3) * 8);
275 WR4(sc, off & ~3, val32);
279 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
282 struct ti_sdhci_softc *sc = device_get_softc(dev);
283 uint32_t clkdiv, val32;
286 * Translate between the hardware and SDHCI 2.0 or 3.0 representations
287 * of the clock divisor. See the comments in ti_sdhci_read_2() for
290 if (off == SDHCI_CLOCK_CONTROL) {
291 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
292 if (slot->version >= SDHCI_SPEC_300)
293 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
294 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
296 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
297 clkdiv = MMCHS_SYSCTL_CLKD_MASK;
298 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
300 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
301 MMCHS_SYSCTL_CLKD_SHIFT);
302 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
303 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
308 * Standard 32-bit handling of command and transfer mode.
310 if (off == SDHCI_TRANSFER_MODE) {
311 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
312 ((uint32_t)val & 0x0000ffff);
314 } else if (off == SDHCI_COMMAND_FLAGS) {
315 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
316 ((uint32_t)val << 16);
317 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
321 val32 = RD4(sc, off & ~3);
322 val32 &= ~(0xffff << (off & 3) * 8);
323 val32 |= ((val & 0xffff) << (off & 3) * 8);
324 WR4(sc, off & ~3, val32);
328 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
331 struct ti_sdhci_softc *sc = device_get_softc(dev);
337 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
338 uint32_t *data, bus_size_t count)
340 struct ti_sdhci_softc *sc = device_get_softc(dev);
342 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
346 ti_sdhci_intr(void *arg)
348 struct ti_sdhci_softc *sc = arg;
350 sdhci_generic_intr(&sc->slot);
354 ti_sdhci_update_ios(device_t brdev, device_t reqdev)
356 struct ti_sdhci_softc *sc = device_get_softc(brdev);
357 struct sdhci_slot *slot;
359 uint32_t val32, newval32;
361 slot = device_get_ivars(reqdev);
362 ios = &slot->host.ios;
365 * There is an 8-bit-bus bit in the MMCHS control register which, when
366 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
367 * registers. Set that bit first according to whether an 8-bit bus is
368 * requested, then let the standard driver handle everything else.
370 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
373 if (ios->bus_width == bus_width_8)
374 newval32 |= MMCHS_CON_DW8;
376 newval32 &= ~MMCHS_CON_DW8;
378 if (ios->bus_mode == opendrain)
379 newval32 |= MMCHS_CON_OD;
380 else /* if (ios->bus_mode == pushpull) */
381 newval32 &= ~MMCHS_CON_OD;
383 if (newval32 != val32)
384 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
386 return (sdhci_generic_update_ios(brdev, reqdev));
390 ti_sdhci_get_ro(device_t brdev, device_t reqdev)
392 struct ti_sdhci_softc *sc = device_get_softc(brdev);
394 if (sc->disable_readonly)
397 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
401 ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
403 struct ti_sdhci_softc *sc = device_get_softc(dev);
405 return (sdhci_fdt_gpio_get_present(sc->gpio));
409 ti_sdhci_detach(device_t dev)
412 /* sdhci_fdt_gpio_teardown(sc->gpio); */
418 ti_sdhci_hw_init(device_t dev)
420 struct ti_sdhci_softc *sc = device_get_softc(dev);
422 unsigned long timeout;
424 /* Enable the controller and interface/functional clocks */
425 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) {
426 device_printf(dev, "Error: failed to enable MMC clock\n");
430 /* Get the frequency of the source clock */
431 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id,
432 &sc->baseclk_hz) != 0) {
433 device_printf(dev, "Error: failed to get source clock freq\n");
437 /* Issue a softreset to the controller */
438 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
440 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
441 MMCHS_SYSSTATUS_RESETDONE)) {
442 if (--timeout == 0) {
444 "Error: Controller reset operation timed out\n");
451 * Reset the command and data state machines and also other aspects of
452 * the controller such as bus clock and power.
454 * If we read the software reset register too fast after writing it we
455 * can get back a zero that means the reset hasn't started yet rather
456 * than that the reset is complete. Per TI recommendations, work around
457 * it by reading until we see the reset bit asserted, then read until
458 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
459 * so that the main sdhci driver uses this same logic in its resets.
461 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
463 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
464 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
465 if (--timeout == 0) {
471 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
473 if (--timeout == 0) {
475 "Error: Software reset operation timed out\n");
482 * The attach() routine has examined fdt data and set flags in
483 * slot.host.caps to reflect what voltages we can handle. Set those
484 * values in the CAPA register. The manual says that these values can
485 * only be set once, "before initialization" whatever that means, and
486 * that they survive a reset. So maybe doing this will be a no-op if
487 * u-boot has already initialized the hardware.
489 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
490 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
491 regval |= MMCHS_SD_CAPA_VS18;
492 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
493 regval |= MMCHS_SD_CAPA_VS30;
494 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
496 /* Set initial host configuration (1-bit, std speed, pwr off). */
497 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
498 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
500 /* Set the initial controller configuration. */
501 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
505 ti_sdhci_attach(device_t dev)
507 struct ti_sdhci_softc *sc = device_get_softc(dev);
515 * Get the MMCHS device id from FDT. If it's not there use the newbus
516 * unit number (which will work as long as the devices are in order and
517 * none are skipped in the fdt). Note that this is a property we made
518 * up and added in freebsd, it doesn't exist in the published bindings.
520 node = ofw_bus_get_node(dev);
521 sc->mmchs_clk_id = ti_hwmods_get_clock(dev);
522 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) {
523 device_printf(dev, "failed to get clock based on hwmods property\n");
527 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
528 * device, and only 1p8v on other devices unless an external transceiver
529 * is used. The only way we could know about a transceiver is fdt data.
530 * Note that we have to do this before calling ti_sdhci_hw_init() so
531 * that it can set the right values in the CAPA register, which can only
532 * be done once and never reset.
534 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
535 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) {
536 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
540 * Set the offset from the device's memory start to the MMCHS registers.
541 * Also for OMAP4 disable high speed mode due to erratum ID i626.
546 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
547 sc->disable_highspeed = true;
552 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
556 panic("Unknown OMAP device\n");
560 * The standard SDHCI registers are at a fixed offset (the same on all
561 * SoCs) beyond the MMCHS registers.
563 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
565 /* Resource setup. */
567 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
570 device_printf(dev, "cannot allocate memory window\n");
576 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
579 device_printf(dev, "cannot allocate interrupt\n");
584 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
585 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
586 device_printf(dev, "cannot setup interrupt handler\n");
592 * Set up handling of card-detect and write-protect gpio lines.
594 * If there is no write protect info in the fdt data, fall back to the
595 * historical practice of assuming that the card is writable. This
596 * works around bad fdt data from the upstream source. The alternative
597 * would be to trust the sdhci controller's PRESENT_STATE register WP
598 * bit, but it may say write protect is in effect when it's not if the
599 * pinmux setup doesn't route the WP signal into the sdchi block.
601 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
603 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable"))
604 sc->disable_readonly = true;
606 /* Initialise the MMCHS hardware. */
607 ti_sdhci_hw_init(dev);
610 * The capabilities register can only express base clock frequencies in
611 * the range of 0-63MHz for a v2.0 controller. Since our clock runs
612 * faster than that, the hardware sets the frequency to zero in the
613 * register. When the register contains zero, the sdhci driver expects
614 * slot.max_clk to already have the right value in it.
616 sc->slot.max_clk = sc->baseclk_hz;
619 * The MMCHS timeout counter is based on the output sdclock. Tell the
620 * sdhci driver to recalculate the timeout clock whenever the output
621 * sdclock frequency changes.
623 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
626 * The MMCHS hardware shifts the 136-bit response data (in violation of
627 * the spec), so tell the sdhci driver not to do the same in software.
629 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
632 * Reset bits are broken, have to wait to see the bits asserted
633 * before waiting to see them de-asserted.
635 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
638 * The controller waits for busy responses.
640 sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
643 * DMA is not really broken, I just haven't implemented it yet.
645 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
648 * Set up the hardware and go. Note that this sets many of the
649 * slot.host.* fields, so we have to do this before overriding any of
650 * those values based on fdt data, below.
652 sdhci_init_slot(dev, &sc->slot, 0);
655 * The SDHCI controller doesn't realize it, but we can support 8-bit
656 * even though we're not a v3.0 controller. If there's an fdt bus-width
657 * property, honor it.
659 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
660 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA |
664 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
667 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
672 device_printf(dev, "Bad bus-width value %u\n", prop);
678 * If the slot is flagged with the non-removable property, set our flag
679 * to always force the SDHCI_CARD_PRESENT bit on.
681 node = ofw_bus_get_node(dev);
682 if (OF_hasprop(node, "non-removable"))
683 sc->force_card_present = true;
685 bus_generic_probe(dev);
686 bus_generic_attach(dev);
688 sdhci_start_slot(&sc->slot);
693 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
695 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
697 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
703 ti_sdhci_probe(device_t dev)
706 if (!ofw_bus_status_okay(dev))
709 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
710 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
711 return (BUS_PROBE_DEFAULT);
717 static device_method_t ti_sdhci_methods[] = {
718 /* Device interface */
719 DEVMETHOD(device_probe, ti_sdhci_probe),
720 DEVMETHOD(device_attach, ti_sdhci_attach),
721 DEVMETHOD(device_detach, ti_sdhci_detach),
724 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
725 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
727 /* MMC bridge interface */
728 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios),
729 DEVMETHOD(mmcbr_request, sdhci_generic_request),
730 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro),
731 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
732 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
734 /* SDHCI registers accessors */
735 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1),
736 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2),
737 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4),
738 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4),
739 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1),
740 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2),
741 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4),
742 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4),
743 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present),
748 static devclass_t ti_sdhci_devclass;
750 static driver_t ti_sdhci_driver = {
753 sizeof(struct ti_sdhci_softc),
756 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL,
758 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
761 MMC_DECLARE_BRIDGE(sdhci_ti);