2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcreg.h>
52 #include <dev/mmc/mmcbrvar.h>
54 #include <dev/sdhci/sdhci.h>
55 #include <dev/sdhci/sdhci_fdt_gpio.h>
58 #include <arm/ti/ti_cpuid.h>
59 #include <arm/ti/ti_prcm.h>
60 #include <arm/ti/ti_hwmods.h>
63 struct ti_sdhci_softc {
65 struct sdhci_fdt_gpio * gpio;
66 struct resource * mem_res;
67 struct resource * irq_res;
69 struct sdhci_slot slot;
70 clk_ident_t mmchs_clk_id;
71 uint32_t mmchs_reg_off;
72 uint32_t sdhci_reg_off;
74 uint32_t cmd_and_mode;
75 uint32_t sdhci_clkdiv;
76 boolean_t disable_highspeed;
77 boolean_t force_card_present;
78 boolean_t disable_readonly;
82 * Table of supported FDT compat strings.
84 * Note that "ti,mmchs" is our own invention, and should be phased out in favor
85 * of the documented names.
87 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
89 static struct ofw_compat_data compat_data[] = {
90 {"ti,omap3-hsmmc", 1},
91 {"ti,omap4-hsmmc", 1},
97 * The MMCHS hardware has a few control and status registers at the beginning of
98 * the device's memory map, followed by the standard sdhci register block.
99 * Different SoCs have the register blocks at different offsets from the
100 * beginning of the device. Define some constants to map out the registers we
101 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
102 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
104 #define OMAP3_MMCHS_REG_OFFSET 0x000
105 #define OMAP4_MMCHS_REG_OFFSET 0x100
106 #define AM335X_MMCHS_REG_OFFSET 0x100
107 #define SDHCI_REG_OFFSET 0x100
109 #define MMCHS_SYSCONFIG 0x010
110 #define MMCHS_SYSCONFIG_RESET (1 << 1)
111 #define MMCHS_SYSSTATUS 0x014
112 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
113 #define MMCHS_CON 0x02C
114 #define MMCHS_CON_DW8 (1 << 5)
115 #define MMCHS_CON_DVAL_8_4MS (3 << 9)
116 #define MMCHS_CON_OD (1 << 0)
117 #define MMCHS_SYSCTL 0x12C
118 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF
119 #define MMCHS_SYSCTL_CLKD_SHIFT 6
120 #define MMCHS_SD_CAPA 0x140
121 #define MMCHS_SD_CAPA_VS18 (1 << 26)
122 #define MMCHS_SD_CAPA_VS30 (1 << 25)
123 #define MMCHS_SD_CAPA_VS33 (1 << 24)
125 static inline uint32_t
126 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
129 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
133 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
136 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
139 static inline uint32_t
140 RD4(struct ti_sdhci_softc *sc, bus_size_t off)
143 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
147 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
150 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
154 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
156 struct ti_sdhci_softc *sc = device_get_softc(dev);
158 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
162 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
164 struct ti_sdhci_softc *sc = device_get_softc(dev);
165 uint32_t clkdiv, val32;
168 * The MMCHS hardware has a non-standard interpretation of the sdclock
169 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6)
170 * but doesn't split them into low:high fields. Instead they're a
171 * single number in the range 0..1023 and the number is exactly the
172 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
173 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking
174 * here extracts the MMCHS representation from the hardware word, cleans
175 * those bits out, applies the 2N adjustment, and plugs the result into
176 * the bit positions for the 2.0 or 3.0 divisor in the returned register
177 * value. The ti_sdhci_write_2() routine performs the opposite
178 * transformation when the SDHCI driver writes to the register.
180 if (off == SDHCI_CLOCK_CONTROL) {
181 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
182 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
183 MMCHS_SYSCTL_CLKD_MASK) / 2;
184 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
185 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
186 if (slot->version >= SDHCI_SPEC_300)
187 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
188 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
189 return (val32 & 0xffff);
193 * Standard 32-bit handling of command and transfer mode.
195 if (off == SDHCI_TRANSFER_MODE) {
196 return (sc->cmd_and_mode >> 16);
197 } else if (off == SDHCI_COMMAND_FLAGS) {
198 return (sc->cmd_and_mode & 0x0000ffff);
201 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
205 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
207 struct ti_sdhci_softc *sc = device_get_softc(dev);
210 val32 = RD4(sc, off);
213 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip
214 * that flag from the returned capabilities.
216 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
217 val32 &= ~SDHCI_CAN_DO_HISPD;
220 * Force the card-present state if necessary.
222 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
223 val32 |= SDHCI_CARD_PRESENT;
229 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
230 uint32_t *data, bus_size_t count)
232 struct ti_sdhci_softc *sc = device_get_softc(dev);
234 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
238 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
241 struct ti_sdhci_softc *sc = device_get_softc(dev);
244 val32 = RD4(sc, off & ~3);
245 val32 &= ~(0xff << (off & 3) * 8);
246 val32 |= (val << (off & 3) * 8);
248 WR4(sc, off & ~3, val32);
252 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
255 struct ti_sdhci_softc *sc = device_get_softc(dev);
256 uint32_t clkdiv, val32;
259 * Translate between the hardware and SDHCI 2.0 or 3.0 representations
260 * of the clock divisor. See the comments in ti_sdhci_read_2() for
263 if (off == SDHCI_CLOCK_CONTROL) {
264 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
265 if (slot->version >= SDHCI_SPEC_300)
266 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
267 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
269 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
270 clkdiv = MMCHS_SYSCTL_CLKD_MASK;
271 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
273 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
274 MMCHS_SYSCTL_CLKD_SHIFT);
275 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
276 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
281 * Standard 32-bit handling of command and transfer mode.
283 if (off == SDHCI_TRANSFER_MODE) {
284 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
285 ((uint32_t)val & 0x0000ffff);
287 } else if (off == SDHCI_COMMAND_FLAGS) {
288 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
289 ((uint32_t)val << 16);
290 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
294 val32 = RD4(sc, off & ~3);
295 val32 &= ~(0xffff << (off & 3) * 8);
296 val32 |= ((val & 0xffff) << (off & 3) * 8);
297 WR4(sc, off & ~3, val32);
301 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
304 struct ti_sdhci_softc *sc = device_get_softc(dev);
310 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
311 uint32_t *data, bus_size_t count)
313 struct ti_sdhci_softc *sc = device_get_softc(dev);
315 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
319 ti_sdhci_intr(void *arg)
321 struct ti_sdhci_softc *sc = arg;
323 sdhci_generic_intr(&sc->slot);
327 ti_sdhci_update_ios(device_t brdev, device_t reqdev)
329 struct ti_sdhci_softc *sc = device_get_softc(brdev);
330 struct sdhci_slot *slot;
332 uint32_t val32, newval32;
334 slot = device_get_ivars(reqdev);
335 ios = &slot->host.ios;
338 * There is an 8-bit-bus bit in the MMCHS control register which, when
339 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
340 * registers. Set that bit first according to whether an 8-bit bus is
341 * requested, then let the standard driver handle everything else.
343 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
346 if (ios->bus_width == bus_width_8)
347 newval32 |= MMCHS_CON_DW8;
349 newval32 &= ~MMCHS_CON_DW8;
351 if (ios->bus_mode == opendrain)
352 newval32 |= MMCHS_CON_OD;
353 else /* if (ios->bus_mode == pushpull) */
354 newval32 &= ~MMCHS_CON_OD;
356 if (newval32 != val32)
357 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
359 return (sdhci_generic_update_ios(brdev, reqdev));
363 ti_sdhci_get_ro(device_t brdev, device_t reqdev)
365 struct ti_sdhci_softc *sc = device_get_softc(brdev);
367 if (sc->disable_readonly)
370 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
374 ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
376 struct ti_sdhci_softc *sc = device_get_softc(dev);
378 return (sdhci_fdt_gpio_get_present(sc->gpio));
382 ti_sdhci_detach(device_t dev)
385 /* sdhci_fdt_gpio_teardown(sc->gpio); */
391 ti_sdhci_hw_init(device_t dev)
393 struct ti_sdhci_softc *sc = device_get_softc(dev);
395 unsigned long timeout;
397 /* Enable the controller and interface/functional clocks */
398 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) {
399 device_printf(dev, "Error: failed to enable MMC clock\n");
403 /* Get the frequency of the source clock */
404 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id,
405 &sc->baseclk_hz) != 0) {
406 device_printf(dev, "Error: failed to get source clock freq\n");
410 /* Issue a softreset to the controller */
411 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
413 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
414 MMCHS_SYSSTATUS_RESETDONE)) {
415 if (--timeout == 0) {
417 "Error: Controller reset operation timed out\n");
424 * Reset the command and data state machines and also other aspects of
425 * the controller such as bus clock and power.
427 * If we read the software reset register too fast after writing it we
428 * can get back a zero that means the reset hasn't started yet rather
429 * than that the reset is complete. Per TI recommendations, work around
430 * it by reading until we see the reset bit asserted, then read until
431 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
432 * so that the main sdhci driver uses this same logic in its resets.
434 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
436 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
437 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
438 if (--timeout == 0) {
444 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
446 if (--timeout == 0) {
448 "Error: Software reset operation timed out\n");
455 * The attach() routine has examined fdt data and set flags in
456 * slot.host.caps to reflect what voltages we can handle. Set those
457 * values in the CAPA register. The manual says that these values can
458 * only be set once, "before initialization" whatever that means, and
459 * that they survive a reset. So maybe doing this will be a no-op if
460 * u-boot has already initialized the hardware.
462 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
463 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
464 regval |= MMCHS_SD_CAPA_VS18;
465 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
466 regval |= MMCHS_SD_CAPA_VS30;
467 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
469 /* Set initial host configuration (1-bit, std speed, pwr off). */
470 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
471 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
473 /* Set the initial controller configuration. */
474 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
478 ti_sdhci_attach(device_t dev)
480 struct ti_sdhci_softc *sc = device_get_softc(dev);
488 * Get the MMCHS device id from FDT. If it's not there use the newbus
489 * unit number (which will work as long as the devices are in order and
490 * none are skipped in the fdt). Note that this is a property we made
491 * up and added in freebsd, it doesn't exist in the published bindings.
493 node = ofw_bus_get_node(dev);
494 sc->mmchs_clk_id = ti_hwmods_get_clock(dev);
495 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) {
496 device_printf(dev, "failed to get clock based on hwmods property\n");
500 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
501 * device, and only 1p8v on other devices unless an external transceiver
502 * is used. The only way we could know about a transceiver is fdt data.
503 * Note that we have to do this before calling ti_sdhci_hw_init() so
504 * that it can set the right values in the CAPA register, which can only
505 * be done once and never reset.
507 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
508 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) {
509 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
513 * Set the offset from the device's memory start to the MMCHS registers.
514 * Also for OMAP4 disable high speed mode due to erratum ID i626.
519 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
520 sc->disable_highspeed = true;
525 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
529 panic("Unknown OMAP device\n");
533 * The standard SDHCI registers are at a fixed offset (the same on all
534 * SoCs) beyond the MMCHS registers.
536 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
538 /* Resource setup. */
540 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
543 device_printf(dev, "cannot allocate memory window\n");
549 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
552 device_printf(dev, "cannot allocate interrupt\n");
557 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
558 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
559 device_printf(dev, "cannot setup interrupt handler\n");
565 * Set up handling of card-detect and write-protect gpio lines.
567 * If there is no write protect info in the fdt data, fall back to the
568 * historical practice of assuming that the card is writable. This
569 * works around bad fdt data from the upstream source. The alternative
570 * would be to trust the sdhci controller's PRESENT_STATE register WP
571 * bit, but it may say write protect is in effect when it's not if the
572 * pinmux setup doesn't route the WP signal into the sdchi block.
574 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
576 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable"))
577 sc->disable_readonly = true;
579 /* Initialise the MMCHS hardware. */
580 ti_sdhci_hw_init(dev);
583 * The capabilities register can only express base clock frequencies in
584 * the range of 0-63MHz for a v2.0 controller. Since our clock runs
585 * faster than that, the hardware sets the frequency to zero in the
586 * register. When the register contains zero, the sdhci driver expects
587 * slot.max_clk to already have the right value in it.
589 sc->slot.max_clk = sc->baseclk_hz;
592 * The MMCHS timeout counter is based on the output sdclock. Tell the
593 * sdhci driver to recalculate the timeout clock whenever the output
594 * sdclock frequency changes.
596 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
599 * The MMCHS hardware shifts the 136-bit response data (in violation of
600 * the spec), so tell the sdhci driver not to do the same in software.
602 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
605 * Reset bits are broken, have to wait to see the bits asserted
606 * before waiting to see them de-asserted.
608 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
611 * The controller waits for busy responses.
613 sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
616 * DMA is not really broken, I just haven't implemented it yet.
618 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
621 * Set up the hardware and go. Note that this sets many of the
622 * slot.host.* fields, so we have to do this before overriding any of
623 * those values based on fdt data, below.
625 sdhci_init_slot(dev, &sc->slot, 0);
628 * The SDHCI controller doesn't realize it, but we can support 8-bit
629 * even though we're not a v3.0 controller. If there's an fdt bus-width
630 * property, honor it.
632 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
633 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA |
637 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
640 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
645 device_printf(dev, "Bad bus-width value %u\n", prop);
651 * If the slot is flagged with the non-removable property, set our flag
652 * to always force the SDHCI_CARD_PRESENT bit on.
654 node = ofw_bus_get_node(dev);
655 if (OF_hasprop(node, "non-removable"))
656 sc->force_card_present = true;
658 bus_generic_probe(dev);
659 bus_generic_attach(dev);
661 sdhci_start_slot(&sc->slot);
667 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
669 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
671 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
677 ti_sdhci_probe(device_t dev)
680 if (!ofw_bus_status_okay(dev))
683 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
684 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
685 return (BUS_PROBE_DEFAULT);
691 static device_method_t ti_sdhci_methods[] = {
692 /* Device interface */
693 DEVMETHOD(device_probe, ti_sdhci_probe),
694 DEVMETHOD(device_attach, ti_sdhci_attach),
695 DEVMETHOD(device_detach, ti_sdhci_detach),
698 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
699 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
701 /* MMC bridge interface */
702 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios),
703 DEVMETHOD(mmcbr_request, sdhci_generic_request),
704 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro),
705 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
706 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
708 /* SDHCI registers accessors */
709 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1),
710 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2),
711 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4),
712 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4),
713 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1),
714 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2),
715 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4),
716 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4),
717 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present),
722 static devclass_t ti_sdhci_devclass;
724 static driver_t ti_sdhci_driver = {
727 sizeof(struct ti_sdhci_softc),
730 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL,
732 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
733 MMC_DECLARE_BRIDGE(sdhci_ti);