3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/interrupt.h>
37 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
43 #include <sys/timetc.h>
44 #include <machine/bus.h>
45 #include <machine/intr.h>
47 #include <dev/ofw/openfirm.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
51 #include <arm/ti/ti_cpuid.h>
52 #include <arm/ti/ti_prcm.h>
53 #include <arm/ti/ti_sdma.h>
54 #include <arm/ti/ti_sdmareg.h>
57 * Kernel functions for using the DMA controller
61 * A DMA transfer block consists of a number of frames (FN). Each frame
62 * consists of a number of elements, and each element can have a size of 8, 16,
65 * OMAP44xx and newer chips support linked list (aka scatter gather) transfers,
66 * where a linked list of source/destination pairs can be placed in memory
67 * for the H/W to process. Earlier chips only allowed you to chain multiple
68 * channels together. However currently this linked list feature is not
69 * supported by the driver.
74 * Data structure per DMA channel.
78 struct ti_sdma_channel {
81 * The configuration registers for the given channel, these are modified
82 * by the set functions and only written to the actual registers when a
83 * transaction is started.
89 /* Set when one of the configuration registers above change */
90 uint32_t need_reg_write;
92 /* Callback function used when an interrupt is tripped on the given channel */
93 void (*callback)(unsigned int ch, uint32_t ch_status, void *data);
95 /* Callback data passed in the callback ... duh */
101 * DMA driver context, allocated and stored globally, this driver is not
102 * intetned to ever be unloaded (see ti_sdma_sc).
105 struct ti_sdma_softc {
107 struct resource* sc_irq_res;
108 struct resource* sc_mem_res;
111 * I guess in theory we should have a mutex per DMA channel for register
112 * modifications. But since we know we are never going to be run on a SMP
113 * system, we can use just the single lock for all channels.
117 /* Stores the H/W revision read from the registers */
121 * Bits in the sc_active_channels data field indicate if the channel has
124 uint32_t sc_active_channels;
126 struct ti_sdma_channel sc_channel[NUM_DMA_CHANNELS];
130 static struct ti_sdma_softc *ti_sdma_sc = NULL;
133 * Macros for driver mutex locking
135 #define TI_SDMA_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
136 #define TI_SDMA_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
137 #define TI_SDMA_LOCK_INIT(_sc) \
138 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
140 #define TI_SDMA_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
141 #define TI_SDMA_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
142 #define TI_SDMA_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
145 * Function prototypes
148 static void ti_sdma_intr(void *);
151 * ti_sdma_read_4 - reads a 32-bit value from one of the DMA registers
152 * @sc: DMA device context
153 * @off: The offset of a register from the DMA register address range
157 * 32-bit value read from the register.
159 static inline uint32_t
160 ti_sdma_read_4(struct ti_sdma_softc *sc, bus_size_t off)
162 return bus_read_4(sc->sc_mem_res, off);
166 * ti_sdma_write_4 - writes a 32-bit value to one of the DMA registers
167 * @sc: DMA device context
168 * @off: The offset of a register from the DMA register address range
172 * 32-bit value read from the register.
175 ti_sdma_write_4(struct ti_sdma_softc *sc, bus_size_t off, uint32_t val)
177 bus_write_4(sc->sc_mem_res, off, val);
181 * ti_sdma_is_omap3_rev - returns true if H/W is from OMAP3 series
182 * @sc: DMA device context
186 ti_sdma_is_omap3_rev(struct ti_sdma_softc *sc)
188 return (sc->sc_hw_rev == DMA4_OMAP3_REV);
192 * ti_sdma_is_omap4_rev - returns true if H/W is from OMAP4 series
193 * @sc: DMA device context
197 ti_sdma_is_omap4_rev(struct ti_sdma_softc *sc)
199 return (sc->sc_hw_rev == DMA4_OMAP4_REV);
203 * ti_sdma_intr - interrupt handler for all 4 DMA IRQs
206 * Called when any of the four DMA IRQs are triggered.
209 * DMA registers protected by internal mutex
215 ti_sdma_intr(void *arg)
217 struct ti_sdma_softc *sc = ti_sdma_sc;
221 struct ti_sdma_channel* channel;
225 for (j = 0; j < NUM_DMA_IRQS; j++) {
227 /* Get the flag interrupts (enabled) */
228 intr = ti_sdma_read_4(sc, DMA4_IRQSTATUS_L(j));
229 intr &= ti_sdma_read_4(sc, DMA4_IRQENABLE_L(j));
230 if (intr == 0x00000000)
233 /* Loop through checking the status bits */
234 for (ch = 0; ch < NUM_DMA_CHANNELS; ch++) {
235 if (intr & (1 << ch)) {
236 channel = &sc->sc_channel[ch];
238 /* Read the CSR regsiter and verify we don't have a spurious IRQ */
239 csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
241 device_printf(sc->sc_dev, "Spurious DMA IRQ for channel "
246 /* Sanity check this channel is active */
247 if ((sc->sc_active_channels & (1 << ch)) == 0) {
248 device_printf(sc->sc_dev, "IRQ %d for a non-activated "
249 "channel %d\n", j, ch);
253 /* Check the status error codes */
254 if (csr & DMA4_CSR_DROP)
255 device_printf(sc->sc_dev, "Synchronization event drop "
256 "occurred during the transfer on channel %u\n",
258 if (csr & DMA4_CSR_SECURE_ERR)
259 device_printf(sc->sc_dev, "Secure transaction error event "
260 "on channel %u\n", ch);
261 if (csr & DMA4_CSR_MISALIGNED_ADRS_ERR)
262 device_printf(sc->sc_dev, "Misaligned address error event "
263 "on channel %u\n", ch);
264 if (csr & DMA4_CSR_TRANS_ERR) {
265 device_printf(sc->sc_dev, "Transaction error event on "
268 * Apparently according to linux code, there is an errata
269 * that says the channel is not disabled upon this error.
270 * They explicitly disable the channel here .. since I
271 * haven't seen the errata, I'm going to ignore for now.
275 /* Clear the status flags for the IRQ */
276 ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
277 ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
279 /* Call the callback for the given channel */
280 if (channel->callback)
281 channel->callback(ch, csr, channel->callback_data);
292 * ti_sdma_activate_channel - activates a DMA channel
293 * @ch: upon return contains the channel allocated
294 * @callback: a callback function to associate with the channel
295 * @data: optional data supplied when the callback is called
297 * Simply activates a channel be enabling and writing default values to the
298 * channel's register set. It doesn't start a transaction, just populates the
299 * internal data structures and sets defaults.
301 * Note this function doesn't enable interrupts, for that you need to call
302 * ti_sdma_enable_channel_irq(). If not using IRQ to detect the end of the
303 * transfer, you can use ti_sdma_status_poll() to detect a change in the
306 * A channel must be activated before any of the other DMA functions can be
310 * DMA registers protected by internal mutex
313 * 0 on success, otherwise an error code
316 ti_sdma_activate_channel(unsigned int *ch,
317 void (*callback)(unsigned int ch, uint32_t status, void *data),
320 struct ti_sdma_softc *sc = ti_sdma_sc;
321 struct ti_sdma_channel *channel = NULL;
334 /* Check to see if all channels are in use */
335 if (sc->sc_active_channels == 0xffffffff) {
340 /* Find the first non-active channel */
341 for (i = 0; i < NUM_DMA_CHANNELS; i++) {
342 if (!(sc->sc_active_channels & (0x1 << i))) {
343 sc->sc_active_channels |= (0x1 << i);
349 /* Get the channel struct and populate the fields */
350 channel = &sc->sc_channel[*ch];
352 channel->callback = callback;
353 channel->callback_data = data;
355 channel->need_reg_write = 1;
357 /* Set the default configuration for the DMA channel */
358 channel->reg_csdp = DMA4_CSDP_DATA_TYPE(0x2)
359 | DMA4_CSDP_SRC_BURST_MODE(0)
360 | DMA4_CSDP_DST_BURST_MODE(0)
361 | DMA4_CSDP_SRC_ENDIANISM(0)
362 | DMA4_CSDP_DST_ENDIANISM(0)
363 | DMA4_CSDP_WRITE_MODE(0)
364 | DMA4_CSDP_SRC_PACKED(0)
365 | DMA4_CSDP_DST_PACKED(0);
367 channel->reg_ccr = DMA4_CCR_DST_ADDRESS_MODE(1)
368 | DMA4_CCR_SRC_ADDRESS_MODE(1)
369 | DMA4_CCR_READ_PRIORITY(0)
370 | DMA4_CCR_WRITE_PRIORITY(0)
371 | DMA4_CCR_SYNC_TRIGGER(0)
372 | DMA4_CCR_FRAME_SYNC(0)
373 | DMA4_CCR_BLOCK_SYNC(0);
375 channel->reg_cicr = DMA4_CICR_TRANS_ERR_IE
376 | DMA4_CICR_SECURE_ERR_IE
377 | DMA4_CICR_SUPERVISOR_ERR_IE
378 | DMA4_CICR_MISALIGNED_ADRS_ERR_IE;
380 /* Clear all the channel registers, this should abort any transaction */
381 for (addr = DMA4_CCR(*ch); addr <= DMA4_COLOR(*ch); addr += 4)
382 ti_sdma_write_4(sc, addr, 0x00000000);
390 * ti_sdma_deactivate_channel - deactivates a channel
391 * @ch: the channel to deactivate
396 * DMA registers protected by internal mutex
399 * EH_HANDLED or EH_NOT_HANDLED
402 ti_sdma_deactivate_channel(unsigned int ch)
404 struct ti_sdma_softc *sc = ti_sdma_sc;
414 /* First check if the channel is currently active */
415 if ((sc->sc_active_channels & (1 << ch)) == 0) {
420 /* Mark the channel as inactive */
421 sc->sc_active_channels &= ~(1 << ch);
423 /* Disable all DMA interrupts for the channel. */
424 ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
426 /* Make sure the DMA transfer is stopped. */
427 ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
429 /* Clear the CSR register and IRQ status register */
430 ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
431 for (j = 0; j < NUM_DMA_IRQS; j++) {
432 ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
435 /* Clear all the channel registers, this should abort any transaction */
436 for (addr = DMA4_CCR(ch); addr <= DMA4_COLOR(ch); addr += 4)
437 ti_sdma_write_4(sc, addr, 0x00000000);
445 * ti_sdma_disable_channel_irq - disables IRQ's on the given channel
446 * @ch: the channel to disable IRQ's on
448 * Disable interrupt generation for the given channel.
451 * DMA registers protected by internal mutex
454 * EH_HANDLED or EH_NOT_HANDLED
457 ti_sdma_disable_channel_irq(unsigned int ch)
459 struct ti_sdma_softc *sc = ti_sdma_sc;
469 if ((sc->sc_active_channels & (1 << ch)) == 0) {
474 /* Disable all the individual error conditions */
475 sc->sc_channel[ch].reg_cicr = 0x0000;
476 ti_sdma_write_4(sc, DMA4_CICR(ch), 0x0000);
478 /* Disable the channel interrupt enable */
479 for (j = 0; j < NUM_DMA_IRQS; j++) {
480 irq_enable = ti_sdma_read_4(sc, DMA4_IRQENABLE_L(j));
481 irq_enable &= ~(1 << ch);
483 ti_sdma_write_4(sc, DMA4_IRQENABLE_L(j), irq_enable);
486 /* Indicate the registers need to be rewritten on the next transaction */
487 sc->sc_channel[ch].need_reg_write = 1;
495 * ti_sdma_disable_channel_irq - enables IRQ's on the given channel
496 * @ch: the channel to enable IRQ's on
497 * @flags: bitmask of interrupt types to enable
499 * Flags can be a bitmask of the following options:
501 * DMA_IRQ_FLAG_HALF_FRAME_COMPL
502 * DMA_IRQ_FLAG_FRAME_COMPL
503 * DMA_IRQ_FLAG_START_LAST_FRAME
504 * DMA_IRQ_FLAG_BLOCK_COMPL
505 * DMA_IRQ_FLAG_ENDOF_PKT
510 * DMA registers protected by internal mutex
513 * EH_HANDLED or EH_NOT_HANDLED
516 ti_sdma_enable_channel_irq(unsigned int ch, uint32_t flags)
518 struct ti_sdma_softc *sc = ti_sdma_sc;
527 if ((sc->sc_active_channels & (1 << ch)) == 0) {
532 /* Always enable the error interrupts if we have interrupts enabled */
533 flags |= DMA4_CICR_TRANS_ERR_IE | DMA4_CICR_SECURE_ERR_IE |
534 DMA4_CICR_SUPERVISOR_ERR_IE | DMA4_CICR_MISALIGNED_ADRS_ERR_IE;
536 sc->sc_channel[ch].reg_cicr = flags;
538 /* Write the values to the register */
539 ti_sdma_write_4(sc, DMA4_CICR(ch), flags);
541 /* Enable the channel interrupt enable */
542 irq_enable = ti_sdma_read_4(sc, DMA4_IRQENABLE_L(0));
543 irq_enable |= (1 << ch);
545 ti_sdma_write_4(sc, DMA4_IRQENABLE_L(0), irq_enable);
547 /* Indicate the registers need to be rewritten on the next transaction */
548 sc->sc_channel[ch].need_reg_write = 1;
556 * ti_sdma_get_channel_status - returns the status of a given channel
557 * @ch: the channel number to get the status of
558 * @status: upon return will contain the status bitmask, see below for possible
568 * DMA_STATUS_TRANS_ERR
569 * DMA_STATUS_SECURE_ERR
570 * DMA_STATUS_SUPERVISOR_ERR
571 * DMA_STATUS_MISALIGNED_ADRS_ERR
572 * DMA_STATUS_DRAIN_END
576 * DMA registers protected by internal mutex
579 * EH_HANDLED or EH_NOT_HANDLED
582 ti_sdma_get_channel_status(unsigned int ch, uint32_t *status)
584 struct ti_sdma_softc *sc = ti_sdma_sc;
593 if ((sc->sc_active_channels & (1 << ch)) == 0) {
600 csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
609 * ti_sdma_start_xfer - starts a DMA transfer
610 * @ch: the channel number to set the endianness of
611 * @src_paddr: the source phsyical address
612 * @dst_paddr: the destination phsyical address
613 * @frmcnt: the number of frames per block
614 * @elmcnt: the number of elements in a frame, an element is either an 8, 16
615 * or 32-bit value as defined by ti_sdma_set_xfer_burst()
619 * DMA registers protected by internal mutex
622 * EH_HANDLED or EH_NOT_HANDLED
625 ti_sdma_start_xfer(unsigned int ch, unsigned int src_paddr,
626 unsigned long dst_paddr,
627 unsigned int frmcnt, unsigned int elmcnt)
629 struct ti_sdma_softc *sc = ti_sdma_sc;
630 struct ti_sdma_channel *channel;
639 if ((sc->sc_active_channels & (1 << ch)) == 0) {
644 channel = &sc->sc_channel[ch];
646 /* a) Write the CSDP register */
647 ti_sdma_write_4(sc, DMA4_CSDP(ch),
648 channel->reg_csdp | DMA4_CSDP_WRITE_MODE(1));
650 /* b) Set the number of element per frame CEN[23:0] */
651 ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
653 /* c) Set the number of frame per block CFN[15:0] */
654 ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
656 /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0] */
657 ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
658 ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
660 /* e) Write the CCR register */
661 ti_sdma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr);
663 /* f) - Set the source element index increment CSEI[15:0] */
664 ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
666 /* - Set the source frame index increment CSFI[15:0] */
667 ti_sdma_write_4(sc, DMA4_CSF(ch), 0x0001);
669 /* - Set the destination element index increment CDEI[15:0]*/
670 ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
672 /* - Set the destination frame index increment CDFI[31:0] */
673 ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001);
675 /* Clear the status register */
676 ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
678 /* Write the start-bit and away we go */
679 ccr = ti_sdma_read_4(sc, DMA4_CCR(ch));
681 ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
683 /* Clear the reg write flag */
684 channel->need_reg_write = 0;
692 * ti_sdma_start_xfer_packet - starts a packet DMA transfer
693 * @ch: the channel number to use for the transfer
694 * @src_paddr: the source physical address
695 * @dst_paddr: the destination physical address
696 * @frmcnt: the number of frames to transfer
697 * @elmcnt: the number of elements in a frame, an element is either an 8, 16
698 * or 32-bit value as defined by ti_sdma_set_xfer_burst()
699 * @pktsize: the number of elements in each transfer packet
701 * The @frmcnt and @elmcnt define the overall number of bytes to transfer,
702 * typically @frmcnt is 1 and @elmcnt contains the total number of elements.
703 * @pktsize is the size of each individual packet, there might be multiple
704 * packets per transfer. i.e. for the following with element size of 32-bits
706 * frmcnt = 1, elmcnt = 512, pktsize = 128
708 * Total transfer bytes = 1 * 512 = 512 elements or 2048 bytes
709 * Packets transferred = 128 / 512 = 4
713 * DMA registers protected by internal mutex
716 * EH_HANDLED or EH_NOT_HANDLED
719 ti_sdma_start_xfer_packet(unsigned int ch, unsigned int src_paddr,
720 unsigned long dst_paddr, unsigned int frmcnt,
721 unsigned int elmcnt, unsigned int pktsize)
723 struct ti_sdma_softc *sc = ti_sdma_sc;
724 struct ti_sdma_channel *channel;
733 if ((sc->sc_active_channels & (1 << ch)) == 0) {
738 channel = &sc->sc_channel[ch];
740 /* a) Write the CSDP register */
741 if (channel->need_reg_write)
742 ti_sdma_write_4(sc, DMA4_CSDP(ch),
743 channel->reg_csdp | DMA4_CSDP_WRITE_MODE(1));
745 /* b) Set the number of elements to transfer CEN[23:0] */
746 ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
748 /* c) Set the number of frames to transfer CFN[15:0] */
749 ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
751 /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0] */
752 ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
753 ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
755 /* e) Write the CCR register */
756 ti_sdma_write_4(sc, DMA4_CCR(ch),
757 channel->reg_ccr | DMA4_CCR_PACKET_TRANS);
759 /* f) - Set the source element index increment CSEI[15:0] */
760 ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
762 /* - Set the packet size, this is dependent on the sync source */
763 if (channel->reg_ccr & DMA4_CCR_SEL_SRC_DST_SYNC(1))
764 ti_sdma_write_4(sc, DMA4_CSF(ch), pktsize);
766 ti_sdma_write_4(sc, DMA4_CDF(ch), pktsize);
768 /* - Set the destination frame index increment CDFI[31:0] */
769 ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
771 /* Clear the status register */
772 ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
774 /* Write the start-bit and away we go */
775 ccr = ti_sdma_read_4(sc, DMA4_CCR(ch));
777 ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
779 /* Clear the reg write flag */
780 channel->need_reg_write = 0;
788 * ti_sdma_stop_xfer - stops any currently active transfers
789 * @ch: the channel number to set the endianness of
791 * This function call is effectively a NOP if no transaction is in progress.
794 * DMA registers protected by internal mutex
797 * EH_HANDLED or EH_NOT_HANDLED
800 ti_sdma_stop_xfer(unsigned int ch)
802 struct ti_sdma_softc *sc = ti_sdma_sc;
811 if ((sc->sc_active_channels & (1 << ch)) == 0) {
816 /* Disable all DMA interrupts for the channel. */
817 ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
819 /* Make sure the DMA transfer is stopped. */
820 ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
822 /* Clear the CSR register and IRQ status register */
823 ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
824 for (j = 0; j < NUM_DMA_IRQS; j++) {
825 ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
828 /* Configuration registers need to be re-written on the next xfer */
829 sc->sc_channel[ch].need_reg_write = 1;
837 * ti_sdma_set_xfer_endianess - sets the endianness of subsequent transfers
838 * @ch: the channel number to set the endianness of
839 * @src: the source endianness (either DMA_ENDIAN_LITTLE or DMA_ENDIAN_BIG)
840 * @dst: the destination endianness (either DMA_ENDIAN_LITTLE or DMA_ENDIAN_BIG)
844 * DMA registers protected by internal mutex
847 * EH_HANDLED or EH_NOT_HANDLED
850 ti_sdma_set_xfer_endianess(unsigned int ch, unsigned int src, unsigned int dst)
852 struct ti_sdma_softc *sc = ti_sdma_sc;
860 if ((sc->sc_active_channels & (1 << ch)) == 0) {
865 sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_ENDIANISM(1);
866 sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_ENDIANISM(src);
868 sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_ENDIANISM(1);
869 sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_ENDIANISM(dst);
871 sc->sc_channel[ch].need_reg_write = 1;
879 * ti_sdma_set_xfer_burst - sets the source and destination element size
880 * @ch: the channel number to set the burst settings of
881 * @src: the source endianness (either DMA_BURST_NONE, DMA_BURST_16, DMA_BURST_32
883 * @dst: the destination endianness (either DMA_BURST_NONE, DMA_BURST_16,
884 * DMA_BURST_32 or DMA_BURST_64)
886 * This function sets the size of the elements for all subsequent transfers.
889 * DMA registers protected by internal mutex
892 * EH_HANDLED or EH_NOT_HANDLED
895 ti_sdma_set_xfer_burst(unsigned int ch, unsigned int src, unsigned int dst)
897 struct ti_sdma_softc *sc = ti_sdma_sc;
905 if ((sc->sc_active_channels & (1 << ch)) == 0) {
910 sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_BURST_MODE(0x3);
911 sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_BURST_MODE(src);
913 sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_BURST_MODE(0x3);
914 sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_BURST_MODE(dst);
916 sc->sc_channel[ch].need_reg_write = 1;
924 * ti_sdma_set_xfer_data_type - driver attach function
925 * @ch: the channel number to set the endianness of
926 * @type: the xfer data type (either DMA_DATA_8BITS_SCALAR, DMA_DATA_16BITS_SCALAR
927 * or DMA_DATA_32BITS_SCALAR)
931 * DMA registers protected by internal mutex
934 * EH_HANDLED or EH_NOT_HANDLED
937 ti_sdma_set_xfer_data_type(unsigned int ch, unsigned int type)
939 struct ti_sdma_softc *sc = ti_sdma_sc;
947 if ((sc->sc_active_channels & (1 << ch)) == 0) {
952 sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DATA_TYPE(0x3);
953 sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DATA_TYPE(type);
955 sc->sc_channel[ch].need_reg_write = 1;
963 * ti_sdma_set_callback - driver attach function
964 * @dev: dma device handle
969 * DMA registers protected by internal mutex
972 * EH_HANDLED or EH_NOT_HANDLED
975 ti_sdma_set_callback(unsigned int ch,
976 void (*callback)(unsigned int ch, uint32_t status, void *data),
979 struct ti_sdma_softc *sc = ti_sdma_sc;
987 if ((sc->sc_active_channels & (1 << ch)) == 0) {
992 sc->sc_channel[ch].callback = callback;
993 sc->sc_channel[ch].callback_data = data;
995 sc->sc_channel[ch].need_reg_write = 1;
1003 * ti_sdma_sync_params - sets channel sync settings
1004 * @ch: the channel number to set the sync on
1005 * @trigger: the number of the sync trigger, this depends on what other H/W
1006 * module is triggering/receiving the DMA transactions
1007 * @mode: flags describing the sync mode to use, it may have one or more of
1008 * the following bits set; TI_SDMA_SYNC_FRAME,
1009 * TI_SDMA_SYNC_BLOCK, TI_SDMA_SYNC_TRIG_ON_SRC.
1014 * DMA registers protected by internal mutex
1017 * EH_HANDLED or EH_NOT_HANDLED
1020 ti_sdma_sync_params(unsigned int ch, unsigned int trigger, unsigned int mode)
1022 struct ti_sdma_softc *sc = ti_sdma_sc;
1031 if ((sc->sc_active_channels & (1 << ch)) == 0) {
1036 ccr = sc->sc_channel[ch].reg_ccr;
1038 ccr &= ~DMA4_CCR_SYNC_TRIGGER(0x7F);
1039 ccr |= DMA4_CCR_SYNC_TRIGGER(trigger + 1);
1041 if (mode & TI_SDMA_SYNC_FRAME)
1042 ccr |= DMA4_CCR_FRAME_SYNC(1);
1044 ccr &= ~DMA4_CCR_FRAME_SYNC(1);
1046 if (mode & TI_SDMA_SYNC_BLOCK)
1047 ccr |= DMA4_CCR_BLOCK_SYNC(1);
1049 ccr &= ~DMA4_CCR_BLOCK_SYNC(1);
1051 if (mode & TI_SDMA_SYNC_TRIG_ON_SRC)
1052 ccr |= DMA4_CCR_SEL_SRC_DST_SYNC(1);
1054 ccr &= ~DMA4_CCR_SEL_SRC_DST_SYNC(1);
1056 sc->sc_channel[ch].reg_ccr = ccr;
1058 sc->sc_channel[ch].need_reg_write = 1;
1066 * ti_sdma_set_addr_mode - driver attach function
1067 * @ch: the channel number to set the endianness of
1068 * @rd_mode: the xfer source addressing mode (either DMA_ADDR_CONSTANT,
1069 * DMA_ADDR_POST_INCREMENT, DMA_ADDR_SINGLE_INDEX or
1070 * DMA_ADDR_DOUBLE_INDEX)
1071 * @wr_mode: the xfer destination addressing mode (either DMA_ADDR_CONSTANT,
1072 * DMA_ADDR_POST_INCREMENT, DMA_ADDR_SINGLE_INDEX or
1073 * DMA_ADDR_DOUBLE_INDEX)
1077 * DMA registers protected by internal mutex
1080 * EH_HANDLED or EH_NOT_HANDLED
1083 ti_sdma_set_addr_mode(unsigned int ch, unsigned int src_mode,
1084 unsigned int dst_mode)
1086 struct ti_sdma_softc *sc = ti_sdma_sc;
1095 if ((sc->sc_active_channels & (1 << ch)) == 0) {
1100 ccr = sc->sc_channel[ch].reg_ccr;
1102 ccr &= ~DMA4_CCR_SRC_ADDRESS_MODE(0x3);
1103 ccr |= DMA4_CCR_SRC_ADDRESS_MODE(src_mode);
1105 ccr &= ~DMA4_CCR_DST_ADDRESS_MODE(0x3);
1106 ccr |= DMA4_CCR_DST_ADDRESS_MODE(dst_mode);
1108 sc->sc_channel[ch].reg_ccr = ccr;
1110 sc->sc_channel[ch].need_reg_write = 1;
1118 * ti_sdma_probe - driver probe function
1119 * @dev: dma device handle
1127 ti_sdma_probe(device_t dev)
1130 if (!ofw_bus_status_okay(dev))
1133 if (!ofw_bus_is_compatible(dev, "ti,omap4430-sdma"))
1136 device_set_desc(dev, "TI sDMA Controller");
1141 * ti_sdma_attach - driver attach function
1142 * @dev: dma device handle
1144 * Initialises memory mapping/pointers to the DMA register set and requests
1145 * IRQs. This is effectively the setup function for the driver.
1148 * 0 on success or a negative error code failure.
1151 ti_sdma_attach(device_t dev)
1153 struct ti_sdma_softc *sc = device_get_softc(dev);
1154 unsigned int timeout;
1160 /* Setup the basics */
1163 /* No channels active at the moment */
1164 sc->sc_active_channels = 0x00000000;
1166 /* Mutex to protect the shared data structures */
1167 TI_SDMA_LOCK_INIT(sc);
1169 /* Get the memory resource for the register mapping */
1171 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1172 if (sc->sc_mem_res == NULL)
1173 panic("%s: Cannot map registers", device_get_name(dev));
1175 /* Enable the interface and functional clocks */
1176 ti_prcm_clk_enable(SDMA_CLK);
1178 /* Read the sDMA revision register and sanity check it's known */
1179 sc->sc_hw_rev = ti_sdma_read_4(sc, DMA4_REVISION);
1180 device_printf(dev, "sDMA revision %08x\n", sc->sc_hw_rev);
1182 if (!ti_sdma_is_omap4_rev(sc) && !ti_sdma_is_omap3_rev(sc)) {
1183 device_printf(sc->sc_dev, "error - unknown sDMA H/W revision\n");
1187 /* Disable all interrupts */
1188 for (i = 0; i < NUM_DMA_IRQS; i++) {
1189 ti_sdma_write_4(sc, DMA4_IRQENABLE_L(i), 0x00000000);
1192 /* Soft-reset is only supported on pre-OMAP44xx devices */
1193 if (ti_sdma_is_omap3_rev(sc)) {
1196 ti_sdma_write_4(sc, DMA4_OCP_SYSCONFIG, 0x0002);
1198 /* Set the timeout to 100ms*/
1199 timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
1201 /* Wait for DMA reset to complete */
1202 while ((ti_sdma_read_4(sc, DMA4_SYSSTATUS) & 0x1) == 0x0) {
1204 /* Sleep for a tick */
1205 pause("DMARESET", 1);
1207 if (timeout-- == 0) {
1208 device_printf(sc->sc_dev, "sDMA reset operation timed out\n");
1215 * Install interrupt handlers for the for possible interrupts. Any channel
1216 * can trip one of the four IRQs
1219 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1220 RF_ACTIVE | RF_SHAREABLE);
1221 if (sc->sc_irq_res == NULL)
1222 panic("Unable to setup the dma irq handler.\n");
1224 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
1225 NULL, ti_sdma_intr, NULL, &ihl);
1227 panic("%s: Cannot register IRQ", device_get_name(dev));
1229 /* Store the DMA structure globally ... this driver should never be unloaded */
1235 static device_method_t ti_sdma_methods[] = {
1236 DEVMETHOD(device_probe, ti_sdma_probe),
1237 DEVMETHOD(device_attach, ti_sdma_attach),
1241 static driver_t ti_sdma_driver = {
1244 sizeof(struct ti_sdma_softc),
1246 static devclass_t ti_sdma_devclass;
1248 DRIVER_MODULE(ti_sdma, simplebus, ti_sdma_driver, ti_sdma_devclass, 0, 0);
1249 MODULE_DEPEND(ti_sdma, ti_prcm, 1, 1, 1);