2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/intr.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/spibus/spi.h>
49 #include <dev/spibus/spibusvar.h>
51 #include <arm/ti/ti_prcm.h>
52 #include <arm/ti/ti_hwmods.h>
53 #include <arm/ti/ti_spireg.h>
54 #include <arm/ti/ti_spivar.h>
56 #include "spibus_if.h"
58 static void ti_spi_intr(void *);
59 static int ti_spi_detach(device_t);
63 #define IRQSTATUSBITS \
64 "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \
65 "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \
66 "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \
69 "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \
70 "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG"
72 "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF"
73 #define MODULCTRLBITS \
74 "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA"
79 ti_spi_printr(device_t dev)
81 int clk, conf, ctrl, div, i, j, wl;
82 struct ti_spi_softc *sc;
85 sc = device_get_softc(dev);
86 reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG);
87 device_printf(dev, "SYSCONFIG: %#x\n", reg);
88 reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS);
89 device_printf(dev, "SYSSTATUS: %#x\n", reg);
90 reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS);
91 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS);
92 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
93 device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS);
94 reg = TI_SPI_READ(sc, MCSPI_MODULCTRL);
95 device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS);
96 for (i = 0; i < sc->sc_numcs; i++) {
97 ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i));
98 conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i));
99 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS);
100 if (conf & MCSPI_CONF_CLKG) {
101 div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK;
102 div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4;
105 j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK;
109 clk = TI_SPI_GCLK / div;
110 wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1;
111 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk);
112 reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i));
113 device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS);
114 device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS);
116 reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL);
117 device_printf(dev, "XFERLEVEL: %#x\n", reg);
122 ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq)
124 uint32_t clkdiv, conf, div, extclk, reg;
126 clkdiv = TI_SPI_GCLK / freq;
127 if (clkdiv > MCSPI_EXTCLK_MSK) {
131 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) {
135 conf = clkdiv << MCSPI_CONF_CLK_SHIFT;
137 extclk = clkdiv >> 4;
138 clkdiv &= MCSPI_CONF_CLK_MSK;
139 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT;
142 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch));
143 reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT);
144 reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT;
145 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg);
147 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch));
148 reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT);
149 TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf);
153 ti_spi_probe(device_t dev)
156 if (!ofw_bus_status_okay(dev))
158 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi"))
161 device_set_desc(dev, "TI McSPI controller");
163 return (BUS_PROBE_DEFAULT);
167 ti_spi_attach(device_t dev)
169 int clk_id, err, i, rid, timeout;
170 struct ti_spi_softc *sc;
173 sc = device_get_softc(dev);
177 * Get the MMCHS device id from FDT. If it's not there use the newbus
178 * unit number (which will work as long as the devices are in order and
179 * none are skipped in the fdt). Note that this is a property we made
180 * up and added in freebsd, it doesn't exist in the published bindings.
182 clk_id = ti_hwmods_get_clock(dev);
183 if (clk_id == INVALID_CLK_IDENT) {
185 "failed to get clock based on hwmods property\n");
189 /* Activate the McSPI module. */
190 err = ti_prcm_clk_enable(clk_id);
192 device_printf(dev, "Error: failed to activate source clock\n");
196 /* Get the number of available channels. */
197 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs",
198 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) {
203 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
205 if (!sc->sc_mem_res) {
206 device_printf(dev, "cannot allocate memory window\n");
210 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
211 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
214 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
216 if (!sc->sc_irq_res) {
217 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
218 device_printf(dev, "cannot allocate interrupt\n");
222 /* Hook up our interrupt handler. */
223 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
224 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) {
225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
226 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
227 device_printf(dev, "cannot setup the interrupt handler\n");
231 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF);
233 /* Issue a softreset to the controller */
234 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET);
236 while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) &
237 MCSPI_SYSSTATUS_RESETDONE)) {
238 if (--timeout == 0) {
240 "Error: Controller reset operation timed out\n");
247 /* Print the McSPI module revision. */
248 rev = TI_SPI_READ(sc, MCSPI_REVISION);
250 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
251 (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK,
252 (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK,
253 (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK,
254 (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK,
255 (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK,
256 (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK);
258 /* Set Master mode, single channel. */
259 TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE);
261 /* Clear pending interrupts and disable interrupts. */
262 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0);
263 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff);
265 for (i = 0; i < sc->sc_numcs; i++) {
267 * Default to SPI mode 0, CS active low, 8 bits word length and
270 TI_SPI_WRITE(sc, MCSPI_CONF_CH(i),
271 MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL |
272 (8 - 1) << MCSPI_CONF_WL_SHIFT);
273 /* Set initial clock - 500kHz. */
274 ti_spi_set_clock(sc, i, 500000);
281 device_add_child(dev, "spibus", -1);
283 return (bus_generic_attach(dev));
287 ti_spi_detach(device_t dev)
289 struct ti_spi_softc *sc;
291 sc = device_get_softc(dev);
293 /* Clear pending interrupts and disable interrupts. */
294 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0);
295 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff);
297 /* Reset controller. */
298 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET);
300 bus_generic_detach(dev);
302 mtx_destroy(&sc->sc_mtx);
304 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
306 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
308 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
314 ti_spi_fill_fifo(struct ti_spi_softc *sc)
317 struct spi_command *cmd;
322 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl);
323 while (bytes-- > 0) {
324 data = (uint8_t *)cmd->tx_cmd;
325 written = sc->sc_written++;
326 if (written >= cmd->tx_cmd_sz) {
327 data = (uint8_t *)cmd->tx_data;
328 written -= cmd->tx_cmd_sz;
330 if (sc->sc_fifolvl == 1) {
333 while (--timeout > 0 && (TI_SPI_READ(sc,
334 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) {
340 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]);
347 ti_spi_drain_fifo(struct ti_spi_softc *sc)
350 struct spi_command *cmd;
355 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl);
356 while (bytes-- > 0) {
357 data = (uint8_t *)cmd->rx_cmd;
358 read = sc->sc_read++;
359 if (read >= cmd->rx_cmd_sz) {
360 data = (uint8_t *)cmd->rx_data;
361 read -= cmd->rx_cmd_sz;
363 if (sc->sc_fifolvl == 1) {
366 while (--timeout > 0 && (TI_SPI_READ(sc,
367 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) {
373 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs));
380 ti_spi_intr(void *arg)
383 struct ti_spi_softc *sc;
387 sc = (struct ti_spi_softc *)arg;
389 status = TI_SPI_READ(sc, MCSPI_IRQSTATUS);
392 * No new TX_empty or RX_full event will be asserted while the CPU has
393 * not performed the number of writes or reads defined by
394 * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility
395 * of CPU perform the right number of writes and reads.
397 if (status & MCSPI_IRQ_TX0_EMPTY)
398 ti_spi_fill_fifo(sc);
399 if (status & MCSPI_IRQ_RX0_FULL)
400 ti_spi_drain_fifo(sc);
402 if (status & MCSPI_IRQ_EOW)
405 /* Clear interrupt status. */
406 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status);
408 /* Check for end of transfer. */
409 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
410 sc->sc_flags |= TI_SPI_DONE;
418 ti_spi_pio_transfer(struct ti_spi_softc *sc)
421 while (sc->sc_len - sc->sc_written > 0) {
422 if (ti_spi_fill_fifo(sc) == -1)
424 if (ti_spi_drain_fifo(sc) == -1)
432 ti_spi_gcd(int a, int b)
436 while ((m = a % b) != 0) {
445 ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
448 struct ti_spi_softc *sc;
449 uint32_t clockhz, cs, mode, reg;
451 sc = device_get_softc(dev);
453 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
454 ("TX/RX command sizes should be equal"));
455 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
456 ("TX/RX data sizes should be equal"));
458 /* Get the proper chip select for this child. */
459 spibus_get_cs(child, &cs);
460 spibus_get_clock(child, &clockhz);
461 spibus_get_mode(child, &mode);
463 cs &= ~SPIBUS_CS_HIGH;
465 if (cs > sc->sc_numcs) {
466 device_printf(dev, "Invalid chip select %d requested by %s\n",
467 cs, device_get_nameunit(child));
473 device_printf(dev, "Invalid mode %d requested by %s\n", mode,
474 device_get_nameunit(child));
480 /* If the controller is in use wait until it is available. */
481 while (sc->sc_flags & TI_SPI_BUSY)
482 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0);
484 /* Now we have control over SPI controller. */
485 sc->sc_flags = TI_SPI_BUSY;
487 /* Save the SPI command data. */
492 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
493 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ);
494 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff)
495 sc->sc_fifolvl = 1; /* FIFO disabled. */
496 /* Disable FIFO for now. */
499 /* Set the bus frequency. */
500 ti_spi_set_clock(sc, sc->sc_cs, clockhz);
502 /* Disable the FIFO. */
503 TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
505 /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */
506 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
507 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL |
508 MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS |
509 MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
510 MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
511 reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
512 reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
513 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
516 /* Enable channel interrupts. */
517 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
519 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg);
522 /* Start the transfer. */
523 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));
524 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE);
527 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
528 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE);
531 if (sc->sc_fifolvl == 1)
532 err = ti_spi_pio_transfer(sc);
535 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
536 reg &= ~MCSPI_CONF_FORCE;
537 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
540 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
542 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg);
543 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf);
545 /* Disable the SPI channel. */
546 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));
547 reg &= ~MCSPI_CTRL_ENABLE;
548 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg);
551 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
552 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW);
553 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
555 /* Release the controller and wakeup the next thread waiting for it. */
564 ti_spi_get_node(device_t bus, device_t dev)
567 /* Share controller node with spibus. */
568 return (ofw_bus_get_node(bus));
571 static device_method_t ti_spi_methods[] = {
572 /* Device interface */
573 DEVMETHOD(device_probe, ti_spi_probe),
574 DEVMETHOD(device_attach, ti_spi_attach),
575 DEVMETHOD(device_detach, ti_spi_detach),
578 DEVMETHOD(spibus_transfer, ti_spi_transfer),
580 /* ofw_bus interface */
581 DEVMETHOD(ofw_bus_get_node, ti_spi_get_node),
586 static devclass_t ti_spi_devclass;
588 static driver_t ti_spi_driver = {
591 sizeof(struct ti_spi_softc),
594 DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0);