2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/intr.h>
45 #include <dev/fdt/fdt_common.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/spibus/spi.h>
50 #include <dev/spibus/spibusvar.h>
52 #include <arm/ti/ti_prcm.h>
53 #include <arm/ti/ti_hwmods.h>
54 #include <arm/ti/ti_spireg.h>
55 #include <arm/ti/ti_spivar.h>
57 #include "spibus_if.h"
59 static void ti_spi_intr(void *);
60 static int ti_spi_detach(device_t);
64 #define IRQSTATUSBITS \
65 "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \
66 "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \
67 "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \
70 "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \
71 "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG"
73 "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF"
74 #define MODULCTRLBITS \
75 "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA"
80 ti_spi_printr(device_t dev)
82 int clk, conf, ctrl, div, i, j, wl;
83 struct ti_spi_softc *sc;
86 sc = device_get_softc(dev);
87 reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG);
88 device_printf(dev, "SYSCONFIG: %#x\n", reg);
89 reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS);
90 device_printf(dev, "SYSSTATUS: %#x\n", reg);
91 reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS);
92 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS);
93 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
94 device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS);
95 reg = TI_SPI_READ(sc, MCSPI_MODULCTRL);
96 device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS);
97 for (i = 0; i < sc->sc_numcs; i++) {
98 ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i));
99 conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i));
100 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS);
101 if (conf & MCSPI_CONF_CLKG) {
102 div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK;
103 div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4;
106 j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK;
110 clk = TI_SPI_GCLK / div;
111 wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1;
112 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk);
113 reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i));
114 device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS);
115 device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS);
117 reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL);
118 device_printf(dev, "XFERLEVEL: %#x\n", reg);
123 ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq)
125 uint32_t clkdiv, conf, div, extclk, reg;
127 clkdiv = TI_SPI_GCLK / freq;
128 if (clkdiv > MCSPI_EXTCLK_MSK) {
132 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) {
136 conf = clkdiv << MCSPI_CONF_CLK_SHIFT;
138 extclk = clkdiv >> 4;
139 clkdiv &= MCSPI_CONF_CLK_MSK;
140 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT;
143 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch));
144 reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT);
145 reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT;
146 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg);
148 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch));
149 reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT);
150 TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf);
154 ti_spi_probe(device_t dev)
157 if (!ofw_bus_status_okay(dev))
159 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi"))
162 device_set_desc(dev, "TI McSPI controller");
164 return (BUS_PROBE_DEFAULT);
168 ti_spi_attach(device_t dev)
170 int clk_id, err, i, rid, timeout;
171 struct ti_spi_softc *sc;
174 sc = device_get_softc(dev);
178 * Get the MMCHS device id from FDT. If it's not there use the newbus
179 * unit number (which will work as long as the devices are in order and
180 * none are skipped in the fdt). Note that this is a property we made
181 * up and added in freebsd, it doesn't exist in the published bindings.
183 clk_id = ti_hwmods_get_clock(dev);
184 if (clk_id == INVALID_CLK_IDENT) {
186 "failed to get clock based on hwmods property\n");
190 /* Activate the McSPI module. */
191 err = ti_prcm_clk_enable(clk_id);
193 device_printf(dev, "Error: failed to activate source clock\n");
197 /* Get the number of available channels. */
198 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs",
199 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) {
204 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
206 if (!sc->sc_mem_res) {
207 device_printf(dev, "cannot allocate memory window\n");
211 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
212 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
215 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
217 if (!sc->sc_irq_res) {
218 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
219 device_printf(dev, "cannot allocate interrupt\n");
223 /* Hook up our interrupt handler. */
224 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
225 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) {
226 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
227 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
228 device_printf(dev, "cannot setup the interrupt handler\n");
232 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF);
234 /* Issue a softreset to the controller */
235 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET);
237 while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) &
238 MCSPI_SYSSTATUS_RESETDONE)) {
239 if (--timeout == 0) {
241 "Error: Controller reset operation timed out\n");
248 /* Print the McSPI module revision. */
249 rev = TI_SPI_READ(sc, MCSPI_REVISION);
251 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
252 (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK,
253 (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK,
254 (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK,
255 (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK,
256 (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK,
257 (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK);
259 /* Set Master mode, single channel. */
260 TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE);
262 /* Clear pending interrupts and disable interrupts. */
263 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0);
264 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff);
266 for (i = 0; i < sc->sc_numcs; i++) {
268 * Default to SPI mode 0, CS active low, 8 bits word length and
271 TI_SPI_WRITE(sc, MCSPI_CONF_CH(i),
272 MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL |
273 (8 - 1) << MCSPI_CONF_WL_SHIFT);
274 /* Set initial clock - 500kHz. */
275 ti_spi_set_clock(sc, i, 500000);
282 device_add_child(dev, "spibus", -1);
284 return (bus_generic_attach(dev));
288 ti_spi_detach(device_t dev)
290 struct ti_spi_softc *sc;
292 sc = device_get_softc(dev);
294 /* Clear pending interrupts and disable interrupts. */
295 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0);
296 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff);
298 /* Reset controller. */
299 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET);
301 bus_generic_detach(dev);
303 mtx_destroy(&sc->sc_mtx);
305 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
307 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
309 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
315 ti_spi_fill_fifo(struct ti_spi_softc *sc)
318 struct spi_command *cmd;
323 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl);
324 while (bytes-- > 0) {
325 data = (uint8_t *)cmd->tx_cmd;
326 written = sc->sc_written++;
327 if (written >= cmd->tx_cmd_sz) {
328 data = (uint8_t *)cmd->tx_data;
329 written -= cmd->tx_cmd_sz;
331 if (sc->sc_fifolvl == 1) {
334 while (--timeout > 0 && (TI_SPI_READ(sc,
335 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) {
341 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]);
348 ti_spi_drain_fifo(struct ti_spi_softc *sc)
351 struct spi_command *cmd;
356 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl);
357 while (bytes-- > 0) {
358 data = (uint8_t *)cmd->rx_cmd;
359 read = sc->sc_read++;
360 if (read >= cmd->rx_cmd_sz) {
361 data = (uint8_t *)cmd->rx_data;
362 read -= cmd->rx_cmd_sz;
364 if (sc->sc_fifolvl == 1) {
367 while (--timeout > 0 && (TI_SPI_READ(sc,
368 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) {
374 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs));
381 ti_spi_intr(void *arg)
384 struct ti_spi_softc *sc;
388 sc = (struct ti_spi_softc *)arg;
390 status = TI_SPI_READ(sc, MCSPI_IRQSTATUS);
393 * No new TX_empty or RX_full event will be asserted while the CPU has
394 * not performed the number of writes or reads defined by
395 * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility
396 * of CPU perform the right number of writes and reads.
398 if (status & MCSPI_IRQ_TX0_EMPTY)
399 ti_spi_fill_fifo(sc);
400 if (status & MCSPI_IRQ_RX0_FULL)
401 ti_spi_drain_fifo(sc);
403 if (status & MCSPI_IRQ_EOW)
406 /* Clear interrupt status. */
407 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status);
409 /* Check for end of transfer. */
410 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
411 sc->sc_flags |= TI_SPI_DONE;
419 ti_spi_pio_transfer(struct ti_spi_softc *sc)
422 while (sc->sc_len - sc->sc_written > 0) {
423 if (ti_spi_fill_fifo(sc) == -1)
425 if (ti_spi_drain_fifo(sc) == -1)
433 ti_spi_gcd(int a, int b)
437 while ((m = a % b) != 0) {
446 ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
449 struct ti_spi_softc *sc;
452 sc = device_get_softc(dev);
454 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
455 ("TX/RX command sizes should be equal"));
456 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
457 ("TX/RX data sizes should be equal"));
459 /* Get the proper chip select for this child. */
460 spibus_get_cs(child, &cs);
461 if (cs < 0 || cs > sc->sc_numcs) {
462 device_printf(dev, "Invalid chip select %d requested by %s\n",
463 cs, device_get_nameunit(child));
469 /* If the controller is in use wait until it is available. */
470 while (sc->sc_flags & TI_SPI_BUSY)
471 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0);
473 /* Now we have control over SPI controller. */
474 sc->sc_flags = TI_SPI_BUSY;
476 /* Save the SPI command data. */
481 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
482 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ);
483 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff)
484 sc->sc_fifolvl = 1; /* FIFO disabled. */
485 /* Disable FIFO for now. */
488 /* Use a safe clock - 500kHz. */
489 ti_spi_set_clock(sc, sc->sc_cs, 500000);
491 /* Disable the FIFO. */
492 TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
494 /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */
495 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
496 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL |
497 MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS |
498 MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
499 MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
500 reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
501 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
504 /* Enable channel interrupts. */
505 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
507 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg);
510 /* Start the transfer. */
511 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));
512 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE);
515 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
516 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE);
519 if (sc->sc_fifolvl == 1)
520 err = ti_spi_pio_transfer(sc);
523 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
524 reg &= ~MCSPI_CONF_FORCE;
525 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
528 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
530 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg);
531 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf);
533 /* Disable the SPI channel. */
534 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));
535 reg &= ~MCSPI_CTRL_ENABLE;
536 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg);
539 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
540 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW);
541 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
543 /* Release the controller and wakeup the next thread waiting for it. */
552 ti_spi_get_node(device_t bus, device_t dev)
555 /* Share controller node with spibus. */
556 return (ofw_bus_get_node(bus));
559 static device_method_t ti_spi_methods[] = {
560 /* Device interface */
561 DEVMETHOD(device_probe, ti_spi_probe),
562 DEVMETHOD(device_attach, ti_spi_attach),
563 DEVMETHOD(device_detach, ti_spi_detach),
566 DEVMETHOD(spibus_transfer, ti_spi_transfer),
568 /* ofw_bus interface */
569 DEVMETHOD(ofw_bus_get_node, ti_spi_get_node),
574 static devclass_t ti_spi_devclass;
576 static driver_t ti_spi_driver = {
579 sizeof(struct ti_spi_softc),
582 DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0);