2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #define TI_SPI_GCLK 48000000U
31 #define TI_SPI_FIFOSZ 32
32 #define MCSPI_REVISION 0x0
33 #define MCSPI_REVISION_SCHEME_SHIFT 30
34 #define MCSPI_REVISION_SCHEME_MSK 0x3
35 #define MCSPI_REVISION_FUNC_SHIFT 16
36 #define MCSPI_REVISION_FUNC_MSK 0xfff
37 #define MCSPI_REVISION_RTL_SHIFT 11
38 #define MCSPI_REVISION_RTL_MSK 0x1f
39 #define MCSPI_REVISION_MAJOR_SHIFT 8
40 #define MCSPI_REVISION_MAJOR_MSK 0x7
41 #define MCSPI_REVISION_CUSTOM_SHIFT 6
42 #define MCSPI_REVISION_CUSTOM_MSK 0x3
43 #define MCSPI_REVISION_MINOR_SHIFT 0
44 #define MCSPI_REVISION_MINOR_MSK 0x3f
45 #define MCSPI_SYSCONFIG 0x110
46 #define MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
47 #define MCSPI_SYSSTATUS 0x114
48 #define MCSPI_SYSSTATUS_RESETDONE (1 << 0)
49 #define MCSPI_MODULCTRL 0x128
50 #define MCSPI_MODULCTRL_SLAVE (1 << 2)
51 #define MCSPI_MODULCTRL_SINGLE (1 << 0)
52 #define MCSPI_IRQSTATUS 0x118
53 #define MCSPI_IRQENABLE 0x11c
54 #define MCSPI_IRQ_EOW (1 << 17)
55 #define MCSPI_IRQ_RX0_OVERFLOW (1 << 3)
56 #define MCSPI_IRQ_RX0_FULL (1 << 2)
57 #define MCSPI_IRQ_TX0_UNDERFLOW (1 << 1)
58 #define MCSPI_IRQ_TX0_EMPTY (1 << 0)
59 #define MCSPI_CONF_CH(_c) (0x12c + 0x14 * (_c))
60 #define MCSPI_CONF_CLKG (1 << 29)
61 #define MCSPI_CONF_FFER (1 << 28)
62 #define MCSPI_CONF_FFEW (1 << 27)
63 #define MCSPI_CONF_SBPOL (1 << 24)
64 #define MCSPI_CONF_SBE (1 << 23)
65 #define MCSPI_CONF_FORCE (1 << 20)
66 #define MCSPI_CONF_TURBO (1 << 19)
67 #define MCSPI_CONF_IS (1 << 18)
68 #define MCSPI_CONF_DPE1 (1 << 17)
69 #define MCSPI_CONF_DPE0 (1 << 16)
70 #define MCSPI_CONF_DMAR (1 << 15)
71 #define MCSPI_CONF_DMAW (1 << 14)
72 #define MCSPI_CONF_WL_MSK 0x1f
73 #define MCSPI_CONF_WL_SHIFT 7
74 #define MCSPI_CONF_WL8BITS (7 << MCSPI_CONF_WL_SHIFT)
75 #define MCSPI_CONF_EPOL (1 << 6)
76 #define MCSPI_CONF_CLK_MSK 0xf
77 #define MCSPI_CONF_CLK_SHIFT 2
78 #define MCSPI_CONF_POL (1 << 1)
79 #define MCSPI_CONF_PHA (1 << 0)
80 #define MCSPI_STAT_CH(_c) (0x130 + 0x14 * (_c))
81 #define MCSPI_STAT_TXFFF (1 << 4)
82 #define MCSPI_STAT_TXS (1 << 1)
83 #define MCSPI_STAT_RXS (1 << 0)
84 #define MCSPI_CTRL_CH(_c) (0x134 + 0x14 * (_c))
85 #define MCSPI_EXTCLK_MSK 0xfff
86 #define MCSPI_CTRL_EXTCLK_MSK 0xff
87 #define MCSPI_CTRL_EXTCLK_SHIFT 8
88 #define MCSPI_CTRL_ENABLE (1 << 0)
89 #define MCSPI_TX_CH(_c) (0x138 + 0x14 * (_c))
90 #define MCSPI_RX_CH(_c) (0x13c + 0x14 * (_c))
91 #define MCSPI_XFERLEVEL 0x17c
92 #define MCSPI_XFERLEVEL_AFL(_a) (((_a) >> 8) & 0xff)
93 #define MCSPI_XFERLEVEL_AEL(_a) (((_a) >> 0) & 0xff)
95 #endif /* _TI_SPIREG_H_ */