2 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org>
4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/queue.h>
37 #include <sys/resource.h>
38 #include <machine/bus.h>
40 #include <vm/vm_extern.h>
41 #include <vm/vm_kern.h>
44 #include <dev/fdt/simplebus.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/extres/clk/clk.h>
51 #include <arm/ti/ti_sysc.h>
52 #include <arm/ti/clk/clock_common.h>
57 #define DPRINTF(dev, msg...) device_printf(dev, msg)
59 #define DPRINTF(dev, msg...)
62 /* Documentation/devicetree/bindings/bus/ti-sysc.txt
64 * Documentation/devicetree/clock/clock-bindings.txt
65 * Defines phandle + optional pair
66 * Documentation/devicetree/clock/ti-clkctl.txt
69 static int ti_sysc_probe(device_t dev);
70 static int ti_sysc_attach(device_t dev);
71 static int ti_sysc_detach(device_t dev);
73 #define TI_SYSC_DRA7_MCAN 15
74 #define TI_SYSC_USB_HOST_FS 14
75 #define TI_SYSC_DRA7_MCASP 13
76 #define TI_SYSC_MCASP 12
77 #define TI_SYSC_OMAP_AES 11
78 #define TI_SYSC_OMAP3_SHAM 10
79 #define TI_SYSC_OMAP4_SR 9
80 #define TI_SYSC_OMAP3630_SR 8
81 #define TI_SYSC_OMAP3430_SR 7
82 #define TI_SYSC_OMAP4_TIMER 6
83 #define TI_SYSC_OMAP2_TIMER 5
84 /* Above needs special workarounds */
85 #define TI_SYSC_OMAP4_SIMPLE 4
86 #define TI_SYSC_OMAP4 3
87 #define TI_SYSC_OMAP2 2
91 static struct ofw_compat_data compat_data[] = {
92 { "ti,sysc-dra7-mcan", TI_SYSC_DRA7_MCAN },
93 { "ti,sysc-usb-host-fs", TI_SYSC_USB_HOST_FS },
94 { "ti,sysc-dra7-mcasp", TI_SYSC_DRA7_MCASP },
95 { "ti,sysc-mcasp", TI_SYSC_MCASP },
96 { "ti,sysc-omap-aes", TI_SYSC_OMAP_AES },
97 { "ti,sysc-omap3-sham", TI_SYSC_OMAP3_SHAM },
98 { "ti,sysc-omap4-sr", TI_SYSC_OMAP4_SR },
99 { "ti,sysc-omap3630-sr", TI_SYSC_OMAP3630_SR },
100 { "ti,sysc-omap3430-sr", TI_SYSC_OMAP3430_SR },
101 { "ti,sysc-omap4-timer", TI_SYSC_OMAP4_TIMER },
102 { "ti,sysc-omap2-timer", TI_SYSC_OMAP2_TIMER },
103 /* Above needs special workarounds */
104 { "ti,sysc-omap4-simple", TI_SYSC_OMAP4_SIMPLE },
105 { "ti,sysc-omap4", TI_SYSC_OMAP4 },
106 { "ti,sysc-omap2", TI_SYSC_OMAP2 },
107 { "ti,sysc", TI_SYSC },
108 { NULL, TI_SYSC_END }
111 /* reg-names can be "rev", "sysc" and "syss" */
112 static const char * reg_names[] = { "rev", "sysc", "syss" };
118 /* master idle / slave idle mode defined in 8.1.3.2.1 / 8.1.3.2.2 */
119 #include <dt-bindings/bus/ti-sysc.h>
120 #define SYSC_IDLE_MAX 4
128 TAILQ_ENTRY(clk_list) next;
132 struct ti_sysc_softc {
133 struct simplebus_softc sc;
139 struct sysc_reg reg[REG_MAX];
140 /* Offset from host base address */
141 uint64_t offset_reg[REG_MAX];
143 uint32_t ti_sysc_mask;
144 int32_t ti_sysc_midle[SYSC_IDLE_MAX];
145 int32_t ti_sysc_sidle[SYSC_IDLE_MAX];
146 uint32_t ti_sysc_delay_us;
147 uint32_t ti_syss_mask;
150 TAILQ_HEAD(, clk_list) clk_list;
152 /* deprecated ti_hwmods */
153 bool ti_no_reset_on_init;
154 bool ti_no_idle_on_init;
159 * All sysc seems to have a reg["rev"] register.
160 * Lets use that for identification of which module the driver are connected to.
163 ti_sysc_get_rev_address(device_t dev) {
164 struct ti_sysc_softc *sc = device_get_softc(dev);
166 return (sc->reg[REG_REV].address);
170 ti_sysc_get_rev_address_offset_host(device_t dev) {
171 struct ti_sysc_softc *sc = device_get_softc(dev);
173 return (sc->offset_reg[REG_REV]);
177 ti_sysc_get_sysc_address(device_t dev) {
178 struct ti_sysc_softc *sc = device_get_softc(dev);
180 return (sc->reg[REG_SYSC].address);
184 ti_sysc_get_sysc_address_offset_host(device_t dev) {
185 struct ti_sysc_softc *sc = device_get_softc(dev);
187 return (sc->offset_reg[REG_SYSC]);
191 ti_sysc_get_syss_address(device_t dev) {
192 struct ti_sysc_softc *sc = device_get_softc(dev);
194 return (sc->reg[REG_SYSS].address);
198 ti_sysc_get_syss_address_offset_host(device_t dev) {
199 struct ti_sysc_softc *sc = device_get_softc(dev);
201 return (sc->offset_reg[REG_SYSS]);
205 * Due no memory region is assigned the sysc driver the children needs to
206 * handle the practical read/writes to the registers.
207 * Check if sysc has reset bit.
210 ti_sysc_get_soft_reset_bit(device_t dev) {
211 struct ti_sysc_softc *sc = device_get_softc(dev);
212 switch (sc->device_type) {
213 case TI_SYSC_OMAP4_TIMER:
214 case TI_SYSC_OMAP4_SIMPLE:
216 if (sc->ti_sysc_mask & SYSC_OMAP4_SOFTRESET) {
217 return (SYSC_OMAP4_SOFTRESET);
221 case TI_SYSC_OMAP2_TIMER:
224 if (sc->ti_sysc_mask & SYSC_OMAP2_SOFTRESET) {
225 return (SYSC_OMAP2_SOFTRESET);
236 ti_sysc_clock_enable(device_t dev) {
237 struct clk_list *clkp, *clkp_tmp;
238 struct ti_sysc_softc *sc = device_get_softc(dev);
241 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
242 err = clk_enable(clkp->clk);
245 DPRINTF(sc->dev, "clk_enable %s failed %d\n",
246 clk_get_name(clkp->clk), err);
254 ti_sysc_clock_disable(device_t dev) {
255 struct clk_list *clkp, *clkp_tmp;
256 struct ti_sysc_softc *sc = device_get_softc(dev);
259 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
260 err = clk_disable(clkp->clk);
263 DPRINTF(sc->dev, "clk_enable %s failed %d\n",
264 clk_get_name(clkp->clk), err);
272 parse_regfields(struct ti_sysc_softc *sc) {
274 uint32_t parent_address_cells;
275 uint32_t parent_size_cells;
278 int err, k, reg_i, prop_idx;
281 node = ofw_bus_get_node(sc->dev);
283 /* Get parents address and size properties */
284 err = OF_searchencprop(OF_parent(node), "#address-cells",
285 &parent_address_cells, sizeof(parent_address_cells));
288 if (!(parent_address_cells == 1 || parent_address_cells == 2)) {
289 DPRINTF(sc->dev, "Expect parent #address-cells=[1||2]\n");
293 err = OF_searchencprop(OF_parent(node), "#size-cells",
294 &parent_size_cells, sizeof(parent_size_cells));
298 if (!(parent_size_cells == 1 || parent_size_cells == 2)) {
299 DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n");
303 /* Grab the content of reg properties */
304 nreg = OF_getproplen(node, "reg");
308 reg = malloc(nreg, M_DEVBUF, M_WAITOK);
309 OF_getencprop(node, "reg", reg, nreg);
311 /* Make sure address & size are 0 */
312 for (idx = 0; idx < REG_MAX; idx++) {
313 sc->reg[idx].address = 0;
314 sc->reg[idx].size = 0;
317 /* Loop through reg-names and figure out which reg-name corresponds to
318 * index populate the values into the reg array.
320 for (idx = 0, reg_i = 0; idx < REG_MAX && reg_i < nreg; idx++) {
321 err = ofw_bus_find_string_index(node, "reg-names",
322 reg_names[idx], &prop_idx);
326 for (k = 0; k < parent_address_cells; k++) {
327 sc->reg[prop_idx].address <<= 32;
328 sc->reg[prop_idx].address |= reg[reg_i++];
331 for (k = 0; k < parent_size_cells; k++) {
332 sc->reg[prop_idx].size <<= 32;
333 sc->reg[prop_idx].size |= reg[reg_i++];
336 if (sc->sc.nranges == 0)
337 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address;
339 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address -
340 sc->sc.ranges[REG_REV].host;
342 DPRINTF(sc->dev, "reg[%s] address %#jx size %#jx\n",
344 sc->reg[prop_idx].address,
345 sc->reg[prop_idx].size);
352 parse_idle(struct ti_sysc_softc *sc, const char *name, uint32_t *idle) {
354 cell_t value[SYSC_IDLE_MAX];
357 node = ofw_bus_get_node(sc->dev);
359 if (!OF_hasprop(node, name)) {
363 len = OF_getproplen(node, name);
364 no = len / sizeof(cell_t);
365 if (no >= SYSC_IDLE_MAX) {
366 DPRINTF(sc->dev, "Limit %s\n", name);
367 no = SYSC_IDLE_MAX-1;
368 len = no * sizeof(cell_t);
371 OF_getencprop(node, name, value, len);
372 for (i = 0; i < no; i++) {
375 DPRINTF(sc->dev, "%s[%d] = %d ",
378 case SYSC_IDLE_FORCE:
379 DPRINTF(sc->dev, "SYSC_IDLE_FORCE\n");
382 DPRINTF(sc->dev, "SYSC_IDLE_NO\n");
384 case SYSC_IDLE_SMART:
385 DPRINTF(sc->dev, "SYSC_IDLE_SMART\n");
387 case SYSC_IDLE_SMART_WKUP:
388 DPRINTF(sc->dev, "SYSC_IDLE_SMART_WKUP\n");
393 for ( ; i < SYSC_IDLE_MAX; i++)
398 ti_sysc_attach_clocks(struct ti_sysc_softc *sc) {
400 struct clk_list *clkp;
403 clk = malloc(sc->num_clocks*sizeof(clk_t), M_DEVBUF, M_WAITOK | M_ZERO);
405 /* Check if all clocks can be found */
406 for (index = 0; index < sc->num_clocks; index++) {
407 err = clk_get_by_ofw_index(sc->dev, 0, index, &clk[index]);
415 /* All clocks are found, add to list */
416 for (index = 0; index < sc->num_clocks; index++) {
417 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
418 clkp->clk = clk[index];
419 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
422 /* Release the clk array */
428 ti_sysc_simplebus_attach_child(device_t dev) {
430 phandle_t node, child;
431 struct ti_sysc_softc *sc = device_get_softc(dev);
433 node = ofw_bus_get_node(sc->dev);
435 for (child = OF_child(node); child > 0; child = OF_peer(child)) {
436 cdev = simplebus_add_device(sc->dev, child, 0, NULL, -1, NULL);
438 device_probe_and_attach(cdev);
443 /* Device interface */
445 ti_sysc_probe(device_t dev)
447 if (!ofw_bus_status_okay(dev))
450 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
453 device_set_desc(dev, "TI SYSC Interconnect");
455 return (BUS_PROBE_DEFAULT);
459 ti_sysc_attach(device_t dev)
461 struct ti_sysc_softc *sc;
466 sc = device_get_softc(dev);
468 sc->device_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
470 node = ofw_bus_get_node(sc->dev);
471 /* ranges - use simplebus */
472 simplebus_init(sc->dev, node);
473 if (simplebus_fill_ranges(node, &sc->sc) < 0) {
474 DPRINTF(sc->dev, "could not get ranges\n");
478 if (sc->sc.nranges == 0) {
479 DPRINTF(sc->dev, "nranges == 0\n");
483 /* Required field reg & reg-names - assume at least "rev" exists */
484 err = parse_regfields(sc);
486 DPRINTF(sc->dev, "parse_regfields failed %d\n", err);
491 if (OF_hasprop(node, "ti,sysc-mask")) {
492 OF_getencprop(node, "ti,sysc-mask", &value, sizeof(cell_t));
493 sc->ti_sysc_mask = value;
495 if (OF_hasprop(node, "ti,syss-mask")) {
496 OF_getencprop(node, "ti,syss-mask", &value, sizeof(cell_t));
497 sc->ti_syss_mask = value;
499 if (OF_hasprop(node, "ti,sysc-delay-us")) {
500 OF_getencprop(node, "ti,sysc-delay-us", &value, sizeof(cell_t));
501 sc->ti_sysc_delay_us = value;
504 DPRINTF(sc->dev, "sysc_mask %x syss_mask %x delay_us %x\n",
505 sc->ti_sysc_mask, sc->ti_syss_mask, sc->ti_sysc_delay_us);
507 parse_idle(sc, "ti,sysc-midle", sc->ti_sysc_midle);
508 parse_idle(sc, "ti,sysc-sidle", sc->ti_sysc_sidle);
510 if (OF_hasprop(node, "ti,no-reset-on-init"))
511 sc->ti_no_reset_on_init = true;
513 sc->ti_no_reset_on_init = false;
515 if (OF_hasprop(node, "ti,no-idle-on-init"))
516 sc->ti_no_idle_on_init = true;
518 sc->ti_no_idle_on_init = false;
520 if (OF_hasprop(node, "ti,no-idle"))
521 sc->ti_no_idle = true;
523 sc->ti_no_idle = false;
526 "no-reset-on-init %d, no-idle-on-init %d, no-idle %d\n",
527 sc->ti_no_reset_on_init,
528 sc->ti_no_idle_on_init,
531 if (OF_hasprop(node, "clocks")) {
532 struct clock_cell_info cell_info;
533 read_clock_cells(sc->dev, &cell_info);
534 free(cell_info.clock_cells, M_DEVBUF);
535 free(cell_info.clock_cells_ncells, M_DEVBUF);
537 sc->num_clocks = cell_info.num_real_clocks;
538 TAILQ_INIT(&sc->clk_list);
540 err = ti_sysc_attach_clocks(sc);
542 DPRINTF(sc->dev, "Failed to attach clocks\n");
543 return (bus_generic_attach(sc->dev));
547 err = ti_sysc_simplebus_attach_child(sc->dev);
549 DPRINTF(sc->dev, "ti_sysc_simplebus_attach_child %d\n",
554 sc->attach_done = true;
556 return (bus_generic_attach(sc->dev));
560 ti_sysc_detach(device_t dev)
567 ti_sysc_new_pass(device_t dev)
569 struct ti_sysc_softc *sc;
573 sc = device_get_softc(dev);
575 if (sc->attach_done) {
576 bus_generic_new_pass(sc->dev);
580 node = ofw_bus_get_node(sc->dev);
581 if (OF_hasprop(node, "clocks")) {
582 err = ti_sysc_attach_clocks(sc);
584 DPRINTF(sc->dev, "Failed to attach clocks\n");
589 err = ti_sysc_simplebus_attach_child(sc->dev);
592 "ti_sysc_simplebus_attach_child failed %d\n", err);
595 sc->attach_done = true;
597 bus_generic_attach(sc->dev);
600 static device_method_t ti_sysc_methods[] = {
601 /* Device interface */
602 DEVMETHOD(device_probe, ti_sysc_probe),
603 DEVMETHOD(device_attach, ti_sysc_attach),
604 DEVMETHOD(device_detach, ti_sysc_detach),
607 DEVMETHOD(bus_new_pass, ti_sysc_new_pass),
612 DEFINE_CLASS_1(ti_sysc, ti_sysc_driver, ti_sysc_methods,
613 sizeof(struct ti_sysc_softc), simplebus_driver);
615 EARLY_DRIVER_MODULE(ti_sysc, simplebus, ti_sysc_driver, 0, 0,
616 BUS_PASS_BUS + BUS_PASS_ORDER_FIRST);