2 * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/event.h>
38 #include <sys/selinfo.h>
39 #include <sys/watchdog.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/frame.h>
43 #include <machine/intr.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <machine/bus.h>
51 #include <arm/ti/ti_prcm.h>
52 #include <arm/ti/ti_wdt.h>
55 #define DPRINTF(fmt, ...) do { \
56 printf("%s: ", __func__); \
57 printf(fmt, __VA_ARGS__); \
60 #define DPRINTF(fmt, ...)
63 static device_probe_t ti_wdt_probe;
64 static device_attach_t ti_wdt_attach;
65 static device_detach_t ti_wdt_detach;
66 static void ti_wdt_intr(void *);
67 static void ti_wdt_event(void *, unsigned int, int *);
70 struct resource *sc_mem_res;
71 struct resource *sc_irq_res;
73 bus_space_tag_t sc_bt;
74 bus_space_handle_t sc_bh;
75 eventhandler_tag sc_ev_tag;
78 static device_method_t ti_wdt_methods[] = {
79 DEVMETHOD(device_probe, ti_wdt_probe),
80 DEVMETHOD(device_attach, ti_wdt_attach),
81 DEVMETHOD(device_detach, ti_wdt_detach),
86 static driver_t ti_wdt_driver = {
89 sizeof(struct ti_wdt_softc)
92 static devclass_t ti_wdt_devclass;
94 DRIVER_MODULE(ti_wdt, simplebus, ti_wdt_driver, ti_wdt_devclass, 0, 0);
96 static __inline uint32_t
97 ti_wdt_reg_read(struct ti_wdt_softc *sc, uint32_t reg)
100 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
104 ti_wdt_reg_write(struct ti_wdt_softc *sc, uint32_t reg, uint32_t val)
107 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
111 * Wait for the write to a specific synchronised register to complete.
114 ti_wdt_reg_wait(struct ti_wdt_softc *sc, uint32_t bit)
117 while (ti_wdt_reg_read(sc, TI_WDT_WWPS) & bit)
122 ti_wdt_disable(struct ti_wdt_softc *sc)
125 DPRINTF("disabling watchdog %p\n", sc);
126 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xAAAA);
127 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
128 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x5555);
129 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
133 ti_wdt_enable(struct ti_wdt_softc *sc)
136 DPRINTF("enabling watchdog %p\n", sc);
137 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xBBBB);
138 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
139 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x4444);
140 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
144 ti_wdt_probe(device_t dev)
147 if (!ofw_bus_status_okay(dev))
149 if (ofw_bus_is_compatible(dev, "ti,omap3-wdt")) {
150 device_set_desc(dev, "TI Watchdog Timer");
151 return (BUS_PROBE_DEFAULT);
158 ti_wdt_attach(device_t dev)
160 struct ti_wdt_softc *sc;
163 sc = device_get_softc(dev);
165 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
167 if (sc->sc_mem_res == NULL) {
168 device_printf(dev, "could not allocate memory resource\n");
171 sc->sc_bt = rman_get_bustag(sc->sc_mem_res);
172 sc->sc_bh = rman_get_bushandle(sc->sc_mem_res);
173 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
174 if (sc->sc_irq_res == NULL) {
175 device_printf(dev, "could not allocate interrupt resource\n");
179 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE | INTR_TYPE_MISC,
180 NULL, ti_wdt_intr, sc, &sc->sc_intr) != 0) {
182 "unable to setup the interrupt handler\n");
186 /* Reset, enable interrupts and stop the watchdog. */
187 ti_wdt_reg_write(sc, TI_WDT_WDSC,
188 ti_wdt_reg_read(sc, TI_WDT_WDSC) | TI_WDSC_SR);
189 while (ti_wdt_reg_read(sc, TI_WDT_WDSC) & TI_WDSC_SR)
191 ti_wdt_reg_write(sc, TI_WDT_WIRQENSET, TI_IRQ_EN_OVF | TI_IRQ_EN_DLY);
194 device_printf(dev, "revision: 0x%x\n",
195 ti_wdt_reg_read(sc, TI_WDT_WIDR));
196 sc->sc_ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ti_wdt_event, sc,
203 ti_wdt_detach(device_t dev)
205 struct ti_wdt_softc *sc;
207 sc = device_get_softc(dev);
209 EVENTHANDLER_DEREGISTER(watchdog_list, sc->sc_ev_tag);
211 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr);
213 bus_release_resource(dev, SYS_RES_IRQ,
214 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
216 bus_release_resource(dev, SYS_RES_MEMORY,
217 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
223 ti_wdt_intr(void *arg)
225 struct ti_wdt_softc *sc;
228 DPRINTF("interrupt %p", sc);
229 ti_wdt_reg_write(sc, TI_WDT_WIRQSTAT, TI_IRQ_EV_OVF | TI_IRQ_EV_DLY);
230 /* TODO: handle interrupt */
234 ti_wdt_event(void *arg, unsigned int cmd, int *error)
236 struct ti_wdt_softc *sc;
243 if (cmd == WD_TO_NEVER) {
247 DPRINTF("cmd 0x%x\n", cmd);
249 if (cmd < WD_TO_1SEC) {
253 s = 1 << (cmd - WD_TO_1SEC);
254 DPRINTF("seconds %u\n", s);
256 * Leave the pre-scaler with its default values:
257 * PTV = 0 == 2**0 == 1
260 * Compute the load register value assuming a 32kHz clock.
261 * See OVF_Rate in the WDT section of the AM335x TRM.
264 wldr = 0xffffffff - (s * (32768 / (1 << ptv))) + 1;
265 DPRINTF("wldr 0x%x\n", wldr);
266 ti_wdt_reg_write(sc, TI_WDT_WLDR, wldr);
268 * Trigger a timer reload.
270 ti_wdt_reg_write(sc, TI_WDT_WTGR,
271 ti_wdt_reg_read(sc, TI_WDT_WTGR) + 1);
272 ti_wdt_reg_wait(sc, TI_W_PEND_WTGR);