3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
37 #include <sys/condvar.h>
39 #include <dev/fdt/simplebus.h>
40 #include <dev/fdt/fdt_common.h>
41 #include <dev/ofw/ofw_bus_subr.h>
43 #include <dev/usb/usb.h>
44 #include <dev/usb/usbdi.h>
46 #include <dev/usb/usb_core.h>
47 #include <dev/usb/usb_busdma.h>
48 #include <dev/usb/usb_process.h>
49 #include <dev/usb/usb_util.h>
51 #include <dev/usb/usb_controller.h>
52 #include <dev/usb/usb_bus.h>
53 #include <dev/usb/controller/ehci.h>
54 #include <dev/usb/controller/ehcireg.h>
56 #include <machine/bus.h>
58 #include <arm/ti/ti_prcm.h>
59 #include <arm/ti/usb/omap_usb.h>
61 #include <arm/ti/omap4/pandaboard/pandaboard.h>
64 #define OMAP_USBHOST_HCCAPBASE 0x0000
65 #define OMAP_USBHOST_HCSPARAMS 0x0004
66 #define OMAP_USBHOST_HCCPARAMS 0x0008
67 #define OMAP_USBHOST_USBCMD 0x0010
68 #define OMAP_USBHOST_USBSTS 0x0014
69 #define OMAP_USBHOST_USBINTR 0x0018
70 #define OMAP_USBHOST_FRINDEX 0x001C
71 #define OMAP_USBHOST_CTRLDSSEGMENT 0x0020
72 #define OMAP_USBHOST_PERIODICLISTBASE 0x0024
73 #define OMAP_USBHOST_ASYNCLISTADDR 0x0028
74 #define OMAP_USBHOST_CONFIGFLAG 0x0050
75 #define OMAP_USBHOST_PORTSC(i) (0x0054 + (0x04 * (i)))
76 #define OMAP_USBHOST_INSNREG00 0x0090
77 #define OMAP_USBHOST_INSNREG01 0x0094
78 #define OMAP_USBHOST_INSNREG02 0x0098
79 #define OMAP_USBHOST_INSNREG03 0x009C
80 #define OMAP_USBHOST_INSNREG04 0x00A0
81 #define OMAP_USBHOST_INSNREG05_UTMI 0x00A4
82 #define OMAP_USBHOST_INSNREG05_ULPI 0x00A4
83 #define OMAP_USBHOST_INSNREG06 0x00A8
84 #define OMAP_USBHOST_INSNREG07 0x00AC
85 #define OMAP_USBHOST_INSNREG08 0x00B0
87 #define OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND (1 << 5)
89 #define OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT 31
90 #define OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT 24
91 #define OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT 22
92 #define OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT 16
93 #define OMAP_USBHOST_INSNREG05_ULPI_EXTREGADD_SHIFT 8
94 #define OMAP_USBHOST_INSNREG05_ULPI_WRDATA_SHIFT 0
96 #define ULPI_FUNC_CTRL_RESET (1 << 5)
98 /*-------------------------------------------------------------------------*/
101 * Macros for Set and Clear
102 * See ULPI 1.1 specification to find the registers with Set and Clear offsets
104 #define ULPI_SET(a) (a + 1)
105 #define ULPI_CLR(a) (a + 2)
107 /*-------------------------------------------------------------------------*/
112 #define ULPI_VENDOR_ID_LOW 0x00
113 #define ULPI_VENDOR_ID_HIGH 0x01
114 #define ULPI_PRODUCT_ID_LOW 0x02
115 #define ULPI_PRODUCT_ID_HIGH 0x03
116 #define ULPI_FUNC_CTRL 0x04
117 #define ULPI_IFC_CTRL 0x07
118 #define ULPI_OTG_CTRL 0x0a
119 #define ULPI_USB_INT_EN_RISE 0x0d
120 #define ULPI_USB_INT_EN_FALL 0x10
121 #define ULPI_USB_INT_STS 0x13
122 #define ULPI_USB_INT_LATCH 0x14
123 #define ULPI_DEBUG 0x15
124 #define ULPI_SCRATCH 0x16
126 #define OMAP_EHCI_HC_DEVSTR "TI OMAP USB 2.0 controller"
128 struct omap_ehci_softc {
129 ehci_softc_t base; /* storage for EHCI code */
133 static device_attach_t omap_ehci_attach;
134 static device_detach_t omap_ehci_detach;
137 * omap_ehci_read_4 - read a 32-bit value from the EHCI registers
138 * omap_ehci_write_4 - write a 32-bit value from the EHCI registers
139 * @sc: omap ehci device context
140 * @off: byte offset within the register set to read from
141 * @val: the value to write into the register
148 * nothing in case of write function, if read function returns the value read.
150 static inline uint32_t
151 omap_ehci_read_4(struct omap_ehci_softc *sc, bus_size_t off)
153 return (bus_read_4(sc->base.sc_io_res, off));
157 omap_ehci_write_4(struct omap_ehci_softc *sc, bus_size_t off, uint32_t val)
159 bus_write_4(sc->base.sc_io_res, off, val);
163 * omap_ehci_soft_phy_reset - resets the phy using the reset command
164 * @isc: omap ehci device context
165 * @port: port to send the reset over
175 omap_ehci_soft_phy_reset(struct omap_ehci_softc *isc, unsigned int port)
177 unsigned long timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
180 reg = ULPI_FUNC_CTRL_RESET
181 /* FUNCTION_CTRL_SET register */
182 | (ULPI_SET(ULPI_FUNC_CTRL) << OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT)
184 | (2 << OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT)
186 | ((port + 1) << OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT)
187 /* start ULPI access*/
188 | (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT);
190 omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg);
192 /* Wait for ULPI access completion */
193 while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI)
194 & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) {
196 /* Sleep for a tick */
197 pause("USBPHY_RESET", 1);
199 if (timeout-- == 0) {
200 device_printf(isc->sc_dev, "PHY reset operation timed out\n");
207 * omap_ehci_init - initialises the USB host EHCI controller
208 * @isc: omap ehci device context
210 * This initialisation routine is quite heavily based on the work done by the
211 * OMAP Linux team (for which I thank them very much). The init sequence is
212 * almost identical, diverging only for the FreeBSD specifics.
218 * 0 on success, a negative error code on failure.
221 omap_ehci_init(struct omap_ehci_softc *isc)
227 uhh_dev = device_get_parent(isc->sc_dev);
228 device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n");
230 /* Set the interrupt threshold control, it controls the maximum rate at
231 * which the host controller issues interrupts. We set it to 1 microframe
232 * at startup - the default is 8 mircoframes (equates to 1ms).
234 reg = omap_ehci_read_4(isc, OMAP_USBHOST_USBCMD);
237 omap_ehci_write_4(isc, OMAP_USBHOST_USBCMD, reg);
239 /* Soft reset the PHY using PHY reset command over ULPI */
240 for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
241 if (omap_usb_port_mode(uhh_dev, i) == EHCI_HCD_OMAP_MODE_PHY)
242 omap_ehci_soft_phy_reset(isc, i);
250 * omap_ehci_probe - starts the given command
253 * Effectively boilerplate EHCI resume code.
256 * Caller should be holding the OMAP3_MMC lock.
259 * EH_HANDLED or EH_NOT_HANDLED
262 omap_ehci_probe(device_t dev)
264 if (!ofw_bus_status_okay(dev))
267 if (!ofw_bus_is_compatible(dev, "ti,ehci-omap"))
270 device_set_desc(dev, OMAP_EHCI_HC_DEVSTR);
272 return (BUS_PROBE_DEFAULT);
276 * omap_ehci_attach - driver entry point, sets up the ECHI controller/driver
277 * @dev: the new device handle
279 * Sets up bus spaces, interrupt handles, etc for the EHCI controller. It also
280 * parses the resource hints and calls omap_ehci_init() to initialise the
287 * 0 on success or a positive error code on failure.
290 omap_ehci_attach(device_t dev)
292 struct omap_ehci_softc *isc = device_get_softc(dev);
293 ehci_softc_t *sc = &isc->base;
302 * If we're running a Pandaboard, run Pandaboard-specific
305 root = OF_finddevice("/");
306 if (ofw_bus_node_is_compatible(root, "ti,omap4-panda"))
307 pandaboard_usb_hub_init();
310 /* initialise some bus fields */
311 sc->sc_bus.parent = dev;
312 sc->sc_bus.devices = sc->sc_devices;
313 sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
314 sc->sc_bus.dma_bits = 32;
316 sprintf(sc->sc_vendor, "Texas Instruments");
318 /* save the device */
321 /* get all DMA memory */
322 if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev),
323 &ehci_iterate_hw_softc)) {
327 /* Allocate resource for the EHCI register set */
329 sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
330 if (!sc->sc_io_res) {
331 device_printf(dev, "Error: Could not map EHCI memory\n");
334 /* Request an interrupt resource */
336 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
337 if (sc->sc_irq_res == NULL) {
338 device_printf(dev, "Error: could not allocate irq\n");
342 /* Add this device as a child of the USBus device */
343 sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
344 if (!sc->sc_bus.bdev) {
345 device_printf(dev, "Error: could not add USB device\n");
349 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
350 device_set_desc(sc->sc_bus.bdev, OMAP_EHCI_HC_DEVSTR);
352 /* Initialise the ECHI registers */
353 err = omap_ehci_init(isc);
355 device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err);
359 /* Set the tag and size of the register set in the EHCI context */
360 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
361 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
362 sc->sc_io_size = rman_get_size(sc->sc_io_res);
364 /* Setup the interrupt */
365 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
366 NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
368 device_printf(dev, "Error: could not setup irq, %d\n", err);
369 sc->sc_intr_hdl = NULL;
373 /* Finally we are ready to kick off the ECHI host controller */
376 err = device_probe_and_attach(sc->sc_bus.bdev);
379 device_printf(dev, "Error: USB init failed err=%d\n", err);
386 omap_ehci_detach(dev);
391 * omap_ehci_detach - detach the device and cleanup the driver
392 * @dev: device handle
394 * Clean-up routine where everything initialised in omap_ehci_attach is
395 * freed and cleaned up. This function calls omap_ehci_fini() to shutdown
396 * the on-chip module.
402 * Always returns 0 (success).
405 omap_ehci_detach(device_t dev)
407 struct omap_ehci_softc *isc = device_get_softc(dev);
408 ehci_softc_t *sc = &isc->base;
411 /* during module unload there are lots of children leftover */
412 device_delete_children(dev);
415 * disable interrupts that might have been switched on in ehci_init
418 EWRITE4(sc, EHCI_USBINTR, 0);
421 if (sc->sc_irq_res && sc->sc_intr_hdl) {
423 * only call ehci_detach() after ehci_init()
427 err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl);
429 device_printf(dev, "Error: could not tear down irq, %d\n", err);
430 sc->sc_intr_hdl = NULL;
433 /* Free the resources stored in the base EHCI handler */
434 if (sc->sc_irq_res) {
435 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
436 sc->sc_irq_res = NULL;
439 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res);
440 sc->sc_io_res = NULL;
446 static device_method_t ehci_methods[] = {
447 /* Device interface */
448 DEVMETHOD(device_probe, omap_ehci_probe),
449 DEVMETHOD(device_attach, omap_ehci_attach),
450 DEVMETHOD(device_detach, omap_ehci_detach),
452 DEVMETHOD(device_suspend, bus_generic_suspend),
453 DEVMETHOD(device_resume, bus_generic_resume),
454 DEVMETHOD(device_shutdown, bus_generic_shutdown),
457 DEVMETHOD(bus_print_child, bus_generic_print_child),
462 static driver_t ehci_driver = {
465 sizeof(struct omap_ehci_softc),
468 static devclass_t ehci_devclass;
470 DRIVER_MODULE(ehci, omap_uhh, ehci_driver, ehci_devclass, 0, 0);