2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
38 #include <sys/timeet.h>
39 #include <sys/timetc.h>
40 #include <sys/watchdog.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/intr.h>
45 #include <dev/fdt/fdt_common.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <machine/bus.h>
52 #define SP804_TIMER1_LOAD 0x00
53 #define SP804_TIMER1_VALUE 0x04
54 #define SP804_TIMER1_CONTROL 0x08
55 #define TIMER_CONTROL_EN (1 << 7)
56 #define TIMER_CONTROL_FREERUN (0 << 6)
57 #define TIMER_CONTROL_PERIODIC (1 << 6)
58 #define TIMER_CONTROL_INTREN (1 << 5)
59 #define TIMER_CONTROL_DIV1 (0 << 2)
60 #define TIMER_CONTROL_DIV16 (1 << 2)
61 #define TIMER_CONTROL_DIV256 (2 << 2)
62 #define TIMER_CONTROL_32BIT (1 << 1)
63 #define TIMER_CONTROL_ONESHOT (1 << 0)
64 #define SP804_TIMER1_INTCLR 0x0C
65 #define SP804_TIMER1_RIS 0x10
66 #define SP804_TIMER1_MIS 0x14
67 #define SP804_TIMER1_BGLOAD 0x18
68 #define SP804_TIMER2_LOAD 0x20
69 #define SP804_TIMER2_VALUE 0x24
70 #define SP804_TIMER2_CONTROL 0x28
71 #define SP804_TIMER2_INTCLR 0x2C
72 #define SP804_TIMER2_RIS 0x30
73 #define SP804_TIMER2_MIS 0x34
74 #define SP804_TIMER2_BGLOAD 0x38
76 #define SP804_PERIPH_ID0 0xFE0
77 #define SP804_PERIPH_ID1 0xFE4
78 #define SP804_PERIPH_ID2 0xFE8
79 #define SP804_PERIPH_ID3 0xFEC
80 #define SP804_PRIMECELL_ID0 0xFF0
81 #define SP804_PRIMECELL_ID1 0xFF4
82 #define SP804_PRIMECELL_ID2 0xFF8
83 #define SP804_PRIMECELL_ID3 0xFFC
85 #define DEFAULT_FREQUENCY 1000000
87 * QEMU seems to have problem with full frequency
89 #define DEFAULT_DIVISOR 16
90 #define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16
92 struct sp804_timer_softc {
93 struct resource* mem_res;
94 struct resource* irq_res;
98 bus_space_handle_t bsh;
99 struct timecounter tc;
101 struct eventtimer et;
102 int timer_initialized;
105 /* Read/Write macros for Timer used as timecounter */
106 #define sp804_timer_tc_read_4(reg) \
107 bus_space_read_4(sc->bst, sc->bsh, reg)
109 #define sp804_timer_tc_write_4(reg, val) \
110 bus_space_write_4(sc->bst, sc->bsh, reg, val)
112 static unsigned sp804_timer_tc_get_timecount(struct timecounter *);
115 sp804_timer_tc_get_timecount(struct timecounter *tc)
117 struct sp804_timer_softc *sc = tc->tc_priv;
118 return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
122 sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
124 struct sp804_timer_softc *sc = et->et_priv;
130 count = ((uint32_t)et->et_frequency * first) >> 32;
132 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
133 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
134 TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV |
136 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
149 sp804_timer_stop(struct eventtimer *et)
151 struct sp804_timer_softc *sc = et->et_priv;
155 reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);
156 reg &= ~(TIMER_CONTROL_EN);
157 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
163 sp804_timer_intr(void *arg)
165 struct sp804_timer_softc *sc = arg;
166 static uint32_t prev = 0;
169 x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
172 sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1);
173 if (sc->et_enabled) {
174 if (sc->et.et_active) {
175 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
179 return (FILTER_HANDLED);
183 sp804_timer_probe(device_t dev)
186 if (!ofw_bus_status_okay(dev))
189 if (ofw_bus_is_compatible(dev, "arm,sp804")) {
190 device_set_desc(dev, "SP804 System Timer");
191 return (BUS_PROBE_DEFAULT);
198 sp804_timer_attach(device_t dev)
200 struct sp804_timer_softc *sc = device_get_softc(dev);
207 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
208 if (sc->mem_res == NULL) {
209 device_printf(dev, "could not allocate memory resource\n");
213 sc->bst = rman_get_bustag(sc->mem_res);
214 sc->bsh = rman_get_bushandle(sc->mem_res);
216 /* Request the IRQ resources */
217 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
218 if (sc->irq_res == NULL) {
219 device_printf(dev, "Error: could not allocate irq resources\n");
223 sc->sysclk_freq = DEFAULT_FREQUENCY;
224 /* Get the base clock frequency */
225 node = ofw_bus_get_node(dev);
226 if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
227 sc->sysclk_freq = fdt32_to_cpu(clock);
230 /* Setup and enable the timer */
231 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
232 sp804_timer_intr, NULL, sc,
233 &sc->intr_hl) != 0) {
234 bus_release_resource(dev, SYS_RES_IRQ, rid,
236 device_printf(dev, "Unable to setup the clock irq handler.\n");
240 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0);
241 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0);
244 * Timer 1, timecounter
246 sc->tc.tc_frequency = sc->sysclk_freq;
247 sc->tc.tc_name = "SP804 Time Counter";
248 sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount;
249 sc->tc.tc_poll_pps = NULL;
250 sc->tc.tc_counter_mask = ~0u;
251 sc->tc.tc_quality = 1000;
254 sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff);
255 sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff);
256 reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;
257 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
258 reg |= TIMER_CONTROL_EN;
259 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
263 * Timer 2, event timer
266 sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO);
267 sprintf(sc->et.et_name, "SP804 Event Timer %d",
268 device_get_unit(dev));
269 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
270 sc->et.et_quality = 1000;
271 sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
272 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
273 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
274 sc->et.et_start = sp804_timer_start;
275 sc->et.et_stop = sp804_timer_stop;
277 et_register(&sc->et);
280 for (i = 3; i >= 0; i--) {
282 (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff);
285 device_printf(dev, "peripheral ID: %08x\n", id);
288 for (i = 3; i >= 0; i--) {
290 (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff);
293 device_printf(dev, "PrimeCell ID: %08x\n", id);
295 sc->timer_initialized = 1;
300 static device_method_t sp804_timer_methods[] = {
301 DEVMETHOD(device_probe, sp804_timer_probe),
302 DEVMETHOD(device_attach, sp804_timer_attach),
306 static driver_t sp804_timer_driver = {
309 sizeof(struct sp804_timer_softc),
312 static devclass_t sp804_timer_devclass;
314 DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0);
320 uint32_t first, last;
322 struct sp804_timer_softc *sc;
323 int timer_initialized = 0;
325 timer_dev = devclass_get_device(sp804_timer_devclass, 0);
328 sc = device_get_softc(timer_dev);
331 timer_initialized = sc->timer_initialized;
334 if (!timer_initialized) {
336 * Timer is not initialized yet
338 for (; usec > 0; usec--)
339 for (counts = 200; counts > 0; counts--)
340 /* Prevent gcc from optimizing out the loop */
345 /* Get the number of times to count */
346 counts = usec * ((sc->tc.tc_frequency / 1000000) + 1);
348 first = sp804_timer_tc_get_timecount(&sc->tc);
351 last = sp804_timer_tc_get_timecount(&sc->tc);
355 counts -= (int32_t)(last - first);
357 counts -= (int32_t)((0xFFFFFFFF - first) + last);