2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
38 #include <sys/timeet.h>
39 #include <sys/timetc.h>
40 #include <sys/watchdog.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/intr.h>
45 #include <machine/machdep.h> /* For arm_set_delay */
47 #include <dev/ofw/openfirm.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
51 #include <machine/bus.h>
53 #define SP804_TIMER1_LOAD 0x00
54 #define SP804_TIMER1_VALUE 0x04
55 #define SP804_TIMER1_CONTROL 0x08
56 #define TIMER_CONTROL_EN (1 << 7)
57 #define TIMER_CONTROL_FREERUN (0 << 6)
58 #define TIMER_CONTROL_PERIODIC (1 << 6)
59 #define TIMER_CONTROL_INTREN (1 << 5)
60 #define TIMER_CONTROL_DIV1 (0 << 2)
61 #define TIMER_CONTROL_DIV16 (1 << 2)
62 #define TIMER_CONTROL_DIV256 (2 << 2)
63 #define TIMER_CONTROL_32BIT (1 << 1)
64 #define TIMER_CONTROL_ONESHOT (1 << 0)
65 #define SP804_TIMER1_INTCLR 0x0C
66 #define SP804_TIMER1_RIS 0x10
67 #define SP804_TIMER1_MIS 0x14
68 #define SP804_TIMER1_BGLOAD 0x18
69 #define SP804_TIMER2_LOAD 0x20
70 #define SP804_TIMER2_VALUE 0x24
71 #define SP804_TIMER2_CONTROL 0x28
72 #define SP804_TIMER2_INTCLR 0x2C
73 #define SP804_TIMER2_RIS 0x30
74 #define SP804_TIMER2_MIS 0x34
75 #define SP804_TIMER2_BGLOAD 0x38
77 #define SP804_PERIPH_ID0 0xFE0
78 #define SP804_PERIPH_ID1 0xFE4
79 #define SP804_PERIPH_ID2 0xFE8
80 #define SP804_PERIPH_ID3 0xFEC
81 #define SP804_PRIMECELL_ID0 0xFF0
82 #define SP804_PRIMECELL_ID1 0xFF4
83 #define SP804_PRIMECELL_ID2 0xFF8
84 #define SP804_PRIMECELL_ID3 0xFFC
86 #define DEFAULT_FREQUENCY 1000000
88 * QEMU seems to have problem with full frequency
90 #define DEFAULT_DIVISOR 16
91 #define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16
93 struct sp804_timer_softc {
94 struct resource* mem_res;
95 struct resource* irq_res;
99 bus_space_handle_t bsh;
100 struct timecounter tc;
102 struct eventtimer et;
103 int timer_initialized;
106 /* Read/Write macros for Timer used as timecounter */
107 #define sp804_timer_tc_read_4(reg) \
108 bus_space_read_4(sc->bst, sc->bsh, reg)
110 #define sp804_timer_tc_write_4(reg, val) \
111 bus_space_write_4(sc->bst, sc->bsh, reg, val)
113 static unsigned sp804_timer_tc_get_timecount(struct timecounter *);
114 static void sp804_timer_delay(int, void *);
117 sp804_timer_tc_get_timecount(struct timecounter *tc)
119 struct sp804_timer_softc *sc = tc->tc_priv;
120 return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
124 sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
126 struct sp804_timer_softc *sc = et->et_priv;
132 count = ((uint32_t)et->et_frequency * first) >> 32;
134 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
135 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
136 TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV |
138 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
151 sp804_timer_stop(struct eventtimer *et)
153 struct sp804_timer_softc *sc = et->et_priv;
157 reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);
158 reg &= ~(TIMER_CONTROL_EN);
159 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
165 sp804_timer_intr(void *arg)
167 struct sp804_timer_softc *sc = arg;
168 static uint32_t prev = 0;
171 x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
174 sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1);
175 if (sc->et_enabled) {
176 if (sc->et.et_active) {
177 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
181 return (FILTER_HANDLED);
185 sp804_timer_probe(device_t dev)
188 if (!ofw_bus_status_okay(dev))
191 if (ofw_bus_is_compatible(dev, "arm,sp804")) {
192 device_set_desc(dev, "SP804 System Timer");
193 return (BUS_PROBE_DEFAULT);
200 sp804_timer_attach(device_t dev)
202 struct sp804_timer_softc *sc = device_get_softc(dev);
209 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
210 if (sc->mem_res == NULL) {
211 device_printf(dev, "could not allocate memory resource\n");
215 sc->bst = rman_get_bustag(sc->mem_res);
216 sc->bsh = rman_get_bushandle(sc->mem_res);
218 /* Request the IRQ resources */
219 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
220 if (sc->irq_res == NULL) {
221 device_printf(dev, "Error: could not allocate irq resources\n");
225 sc->sysclk_freq = DEFAULT_FREQUENCY;
226 /* Get the base clock frequency */
227 node = ofw_bus_get_node(dev);
228 if ((OF_getencprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
229 sc->sysclk_freq = clock;
232 /* Setup and enable the timer */
233 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
234 sp804_timer_intr, NULL, sc,
235 &sc->intr_hl) != 0) {
236 bus_release_resource(dev, SYS_RES_IRQ, rid,
238 device_printf(dev, "Unable to setup the clock irq handler.\n");
242 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0);
243 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0);
246 * Timer 1, timecounter
248 sc->tc.tc_frequency = sc->sysclk_freq;
249 sc->tc.tc_name = "SP804-1";
250 sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount;
251 sc->tc.tc_poll_pps = NULL;
252 sc->tc.tc_counter_mask = ~0u;
253 sc->tc.tc_quality = 1000;
256 sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff);
257 sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff);
258 reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;
259 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
260 reg |= TIMER_CONTROL_EN;
261 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
265 * Timer 2, event timer
268 sc->et.et_name = "SP804-2";
269 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
270 sc->et.et_quality = 1000;
271 sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
272 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
273 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
274 sc->et.et_start = sp804_timer_start;
275 sc->et.et_stop = sp804_timer_stop;
277 et_register(&sc->et);
280 for (i = 3; i >= 0; i--) {
282 (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff);
285 device_printf(dev, "peripheral ID: %08x\n", id);
288 for (i = 3; i >= 0; i--) {
290 (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff);
293 arm_set_delay(sp804_timer_delay, sc);
295 device_printf(dev, "PrimeCell ID: %08x\n", id);
297 sc->timer_initialized = 1;
302 static device_method_t sp804_timer_methods[] = {
303 DEVMETHOD(device_probe, sp804_timer_probe),
304 DEVMETHOD(device_attach, sp804_timer_attach),
308 static driver_t sp804_timer_driver = {
311 sizeof(struct sp804_timer_softc),
314 static devclass_t sp804_timer_devclass;
316 DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0);
319 sp804_timer_delay(int usec, void *arg)
321 struct sp804_timer_softc *sc = arg;
323 uint32_t first, last;
325 /* Get the number of times to count */
326 counts = usec * ((sc->tc.tc_frequency / 1000000) + 1);
328 first = sp804_timer_tc_get_timecount(&sc->tc);
331 last = sp804_timer_tc_get_timecount(&sc->tc);
335 counts -= (int32_t)(last - first);
337 counts -= (int32_t)((0xFFFFFFFF - first) + last);