2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
38 #include <sys/timeet.h>
39 #include <sys/timetc.h>
40 #include <sys/watchdog.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/intr.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <machine/bus.h>
51 #define SP804_TIMER1_LOAD 0x00
52 #define SP804_TIMER1_VALUE 0x04
53 #define SP804_TIMER1_CONTROL 0x08
54 #define TIMER_CONTROL_EN (1 << 7)
55 #define TIMER_CONTROL_FREERUN (0 << 6)
56 #define TIMER_CONTROL_PERIODIC (1 << 6)
57 #define TIMER_CONTROL_INTREN (1 << 5)
58 #define TIMER_CONTROL_DIV1 (0 << 2)
59 #define TIMER_CONTROL_DIV16 (1 << 2)
60 #define TIMER_CONTROL_DIV256 (2 << 2)
61 #define TIMER_CONTROL_32BIT (1 << 1)
62 #define TIMER_CONTROL_ONESHOT (1 << 0)
63 #define SP804_TIMER1_INTCLR 0x0C
64 #define SP804_TIMER1_RIS 0x10
65 #define SP804_TIMER1_MIS 0x14
66 #define SP804_TIMER1_BGLOAD 0x18
67 #define SP804_TIMER2_LOAD 0x20
68 #define SP804_TIMER2_VALUE 0x24
69 #define SP804_TIMER2_CONTROL 0x28
70 #define SP804_TIMER2_INTCLR 0x2C
71 #define SP804_TIMER2_RIS 0x30
72 #define SP804_TIMER2_MIS 0x34
73 #define SP804_TIMER2_BGLOAD 0x38
75 #define SP804_PERIPH_ID0 0xFE0
76 #define SP804_PERIPH_ID1 0xFE4
77 #define SP804_PERIPH_ID2 0xFE8
78 #define SP804_PERIPH_ID3 0xFEC
79 #define SP804_PRIMECELL_ID0 0xFF0
80 #define SP804_PRIMECELL_ID1 0xFF4
81 #define SP804_PRIMECELL_ID2 0xFF8
82 #define SP804_PRIMECELL_ID3 0xFFC
84 #define DEFAULT_FREQUENCY 1000000
86 * QEMU seems to have problem with full frequency
88 #define DEFAULT_DIVISOR 16
89 #define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16
91 struct sp804_timer_softc {
92 struct resource* mem_res;
93 struct resource* irq_res;
97 bus_space_handle_t bsh;
98 struct timecounter tc;
100 struct eventtimer et;
101 int timer_initialized;
104 /* Read/Write macros for Timer used as timecounter */
105 #define sp804_timer_tc_read_4(reg) \
106 bus_space_read_4(sc->bst, sc->bsh, reg)
108 #define sp804_timer_tc_write_4(reg, val) \
109 bus_space_write_4(sc->bst, sc->bsh, reg, val)
111 static unsigned sp804_timer_tc_get_timecount(struct timecounter *);
114 sp804_timer_tc_get_timecount(struct timecounter *tc)
116 struct sp804_timer_softc *sc = tc->tc_priv;
117 return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
121 sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
123 struct sp804_timer_softc *sc = et->et_priv;
129 count = ((uint32_t)et->et_frequency * first) >> 32;
131 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
132 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
133 TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV |
135 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
148 sp804_timer_stop(struct eventtimer *et)
150 struct sp804_timer_softc *sc = et->et_priv;
154 reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);
155 reg &= ~(TIMER_CONTROL_EN);
156 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
162 sp804_timer_intr(void *arg)
164 struct sp804_timer_softc *sc = arg;
165 static uint32_t prev = 0;
168 x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
171 sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1);
172 if (sc->et_enabled) {
173 if (sc->et.et_active) {
174 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
178 return (FILTER_HANDLED);
182 sp804_timer_probe(device_t dev)
185 if (!ofw_bus_status_okay(dev))
188 if (ofw_bus_is_compatible(dev, "arm,sp804")) {
189 device_set_desc(dev, "SP804 System Timer");
190 return (BUS_PROBE_DEFAULT);
197 sp804_timer_attach(device_t dev)
199 struct sp804_timer_softc *sc = device_get_softc(dev);
206 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
207 if (sc->mem_res == NULL) {
208 device_printf(dev, "could not allocate memory resource\n");
212 sc->bst = rman_get_bustag(sc->mem_res);
213 sc->bsh = rman_get_bushandle(sc->mem_res);
215 /* Request the IRQ resources */
216 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
217 if (sc->irq_res == NULL) {
218 device_printf(dev, "Error: could not allocate irq resources\n");
222 sc->sysclk_freq = DEFAULT_FREQUENCY;
223 /* Get the base clock frequency */
224 node = ofw_bus_get_node(dev);
225 if ((OF_getencprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
226 sc->sysclk_freq = clock;
229 /* Setup and enable the timer */
230 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
231 sp804_timer_intr, NULL, sc,
232 &sc->intr_hl) != 0) {
233 bus_release_resource(dev, SYS_RES_IRQ, rid,
235 device_printf(dev, "Unable to setup the clock irq handler.\n");
239 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0);
240 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0);
243 * Timer 1, timecounter
245 sc->tc.tc_frequency = sc->sysclk_freq;
246 sc->tc.tc_name = "SP804-1";
247 sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount;
248 sc->tc.tc_poll_pps = NULL;
249 sc->tc.tc_counter_mask = ~0u;
250 sc->tc.tc_quality = 1000;
253 sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff);
254 sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff);
255 reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;
256 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
257 reg |= TIMER_CONTROL_EN;
258 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
262 * Timer 2, event timer
265 sc->et.et_name = "SP804-2";
266 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
267 sc->et.et_quality = 1000;
268 sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
269 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
270 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
271 sc->et.et_start = sp804_timer_start;
272 sc->et.et_stop = sp804_timer_stop;
274 et_register(&sc->et);
277 for (i = 3; i >= 0; i--) {
279 (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff);
282 device_printf(dev, "peripheral ID: %08x\n", id);
285 for (i = 3; i >= 0; i--) {
287 (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff);
290 device_printf(dev, "PrimeCell ID: %08x\n", id);
292 sc->timer_initialized = 1;
297 static device_method_t sp804_timer_methods[] = {
298 DEVMETHOD(device_probe, sp804_timer_probe),
299 DEVMETHOD(device_attach, sp804_timer_attach),
303 static driver_t sp804_timer_driver = {
306 sizeof(struct sp804_timer_softc),
309 static devclass_t sp804_timer_devclass;
311 DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0);
317 uint32_t first, last;
319 struct sp804_timer_softc *sc;
320 int timer_initialized = 0;
322 timer_dev = devclass_get_device(sp804_timer_devclass, 0);
325 sc = device_get_softc(timer_dev);
328 timer_initialized = sc->timer_initialized;
331 if (!timer_initialized) {
333 * Timer is not initialized yet
335 for (; usec > 0; usec--)
336 for (counts = 200; counts > 0; counts--)
337 /* Prevent gcc from optimizing out the loop */
342 /* Get the number of times to count */
343 counts = usec * ((sc->tc.tc_frequency / 1000000) + 1);
345 first = sp804_timer_tc_get_timecount(&sc->tc);
348 last = sp804_timer_tc_get_timecount(&sc->tc);
352 counts -= (int32_t)(last - first);
354 counts -= (int32_t)((0xFFFFFFFF - first) + last);