2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/watchdog.h>
42 #include <machine/bus.h>
43 #include <machine/cpu.h>
44 #include <machine/intr.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcib_private.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
56 #include <machine/bus.h>
57 #include <machine/fdt.h>
62 #define MEM_CONF_BASE 3
65 #define SYS_PCICTL 0x00
67 #define PCI_CORE_IMAP0 0x00
68 #define PCI_CORE_IMAP1 0x04
69 #define PCI_CORE_IMAP2 0x08
70 #define PCI_CORE_SELFID 0x0C
71 #define PCI_CORE_SMAP0 0x10
72 #define PCI_CORE_SMAP1 0x14
73 #define PCI_CORE_SMAP2 0x18
75 #define VERSATILE_PCI_DEV 0x030010ee
76 #define VERSATILE_PCI_CLASS 0x0b400000
78 #define PCI_IO_WINDOW 0x44000000
79 #define PCI_IO_SIZE 0x0c000000
80 #define PCI_NPREFETCH_WINDOW 0x50000000
81 #define PCI_NPREFETCH_SIZE 0x10000000
82 #define PCI_PREFETCH_WINDOW 0x60000000
83 #define PCI_PREFETCH_SIZE 0x10000000
85 #define VERSATILE_PCI_IRQ_START 27
86 #define VERSATILE_PCI_IRQ_END 30
89 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
90 printf(fmt,##args); } while (0)
92 #define dprintf(fmt, args...)
96 #define versatile_pci_sys_read_4(reg) \
97 bus_read_4(sc->mem_res[MEM_SYS], (reg))
98 #define versatile_pci_sys_write_4(reg, val) \
99 bus_write_4(sc->mem_res[MEM_SYS], (reg), (val))
101 #define versatile_pci_core_read_4(reg) \
102 bus_read_4(sc->mem_res[MEM_CORE], (reg))
103 #define versatile_pci_core_write_4(reg, val) \
104 bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
106 #define versatile_pci_read_4(reg) \
107 bus_read_4(sc->mem_res[MEM_BASE], (reg))
108 #define versatile_pci_write_4(reg, val) \
109 bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
111 #define versatile_pci_conf_read_4(reg) \
112 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
113 #define versatile_pci_conf_write_4(reg, val) \
114 bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
115 #define versatile_pci_conf_write_2(reg, val) \
116 bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
117 #define versatile_pci_conf_write_1(reg, val) \
118 bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
120 struct versatile_pci_softc {
121 struct resource* mem_res[MEM_REGIONS];
122 struct resource* irq_res;
130 struct rman irq_rman;
131 struct rman mem_rman;
136 static struct resource_spec versatile_pci_mem_spec[] = {
137 { SYS_RES_MEMORY, 0, RF_ACTIVE },
138 { SYS_RES_MEMORY, 1, RF_ACTIVE },
139 { SYS_RES_MEMORY, 2, RF_ACTIVE },
140 { SYS_RES_MEMORY, 3, RF_ACTIVE },
145 versatile_pci_probe(device_t dev)
148 if (!ofw_bus_status_okay(dev))
151 if (ofw_bus_is_compatible(dev, "versatile,pci")) {
152 device_set_desc(dev, "Versatile PCI controller");
153 return (BUS_PROBE_DEFAULT);
160 versatile_pci_attach(device_t dev)
162 struct versatile_pci_softc *sc = device_get_softc(dev);
165 uint32_t vendordev_id, class_id;
168 /* Request memory resources */
169 err = bus_alloc_resources(dev, versatile_pci_mem_spec,
172 device_printf(dev, "Error: could not allocate memory resources\n");
177 * Setup memory windows
179 versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
180 versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
181 versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
184 * XXX: this is SDRAM offset >> 28
185 * Unused as of QEMU 1.5
187 versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
188 versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
189 versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
191 versatile_pci_sys_write_4(SYS_PCICTL, 1);
193 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
194 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
195 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
196 if ((vendordev_id == VERSATILE_PCI_DEV) &&
197 (class_id == VERSATILE_PCI_CLASS))
201 if (slot == (PCI_SLOTMAX + 1)) {
202 bus_release_resources(dev, versatile_pci_mem_spec,
204 device_printf(dev, "Versatile PCI core not found\n");
208 sc->pcib_slot = slot;
209 device_printf(dev, "PCI core at slot #%d\n", slot);
211 versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
212 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
213 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
214 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
216 /* Again SDRAM start >> 28 */
217 versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
218 versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
219 versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
221 /* Prepare resource managers */
222 sc->mem_rman.rm_type = RMAN_ARRAY;
223 sc->mem_rman.rm_descr = "versatile PCI memory window";
224 if (rman_init(&sc->mem_rman) != 0 ||
225 rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW,
226 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
227 panic("versatile_pci_attach: failed to set up memory rman");
231 sc->io_rman.rm_type = RMAN_ARRAY;
232 sc->io_rman.rm_descr = "versatile PCI IO window";
233 if (rman_init(&sc->io_rman) != 0 ||
234 rman_manage_region(&sc->io_rman, PCI_IO_WINDOW,
235 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
236 panic("versatile_pci_attach: failed to set up I/O rman");
239 sc->irq_rman.rm_type = RMAN_ARRAY;
240 sc->irq_rman.rm_descr = "versatile PCI IRQs";
241 if (rman_init(&sc->irq_rman) != 0 ||
242 rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START,
243 VERSATILE_PCI_IRQ_END) != 0) {
244 panic("versatile_pci_attach: failed to set up IRQ rman");
247 mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
250 val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
252 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
253 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
254 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
256 if (slot == sc->pcib_slot)
259 if ((vendordev_id == 0xffffffff) &&
260 (class_id == 0xffffffff))
263 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
264 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
265 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
268 device_add_child(dev, "pci", -1);
269 return (bus_generic_attach(dev));
273 versatile_pci_read_ivar(device_t dev, device_t child, int which,
276 struct versatile_pci_softc *sc = device_get_softc(dev);
279 case PCIB_IVAR_DOMAIN:
291 versatile_pci_write_ivar(device_t dev, device_t child, int which,
294 struct versatile_pci_softc * sc = device_get_softc(dev);
305 static struct resource *
306 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
307 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
310 struct versatile_pci_softc *sc = device_get_softc(bus);
314 dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
330 rv = rman_reserve_resource(rm, start, end, count, flags, child);
335 rman_set_rid(rv, *rid);
337 if (flags & RF_ACTIVE) {
338 if (bus_activate_resource(child, type, *rid, rv)) {
339 rman_release_resource(rv);
347 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
356 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
358 rman_set_bushandle(r, vaddr);
359 rman_set_bustag(r, fdtbus_bs_tag);
360 res = rman_activate_resource(r);
363 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
364 child, type, rid, r));
375 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
376 int flags, driver_filter_t *filt, driver_intr_t *handler,
377 void *arg, void **cookiep)
380 return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
381 filt, handler, arg, cookiep);
385 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
389 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
395 versatile_pci_maxslots(device_t dev)
398 return (PCI_SLOTMAX);
402 versatile_pci_route_interrupt(device_t pcib, device_t device, int pin)
405 return (27 + ((pci_get_slot(device) + pin - 1) & 3));
409 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
410 u_int reg, int bytes)
412 struct versatile_pci_softc *sc = device_get_softc(dev);
414 uint32_t shift, mask;
417 if (sc->pcib_slot == slot) {
431 addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
433 /* register access is 32-bit aligned */
434 shift = (reg & 3) * 8;
436 /* Create a mask based on the width, post-shift */
444 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
447 mtx_lock_spin(&sc->mtx);
448 data = versatile_pci_conf_read_4(addr);
449 mtx_unlock_spin(&sc->mtx);
451 /* get request bytes from 32-bit word */
452 data = (data >> shift) & mask;
454 dprintf("%s: read 0x%x\n", __func__, data);
460 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
461 u_int reg, uint32_t data, int bytes)
464 struct versatile_pci_softc *sc = device_get_softc(dev);
467 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
470 if (sc->pcib_slot == slot)
473 addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
474 mtx_lock_spin(&sc->mtx);
477 versatile_pci_conf_write_4(addr, data);
480 versatile_pci_conf_write_2(addr, data);
483 versatile_pci_conf_write_1(addr, data);
486 mtx_unlock_spin(&sc->mtx);
489 static device_method_t versatile_pci_methods[] = {
490 DEVMETHOD(device_probe, versatile_pci_probe),
491 DEVMETHOD(device_attach, versatile_pci_attach),
494 DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar),
495 DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar),
496 DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource),
497 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
498 DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
499 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
500 DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr),
501 DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr),
504 DEVMETHOD(pcib_maxslots, versatile_pci_maxslots),
505 DEVMETHOD(pcib_read_config, versatile_pci_read_config),
506 DEVMETHOD(pcib_write_config, versatile_pci_write_config),
507 DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
512 static driver_t versatile_pci_driver = {
514 versatile_pci_methods,
515 sizeof(struct versatile_pci_softc),
518 static devclass_t versatile_pci_devclass;
520 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);