2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/watchdog.h>
42 #include <machine/bus.h>
43 #include <machine/cpu.h>
44 #include <machine/intr.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcib_private.h>
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
57 #include <machine/bus.h>
58 #include <machine/fdt.h>
63 #define MEM_CONF_BASE 3
66 #define SYS_PCICTL 0x00
68 #define PCI_CORE_IMAP0 0x00
69 #define PCI_CORE_IMAP1 0x04
70 #define PCI_CORE_IMAP2 0x08
71 #define PCI_CORE_SELFID 0x0C
72 #define PCI_CORE_SMAP0 0x10
73 #define PCI_CORE_SMAP1 0x14
74 #define PCI_CORE_SMAP2 0x18
76 #define VERSATILE_PCI_DEV 0x030010ee
77 #define VERSATILE_PCI_CLASS 0x0b400000
79 #define PCI_IO_WINDOW 0x44000000
80 #define PCI_IO_SIZE 0x0c000000
81 #define PCI_NPREFETCH_WINDOW 0x50000000
82 #define PCI_NPREFETCH_SIZE 0x10000000
83 #define PCI_PREFETCH_WINDOW 0x60000000
84 #define PCI_PREFETCH_SIZE 0x10000000
86 #define VERSATILE_PCI_IRQ_START 27
87 #define VERSATILE_PCI_IRQ_END 30
90 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
91 printf(fmt,##args); } while (0)
93 #define dprintf(fmt, args...)
97 #define versatile_pci_sys_read_4(reg) \
98 bus_read_4(sc->mem_res[MEM_SYS], (reg))
99 #define versatile_pci_sys_write_4(reg, val) \
100 bus_write_4(sc->mem_res[MEM_SYS], (reg), (val))
102 #define versatile_pci_core_read_4(reg) \
103 bus_read_4(sc->mem_res[MEM_CORE], (reg))
104 #define versatile_pci_core_write_4(reg, val) \
105 bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
107 #define versatile_pci_read_4(reg) \
108 bus_read_4(sc->mem_res[MEM_BASE], (reg))
109 #define versatile_pci_write_4(reg, val) \
110 bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
112 #define versatile_pci_conf_read_4(reg) \
113 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
114 #define versatile_pci_conf_write_4(reg, val) \
115 bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
116 #define versatile_pci_conf_write_2(reg, val) \
117 bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
118 #define versatile_pci_conf_write_1(reg, val) \
119 bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
121 struct versatile_pci_softc {
122 struct resource* mem_res[MEM_REGIONS];
123 struct resource* irq_res;
131 struct rman irq_rman;
132 struct rman mem_rman;
137 static struct resource_spec versatile_pci_mem_spec[] = {
138 { SYS_RES_MEMORY, 0, RF_ACTIVE },
139 { SYS_RES_MEMORY, 1, RF_ACTIVE },
140 { SYS_RES_MEMORY, 2, RF_ACTIVE },
141 { SYS_RES_MEMORY, 3, RF_ACTIVE },
146 versatile_pci_probe(device_t dev)
149 if (!ofw_bus_status_okay(dev))
152 if (ofw_bus_is_compatible(dev, "versatile,pci")) {
153 device_set_desc(dev, "Versatile PCI controller");
154 return (BUS_PROBE_DEFAULT);
161 versatile_pci_attach(device_t dev)
163 struct versatile_pci_softc *sc = device_get_softc(dev);
166 uint32_t vendordev_id, class_id;
169 /* Request memory resources */
170 err = bus_alloc_resources(dev, versatile_pci_mem_spec,
173 device_printf(dev, "Error: could not allocate memory resources\n");
178 * Setup memory windows
180 versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
181 versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
182 versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
185 * XXX: this is SDRAM offset >> 28
186 * Unused as of QEMU 1.5
188 versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
189 versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
190 versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
192 versatile_pci_sys_write_4(SYS_PCICTL, 1);
194 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
195 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
196 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
197 if ((vendordev_id == VERSATILE_PCI_DEV) &&
198 (class_id == VERSATILE_PCI_CLASS))
202 if (slot == (PCI_SLOTMAX + 1)) {
203 bus_release_resources(dev, versatile_pci_mem_spec,
205 device_printf(dev, "Versatile PCI core not found\n");
209 sc->pcib_slot = slot;
210 device_printf(dev, "PCI core at slot #%d\n", slot);
212 versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
213 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
214 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
215 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
217 /* Again SDRAM start >> 28 */
218 versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
219 versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
220 versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
222 /* Prepare resource managers */
223 sc->mem_rman.rm_type = RMAN_ARRAY;
224 sc->mem_rman.rm_descr = "versatile PCI memory window";
225 if (rman_init(&sc->mem_rman) != 0 ||
226 rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW,
227 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
228 panic("versatile_pci_attach: failed to set up memory rman");
232 sc->io_rman.rm_type = RMAN_ARRAY;
233 sc->io_rman.rm_descr = "versatile PCI IO window";
234 if (rman_init(&sc->io_rman) != 0 ||
235 rman_manage_region(&sc->io_rman, PCI_IO_WINDOW,
236 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
237 panic("versatile_pci_attach: failed to set up I/O rman");
240 sc->irq_rman.rm_type = RMAN_ARRAY;
241 sc->irq_rman.rm_descr = "versatile PCI IRQs";
242 if (rman_init(&sc->irq_rman) != 0 ||
243 rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START,
244 VERSATILE_PCI_IRQ_END) != 0) {
245 panic("versatile_pci_attach: failed to set up IRQ rman");
248 mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
251 val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
253 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
254 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
255 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
257 if (slot == sc->pcib_slot)
260 if ((vendordev_id == 0xffffffff) &&
261 (class_id == 0xffffffff))
264 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
265 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
266 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
269 device_add_child(dev, "pci", -1);
270 return (bus_generic_attach(dev));
274 versatile_pci_read_ivar(device_t dev, device_t child, int which,
277 struct versatile_pci_softc *sc = device_get_softc(dev);
280 case PCIB_IVAR_DOMAIN:
292 versatile_pci_write_ivar(device_t dev, device_t child, int which,
295 struct versatile_pci_softc * sc = device_get_softc(dev);
306 static struct resource *
307 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
308 u_long start, u_long end, u_long count, u_int flags)
311 struct versatile_pci_softc *sc = device_get_softc(bus);
315 dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
331 rv = rman_reserve_resource(rm, start, end, count, flags, child);
336 rman_set_rid(rv, *rid);
338 if (flags & RF_ACTIVE) {
339 if (bus_activate_resource(child, type, *rid, rv)) {
340 rman_release_resource(rv);
348 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
357 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
359 rman_set_bushandle(r, vaddr);
360 rman_set_bustag(r, arm_base_bs_tag);
361 res = rman_activate_resource(r);
364 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
365 child, type, rid, r));
376 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
377 int flags, driver_filter_t *filt, driver_intr_t *handler,
378 void *arg, void **cookiep)
381 return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
382 filt, handler, arg, cookiep);
386 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
390 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
396 versatile_pci_maxslots(device_t dev)
399 return (PCI_SLOTMAX);
403 versatile_pci_route_interrupt(device_t pcib, device_t device, int pin)
406 return (27 + ((pci_get_slot(device) + pin - 1) & 3));
410 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
411 u_int reg, int bytes)
413 struct versatile_pci_softc *sc = device_get_softc(dev);
415 uint32_t shift, mask;
418 if (sc->pcib_slot == slot) {
432 addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
434 /* register access is 32-bit aligned */
435 shift = (reg & 3) * 8;
437 /* Create a mask based on the width, post-shift */
445 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
448 mtx_lock_spin(&sc->mtx);
449 data = versatile_pci_conf_read_4(addr);
450 mtx_unlock_spin(&sc->mtx);
452 /* get request bytes from 32-bit word */
453 data = (data >> shift) & mask;
455 dprintf("%s: read 0x%x\n", __func__, data);
461 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
462 u_int reg, uint32_t data, int bytes)
465 struct versatile_pci_softc *sc = device_get_softc(dev);
468 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
471 if (sc->pcib_slot == slot)
474 addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
475 mtx_lock_spin(&sc->mtx);
478 versatile_pci_conf_write_4(addr, data);
481 versatile_pci_conf_write_2(addr, data);
484 versatile_pci_conf_write_1(addr, data);
487 mtx_unlock_spin(&sc->mtx);
490 static device_method_t versatile_pci_methods[] = {
491 DEVMETHOD(device_probe, versatile_pci_probe),
492 DEVMETHOD(device_attach, versatile_pci_attach),
495 DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar),
496 DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar),
497 DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource),
498 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
499 DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
500 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
501 DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr),
502 DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr),
505 DEVMETHOD(pcib_maxslots, versatile_pci_maxslots),
506 DEVMETHOD(pcib_read_config, versatile_pci_read_config),
507 DEVMETHOD(pcib_write_config, versatile_pci_write_config),
508 DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
513 static driver_t versatile_pci_driver = {
515 versatile_pci_methods,
516 sizeof(struct versatile_pci_softc),
519 static devclass_t versatile_pci_devclass;
521 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);