2 * Copyright (c) 2012-2017 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/watchdog.h>
42 #include <machine/bus.h>
43 #include <machine/cpu.h>
44 #include <machine/intr.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcib_private.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55 #include <dev/ofw/ofw_pci.h>
57 #include <arm/versatile/versatile_scm.h>
59 #include <machine/bus.h>
60 #include <machine/fdt.h>
64 #define MEM_CONF_BASE 2
67 #define PCI_CORE_IMAP0 0x00
68 #define PCI_CORE_IMAP1 0x04
69 #define PCI_CORE_IMAP2 0x08
70 #define PCI_CORE_SELFID 0x0C
71 #define PCI_CORE_SMAP0 0x10
72 #define PCI_CORE_SMAP1 0x14
73 #define PCI_CORE_SMAP2 0x18
75 #define VERSATILE_PCI_DEV 0x030010ee
76 #define VERSATILE_PCI_CLASS 0x0b400000
78 #define PCI_IO_WINDOW 0x44000000
79 #define PCI_IO_SIZE 0x0c000000
80 #define PCI_NPREFETCH_WINDOW 0x50000000
81 #define PCI_NPREFETCH_SIZE 0x10000000
82 #define PCI_PREFETCH_WINDOW 0x60000000
83 #define PCI_PREFETCH_SIZE 0x10000000
85 #define VERSATILE_PCI_IRQ_START 27
86 #define VERSATILE_PCI_IRQ_END 30
89 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
90 printf(fmt,##args); } while (0)
92 #define dprintf(fmt, args...)
95 #define versatile_pci_core_read_4(reg) \
96 bus_read_4(sc->mem_res[MEM_CORE], (reg))
97 #define versatile_pci_core_write_4(reg, val) \
98 bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
100 #define versatile_pci_read_4(reg) \
101 bus_read_4(sc->mem_res[MEM_BASE], (reg))
102 #define versatile_pci_write_4(reg, val) \
103 bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
105 #define versatile_pci_conf_read_4(reg) \
106 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
107 #define versatile_pci_conf_write_4(reg, val) \
108 bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
109 #define versatile_pci_conf_write_2(reg, val) \
110 bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
111 #define versatile_pci_conf_write_1(reg, val) \
112 bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
114 struct versatile_pci_softc {
115 struct resource* mem_res[MEM_REGIONS];
116 struct resource* irq_res;
124 struct rman irq_rman;
125 struct rman mem_rman;
128 struct ofw_bus_iinfo pci_iinfo;
131 static struct resource_spec versatile_pci_mem_spec[] = {
132 { SYS_RES_MEMORY, 0, RF_ACTIVE },
133 { SYS_RES_MEMORY, 1, RF_ACTIVE },
134 { SYS_RES_MEMORY, 2, RF_ACTIVE },
139 versatile_pci_probe(device_t dev)
142 if (!ofw_bus_status_okay(dev))
145 if (ofw_bus_is_compatible(dev, "arm,versatile-pci")) {
146 device_set_desc(dev, "Versatile PCI controller");
147 return (BUS_PROBE_DEFAULT);
154 versatile_pci_attach(device_t dev)
156 struct versatile_pci_softc *sc = device_get_softc(dev);
159 uint32_t vendordev_id, class_id;
163 node = ofw_bus_get_node(dev);
165 /* Request memory resources */
166 err = bus_alloc_resources(dev, versatile_pci_mem_spec,
169 device_printf(dev, "Error: could not allocate memory resources\n");
174 * Setup memory windows
176 versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
177 versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
178 versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
181 * XXX: this is SDRAM offset >> 28
182 * Unused as of QEMU 1.5
184 versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
185 versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
186 versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
188 versatile_scm_reg_write_4(SCM_PCICTL, 1);
190 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
191 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
192 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
193 if ((vendordev_id == VERSATILE_PCI_DEV) &&
194 (class_id == VERSATILE_PCI_CLASS))
198 if (slot == (PCI_SLOTMAX + 1)) {
199 bus_release_resources(dev, versatile_pci_mem_spec,
201 device_printf(dev, "Versatile PCI core not found\n");
205 sc->pcib_slot = slot;
206 device_printf(dev, "PCI core at slot #%d\n", slot);
208 versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
209 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
210 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
211 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
213 /* Again SDRAM start >> 28 */
214 versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
215 versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
216 versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
218 /* Prepare resource managers */
219 sc->mem_rman.rm_type = RMAN_ARRAY;
220 sc->mem_rman.rm_descr = "versatile PCI memory window";
221 if (rman_init(&sc->mem_rman) != 0 ||
222 rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW,
223 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
224 panic("versatile_pci_attach: failed to set up memory rman");
228 sc->io_rman.rm_type = RMAN_ARRAY;
229 sc->io_rman.rm_descr = "versatile PCI IO window";
230 if (rman_init(&sc->io_rman) != 0 ||
231 rman_manage_region(&sc->io_rman, PCI_IO_WINDOW,
232 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
233 panic("versatile_pci_attach: failed to set up I/O rman");
236 sc->irq_rman.rm_type = RMAN_ARRAY;
237 sc->irq_rman.rm_descr = "versatile PCI IRQs";
238 if (rman_init(&sc->irq_rman) != 0 ||
239 rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START,
240 VERSATILE_PCI_IRQ_END) != 0) {
241 panic("versatile_pci_attach: failed to set up IRQ rman");
244 mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
247 val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
249 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
250 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
251 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
253 if (slot == sc->pcib_slot)
256 if ((vendordev_id == 0xffffffff) &&
257 (class_id == 0xffffffff))
260 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
261 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
262 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
265 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
267 device_add_child(dev, "pci", -1);
268 return (bus_generic_attach(dev));
272 versatile_pci_read_ivar(device_t dev, device_t child, int which,
275 struct versatile_pci_softc *sc = device_get_softc(dev);
278 case PCIB_IVAR_DOMAIN:
290 versatile_pci_write_ivar(device_t dev, device_t child, int which,
293 struct versatile_pci_softc * sc = device_get_softc(dev);
304 static struct resource *
305 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
306 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
309 struct versatile_pci_softc *sc = device_get_softc(bus);
313 dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
330 return (BUS_ALLOC_RESOURCE(device_get_parent(bus),
331 child, type, rid, start, end, count, flags));
333 rv = rman_reserve_resource(rm, start, end, count, flags, child);
337 rman_set_rid(rv, *rid);
339 if (flags & RF_ACTIVE) {
340 if (bus_activate_resource(child, type, *rid, rv)) {
341 rman_release_resource(rv);
349 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
358 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
360 rman_set_bushandle(r, vaddr);
361 rman_set_bustag(r, fdtbus_bs_tag);
362 res = rman_activate_resource(r);
365 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
366 child, type, rid, r));
377 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
378 int flags, driver_filter_t *filt, driver_intr_t *handler,
379 void *arg, void **cookiep)
382 return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
383 filt, handler, arg, cookiep);
387 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
391 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
395 versatile_pci_maxslots(device_t dev)
398 return (PCI_SLOTMAX);
402 versatile_pci_route_interrupt(device_t bus, device_t dev, int pin)
404 struct versatile_pci_softc *sc;
405 struct ofw_pci_register reg;
406 uint32_t pintr, mintr[4];
410 sc = device_get_softc(bus);
413 bzero(®, sizeof(reg));
414 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
415 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
416 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
418 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
419 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
420 mintr, sizeof(mintr), &iparent);
422 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
426 device_printf(bus, "could not route pin %d for device %d.%d\n",
427 pin, pci_get_slot(dev), pci_get_function(dev));
428 return (PCI_INVALID_IRQ);
432 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
433 u_int reg, int bytes)
435 struct versatile_pci_softc *sc = device_get_softc(dev);
437 uint32_t shift, mask;
440 if (sc->pcib_slot == slot) {
454 addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
456 /* register access is 32-bit aligned */
457 shift = (reg & 3) * 8;
459 /* Create a mask based on the width, post-shift */
467 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
470 mtx_lock_spin(&sc->mtx);
471 data = versatile_pci_conf_read_4(addr);
472 mtx_unlock_spin(&sc->mtx);
474 /* get request bytes from 32-bit word */
475 data = (data >> shift) & mask;
477 dprintf("%s: read 0x%x\n", __func__, data);
483 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
484 u_int reg, uint32_t data, int bytes)
487 struct versatile_pci_softc *sc = device_get_softc(dev);
490 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
493 if (sc->pcib_slot == slot)
496 addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
497 mtx_lock_spin(&sc->mtx);
500 versatile_pci_conf_write_4(addr, data);
503 versatile_pci_conf_write_2(addr, data);
506 versatile_pci_conf_write_1(addr, data);
509 mtx_unlock_spin(&sc->mtx);
512 static device_method_t versatile_pci_methods[] = {
513 DEVMETHOD(device_probe, versatile_pci_probe),
514 DEVMETHOD(device_attach, versatile_pci_attach),
517 DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar),
518 DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar),
519 DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource),
520 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
521 DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
522 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
523 DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr),
524 DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr),
527 DEVMETHOD(pcib_maxslots, versatile_pci_maxslots),
528 DEVMETHOD(pcib_read_config, versatile_pci_read_config),
529 DEVMETHOD(pcib_write_config, versatile_pci_write_config),
530 DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
531 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
536 static driver_t versatile_pci_driver = {
538 versatile_pci_methods,
539 sizeof(struct versatile_pci_softc),
542 static devclass_t versatile_pci_devclass;
544 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);