2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012-2017 Oleksandr Tymoshenko <gonzo@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
39 #include <sys/watchdog.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
46 #include <machine/intr.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
57 #include <dev/ofw/ofw_pci.h>
59 #include <arm/versatile/versatile_scm.h>
61 #include <machine/bus.h>
62 #include <machine/fdt.h>
66 #define MEM_CONF_BASE 2
69 #define PCI_CORE_IMAP0 0x00
70 #define PCI_CORE_IMAP1 0x04
71 #define PCI_CORE_IMAP2 0x08
72 #define PCI_CORE_SELFID 0x0C
73 #define PCI_CORE_SMAP0 0x10
74 #define PCI_CORE_SMAP1 0x14
75 #define PCI_CORE_SMAP2 0x18
77 #define VERSATILE_PCI_DEV 0x030010ee
78 #define VERSATILE_PCI_CLASS 0x0b400000
80 #define PCI_IO_WINDOW 0x44000000
81 #define PCI_IO_SIZE 0x0c000000
82 #define PCI_NPREFETCH_WINDOW 0x50000000
83 #define PCI_NPREFETCH_SIZE 0x10000000
84 #define PCI_PREFETCH_WINDOW 0x60000000
85 #define PCI_PREFETCH_SIZE 0x10000000
87 #define VERSATILE_PCI_IRQ_START 27
88 #define VERSATILE_PCI_IRQ_END 30
91 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
92 printf(fmt,##args); } while (0)
94 #define dprintf(fmt, args...)
97 #define versatile_pci_core_read_4(reg) \
98 bus_read_4(sc->mem_res[MEM_CORE], (reg))
99 #define versatile_pci_core_write_4(reg, val) \
100 bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
102 #define versatile_pci_read_4(reg) \
103 bus_read_4(sc->mem_res[MEM_BASE], (reg))
104 #define versatile_pci_write_4(reg, val) \
105 bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
107 #define versatile_pci_conf_read_4(reg) \
108 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
109 #define versatile_pci_conf_write_4(reg, val) \
110 bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
111 #define versatile_pci_conf_write_2(reg, val) \
112 bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
113 #define versatile_pci_conf_write_1(reg, val) \
114 bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
116 struct versatile_pci_softc {
117 struct resource* mem_res[MEM_REGIONS];
118 struct resource* irq_res;
126 struct rman irq_rman;
127 struct rman mem_rman;
130 struct ofw_bus_iinfo pci_iinfo;
133 static struct resource_spec versatile_pci_mem_spec[] = {
134 { SYS_RES_MEMORY, 0, RF_ACTIVE },
135 { SYS_RES_MEMORY, 1, RF_ACTIVE },
136 { SYS_RES_MEMORY, 2, RF_ACTIVE },
141 versatile_pci_probe(device_t dev)
144 if (!ofw_bus_status_okay(dev))
147 if (ofw_bus_is_compatible(dev, "arm,versatile-pci")) {
148 device_set_desc(dev, "Versatile PCI controller");
149 return (BUS_PROBE_DEFAULT);
156 versatile_pci_attach(device_t dev)
158 struct versatile_pci_softc *sc = device_get_softc(dev);
161 uint32_t vendordev_id, class_id;
165 node = ofw_bus_get_node(dev);
167 /* Request memory resources */
168 err = bus_alloc_resources(dev, versatile_pci_mem_spec,
171 device_printf(dev, "Error: could not allocate memory resources\n");
176 * Setup memory windows
178 versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
179 versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
180 versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
183 * XXX: this is SDRAM offset >> 28
184 * Unused as of QEMU 1.5
186 versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
187 versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
188 versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
190 versatile_scm_reg_write_4(SCM_PCICTL, 1);
192 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
193 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
194 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
195 if ((vendordev_id == VERSATILE_PCI_DEV) &&
196 (class_id == VERSATILE_PCI_CLASS))
200 if (slot == (PCI_SLOTMAX + 1)) {
201 bus_release_resources(dev, versatile_pci_mem_spec,
203 device_printf(dev, "Versatile PCI core not found\n");
207 sc->pcib_slot = slot;
208 device_printf(dev, "PCI core at slot #%d\n", slot);
210 versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
211 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
212 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
213 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
215 /* Again SDRAM start >> 28 */
216 versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
217 versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
218 versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
220 /* Prepare resource managers */
221 sc->mem_rman.rm_type = RMAN_ARRAY;
222 sc->mem_rman.rm_descr = "versatile PCI memory window";
223 if (rman_init(&sc->mem_rman) != 0 ||
224 rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW,
225 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
226 panic("versatile_pci_attach: failed to set up memory rman");
230 sc->io_rman.rm_type = RMAN_ARRAY;
231 sc->io_rman.rm_descr = "versatile PCI IO window";
232 if (rman_init(&sc->io_rman) != 0 ||
233 rman_manage_region(&sc->io_rman, PCI_IO_WINDOW,
234 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
235 panic("versatile_pci_attach: failed to set up I/O rman");
238 sc->irq_rman.rm_type = RMAN_ARRAY;
239 sc->irq_rman.rm_descr = "versatile PCI IRQs";
240 if (rman_init(&sc->irq_rman) != 0 ||
241 rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START,
242 VERSATILE_PCI_IRQ_END) != 0) {
243 panic("versatile_pci_attach: failed to set up IRQ rman");
246 mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
249 val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
251 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
252 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
253 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
255 if (slot == sc->pcib_slot)
258 if ((vendordev_id == 0xffffffff) &&
259 (class_id == 0xffffffff))
262 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
263 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
264 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
267 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
269 device_add_child(dev, "pci", -1);
270 return (bus_generic_attach(dev));
274 versatile_pci_read_ivar(device_t dev, device_t child, int which,
277 struct versatile_pci_softc *sc = device_get_softc(dev);
280 case PCIB_IVAR_DOMAIN:
292 versatile_pci_write_ivar(device_t dev, device_t child, int which,
295 struct versatile_pci_softc * sc = device_get_softc(dev);
306 static struct resource *
307 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
308 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
311 struct versatile_pci_softc *sc = device_get_softc(bus);
315 dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
332 return (BUS_ALLOC_RESOURCE(device_get_parent(bus),
333 child, type, rid, start, end, count, flags));
335 rv = rman_reserve_resource(rm, start, end, count, flags, child);
339 rman_set_rid(rv, *rid);
341 if (flags & RF_ACTIVE) {
342 if (bus_activate_resource(child, type, *rid, rv)) {
343 rman_release_resource(rv);
351 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
360 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
362 rman_set_bushandle(r, vaddr);
363 rman_set_bustag(r, fdtbus_bs_tag);
364 res = rman_activate_resource(r);
367 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
368 child, type, rid, r));
379 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
380 int flags, driver_filter_t *filt, driver_intr_t *handler,
381 void *arg, void **cookiep)
384 return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
385 filt, handler, arg, cookiep);
389 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
393 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
397 versatile_pci_maxslots(device_t dev)
400 return (PCI_SLOTMAX);
404 versatile_pci_route_interrupt(device_t bus, device_t dev, int pin)
406 struct versatile_pci_softc *sc;
407 struct ofw_pci_register reg;
408 uint32_t pintr, mintr[4];
412 sc = device_get_softc(bus);
415 bzero(®, sizeof(reg));
416 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
417 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
418 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
420 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
421 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
422 mintr, sizeof(mintr), &iparent);
424 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
428 device_printf(bus, "could not route pin %d for device %d.%d\n",
429 pin, pci_get_slot(dev), pci_get_function(dev));
430 return (PCI_INVALID_IRQ);
434 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
435 u_int reg, int bytes)
437 struct versatile_pci_softc *sc = device_get_softc(dev);
439 uint32_t shift, mask;
442 if (sc->pcib_slot == slot) {
456 addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
458 /* register access is 32-bit aligned */
459 shift = (reg & 3) * 8;
461 /* Create a mask based on the width, post-shift */
469 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
472 mtx_lock_spin(&sc->mtx);
473 data = versatile_pci_conf_read_4(addr);
474 mtx_unlock_spin(&sc->mtx);
476 /* get request bytes from 32-bit word */
477 data = (data >> shift) & mask;
479 dprintf("%s: read 0x%x\n", __func__, data);
485 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
486 u_int reg, uint32_t data, int bytes)
489 struct versatile_pci_softc *sc = device_get_softc(dev);
492 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
495 if (sc->pcib_slot == slot)
498 addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
499 mtx_lock_spin(&sc->mtx);
502 versatile_pci_conf_write_4(addr, data);
505 versatile_pci_conf_write_2(addr, data);
508 versatile_pci_conf_write_1(addr, data);
511 mtx_unlock_spin(&sc->mtx);
514 static device_method_t versatile_pci_methods[] = {
515 DEVMETHOD(device_probe, versatile_pci_probe),
516 DEVMETHOD(device_attach, versatile_pci_attach),
519 DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar),
520 DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar),
521 DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource),
522 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
523 DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
524 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
525 DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr),
526 DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr),
529 DEVMETHOD(pcib_maxslots, versatile_pci_maxslots),
530 DEVMETHOD(pcib_read_config, versatile_pci_read_config),
531 DEVMETHOD(pcib_write_config, versatile_pci_write_config),
532 DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
533 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
538 static driver_t versatile_pci_driver = {
540 versatile_pci_methods,
541 sizeof(struct versatile_pci_softc),
544 static devclass_t versatile_pci_devclass;
546 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);