2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/watchdog.h>
38 #include <machine/bus.h>
39 #include <machine/cpu.h>
40 #include <machine/intr.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcib_private.h>
48 #include <dev/fdt/fdt_common.h>
49 #include <dev/ofw/openfirm.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
53 #include <machine/bus.h>
54 #include <machine/fdt.h>
56 #include <arm/versatile/versatile_pci_bus_space.h>
61 #define MEM_CONF_BASE 3
64 #define SYS_PCICTL 0x00
66 #define PCI_CORE_IMAP0 0x00
67 #define PCI_CORE_IMAP1 0x04
68 #define PCI_CORE_IMAP2 0x08
69 #define PCI_CORE_SELFID 0x0C
70 #define PCI_CORE_SMAP0 0x10
71 #define PCI_CORE_SMAP1 0x14
72 #define PCI_CORE_SMAP2 0x18
74 #define VERSATILE_PCI_DEV 0x030010ee
75 #define VERSATILE_PCI_CLASS 0x0b400000
77 #define PCI_IO_WINDOW 0x44000000
78 #define PCI_IO_SIZE 0x0c000000
79 #define PCI_NPREFETCH_WINDOW 0x50000000
80 #define PCI_NPREFETCH_SIZE 0x10000000
81 #define PCI_PREFETCH_WINDOW 0x60000000
82 #define PCI_PREFETCH_SIZE 0x10000000
84 #define VERSATILE_PCI_IRQ_START 27
85 #define VERSATILE_PCI_IRQ_END 30
88 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
89 printf(fmt,##args); } while (0)
91 #define dprintf(fmt, args...)
95 #define versatile_pci_sys_read_4(reg) \
96 bus_read_4(sc->mem_res[MEM_SYS], (reg))
97 #define versatile_pci_sys_write_4(reg, val) \
98 bus_write_4(sc->mem_res[MEM_SYS], (reg), (val))
100 #define versatile_pci_core_read_4(reg) \
101 bus_read_4(sc->mem_res[MEM_CORE], (reg))
102 #define versatile_pci_core_write_4(reg, val) \
103 bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
105 #define versatile_pci_read_4(reg) \
106 bus_read_4(sc->mem_res[MEM_BASE], (reg))
107 #define versatile_pci_write_4(reg, val) \
108 bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
110 #define versatile_pci_conf_read_4(reg) \
111 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
112 #define versatile_pci_conf_write_4(reg, val) \
113 bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
114 #define versatile_pci_conf_write_2(reg, val) \
115 bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
116 #define versatile_pci_conf_write_1(reg, val) \
117 bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
119 struct versatile_pci_softc {
120 struct resource* mem_res[MEM_REGIONS];
121 struct resource* irq_res;
129 struct rman irq_rman;
130 struct rman mem_rman;
135 static struct resource_spec versatile_pci_mem_spec[] = {
136 { SYS_RES_MEMORY, 0, RF_ACTIVE },
137 { SYS_RES_MEMORY, 1, RF_ACTIVE },
138 { SYS_RES_MEMORY, 2, RF_ACTIVE },
139 { SYS_RES_MEMORY, 3, RF_ACTIVE },
144 versatile_pci_probe(device_t dev)
147 if (ofw_bus_is_compatible(dev, "versatile,pci")) {
148 device_set_desc(dev, "Versatile PCI controller");
149 return (BUS_PROBE_DEFAULT);
156 versatile_pci_attach(device_t dev)
158 struct versatile_pci_softc *sc = device_get_softc(dev);
161 uint32_t vendordev_id, class_id;
164 /* Request memory resources */
165 err = bus_alloc_resources(dev, versatile_pci_mem_spec,
168 device_printf(dev, "Error: could not allocate memory resources\n");
173 * Setup memory windows
175 versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
176 versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
177 versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
180 * XXX: this is SDRAM offset >> 28
181 * Unused as of QEMU 1.5
183 versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
184 versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
185 versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
187 versatile_pci_sys_write_4(SYS_PCICTL, 1);
189 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
190 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
191 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
192 if ((vendordev_id == VERSATILE_PCI_DEV) &&
193 (class_id == VERSATILE_PCI_CLASS))
197 if (slot == (PCI_SLOTMAX + 1)) {
198 bus_release_resources(dev, versatile_pci_mem_spec,
200 device_printf(dev, "Versatile PCI core not found\n");
204 sc->pcib_slot = slot;
205 device_printf(dev, "PCI core at slot #%d\n", slot);
207 versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
208 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
209 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
210 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
212 /* Again SDRAM start >> 28 */
213 versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
214 versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
215 versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
217 /* Prepare resource managers */
218 sc->mem_rman.rm_type = RMAN_ARRAY;
219 sc->mem_rman.rm_descr = "versatile PCI memory window";
220 if (rman_init(&sc->mem_rman) != 0 ||
221 rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW,
222 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
223 panic("versatile_pci_attach: failed to set up memory rman");
227 sc->io_rman.rm_type = RMAN_ARRAY;
228 sc->io_rman.rm_descr = "versatile PCI IO window";
229 if (rman_init(&sc->io_rman) != 0 ||
230 rman_manage_region(&sc->io_rman, PCI_IO_WINDOW,
231 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
232 panic("versatile_pci_attach: failed to set up I/O rman");
235 sc->irq_rman.rm_type = RMAN_ARRAY;
236 sc->irq_rman.rm_descr = "versatile PCI IRQs";
237 if (rman_init(&sc->irq_rman) != 0 ||
238 rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START,
239 VERSATILE_PCI_IRQ_END) != 0) {
240 panic("versatile_pci_attach: failed to set up IRQ rman");
243 mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
246 val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
248 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
249 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
250 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
252 if (slot == sc->pcib_slot)
255 if ((vendordev_id == 0xffffffff) &&
256 (class_id == 0xffffffff))
259 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
260 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
261 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
264 device_add_child(dev, "pci", 0);
265 return (bus_generic_attach(dev));
269 versatile_pci_read_ivar(device_t dev, device_t child, int which,
272 struct versatile_pci_softc *sc = device_get_softc(dev);
275 case PCIB_IVAR_DOMAIN:
287 versatile_pci_write_ivar(device_t dev, device_t child, int which,
290 struct versatile_pci_softc * sc = device_get_softc(dev);
301 static struct resource *
302 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
303 u_long start, u_long end, u_long count, u_int flags)
306 struct versatile_pci_softc *sc = device_get_softc(bus);
310 dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
326 rv = rman_reserve_resource(rm, start, end, count, flags, child);
331 rman_set_rid(rv, *rid);
333 if (flags & RF_ACTIVE) {
334 if (bus_activate_resource(child, type, *rid, rv)) {
335 rman_release_resource(rv);
343 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
352 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
354 rman_set_bushandle(r, vaddr);
355 rman_set_bustag(r, versatile_bus_space_pcimem);
356 res = rman_activate_resource(r);
359 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
360 child, type, rid, r));
371 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
372 int flags, driver_filter_t *filt, driver_intr_t *handler,
373 void *arg, void **cookiep)
376 return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
377 filt, handler, arg, cookiep);
381 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
385 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
391 versatile_pci_maxslots(device_t dev)
394 return (PCI_SLOTMAX);
398 versatile_pci_route_interrupt(device_t pcib, device_t device, int pin)
401 return (27 + ((pci_get_slot(device) + pin - 1) & 3));
405 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
406 u_int reg, int bytes)
408 struct versatile_pci_softc *sc = device_get_softc(dev);
410 uint32_t shift, mask;
413 if (sc->pcib_slot == slot) {
427 addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
429 /* register access is 32-bit aligned */
430 shift = (reg & 3) * 8;
432 /* Create a mask based on the width, post-shift */
440 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
443 mtx_lock_spin(&sc->mtx);
444 data = versatile_pci_conf_read_4(addr);
445 mtx_unlock_spin(&sc->mtx);
447 /* get request bytes from 32-bit word */
448 data = (data >> shift) & mask;
450 dprintf("%s: read 0x%x\n", __func__, data);
456 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
457 u_int reg, uint32_t data, int bytes)
460 struct versatile_pci_softc *sc = device_get_softc(dev);
463 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
466 if (sc->pcib_slot == slot)
469 addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
470 mtx_lock_spin(&sc->mtx);
473 versatile_pci_conf_write_4(addr, data);
476 versatile_pci_conf_write_2(addr, data);
479 versatile_pci_conf_write_1(addr, data);
482 mtx_unlock_spin(&sc->mtx);
485 static device_method_t versatile_pci_methods[] = {
486 DEVMETHOD(device_probe, versatile_pci_probe),
487 DEVMETHOD(device_attach, versatile_pci_attach),
490 DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar),
491 DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar),
492 DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource),
493 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
494 DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
495 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
496 DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr),
497 DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr),
500 DEVMETHOD(pcib_maxslots, versatile_pci_maxslots),
501 DEVMETHOD(pcib_read_config, versatile_pci_read_config),
502 DEVMETHOD(pcib_write_config, versatile_pci_write_config),
503 DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
508 static driver_t versatile_pci_driver = {
510 versatile_pci_methods,
511 sizeof(struct versatile_pci_softc),
514 static devclass_t versatile_pci_devclass;
516 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);