2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2005 Olivier Houchard All rights reserved.
5 * Copyright (c) 2012 Thomas Skibo All rights reserved.
6 * Copyright (c) 2005 M. Warner Losh <imp@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585. UART is covered in Ch. 19
35 * and register definitions are in appendix B.33.
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/systm.h>
47 #include <machine/bus.h>
49 #include <dev/uart/uart.h>
50 #include <dev/uart/uart_cpu.h>
51 #include <dev/uart/uart_cpu_fdt.h>
52 #include <dev/uart/uart_bus.h>
56 #define UART_FIFO_SIZE 64
58 #define RD4(bas, reg) \
59 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)))
60 #define WR4(bas, reg, value) \
61 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \
64 /* Register definitions for Cadence UART Controller.
66 #define CDNC_UART_CTRL_REG 0x00 /* Control Register. */
67 #define CDNC_UART_CTRL_REG_STOPBRK (1<<8)
68 #define CDNC_UART_CTRL_REG_STARTBRK (1<<7)
69 #define CDNC_UART_CTRL_REG_TORST (1<<6)
70 #define CDNC_UART_CTRL_REG_TX_DIS (1<<5)
71 #define CDNC_UART_CTRL_REG_TX_EN (1<<4)
72 #define CDNC_UART_CTRL_REG_RX_DIS (1<<3)
73 #define CDNC_UART_CTRL_REG_RX_EN (1<<2)
74 #define CDNC_UART_CTRL_REG_TXRST (1<<1)
75 #define CDNC_UART_CTRL_REG_RXRST (1<<0)
77 #define CDNC_UART_MODE_REG 0x04 /* Mode Register. */
78 #define CDNC_UART_MODE_REG_CHMOD_R_LOOP (3<<8) /* [9:8] - channel mode */
79 #define CDNC_UART_MODE_REG_CHMOD_L_LOOP (2<<8)
80 #define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8)
81 #define CDNC_UART_MODE_REG_STOP2 (2<<6) /* [7:6] - stop bits */
82 #define CDNC_UART_MODE_REG_PAR_NONE (4<<3) /* [5:3] - parity type */
83 #define CDNC_UART_MODE_REG_PAR_MARK (3<<3)
84 #define CDNC_UART_MODE_REG_PAR_SPACE (2<<3)
85 #define CDNC_UART_MODE_REG_PAR_ODD (1<<3)
86 #define CDNC_UART_MODE_REG_PAR_EVEN (0<<3)
87 #define CDNC_UART_MODE_REG_6BIT (3<<1) /* [2:1] - character len */
88 #define CDNC_UART_MODE_REG_7BIT (2<<1)
89 #define CDNC_UART_MODE_REG_8BIT (0<<1)
90 #define CDNC_UART_MODE_REG_CLKSEL (1<<0)
92 #define CDNC_UART_IEN_REG 0x08 /* Interrupt registers. */
93 #define CDNC_UART_IDIS_REG 0x0C
94 #define CDNC_UART_IMASK_REG 0x10
95 #define CDNC_UART_ISTAT_REG 0x14
96 #define CDNC_UART_INT_TXOVR (1<<12)
97 #define CDNC_UART_INT_TXNRLYFUL (1<<11) /* tx "nearly" full */
98 #define CDNC_UART_INT_TXTRIG (1<<10)
99 #define CDNC_UART_INT_DMSI (1<<9) /* delta modem status */
100 #define CDNC_UART_INT_RXTMOUT (1<<8)
101 #define CDNC_UART_INT_PARITY (1<<7)
102 #define CDNC_UART_INT_FRAMING (1<<6)
103 #define CDNC_UART_INT_RXOVR (1<<5)
104 #define CDNC_UART_INT_TXFULL (1<<4)
105 #define CDNC_UART_INT_TXEMPTY (1<<3)
106 #define CDNC_UART_INT_RXFULL (1<<2)
107 #define CDNC_UART_INT_RXEMPTY (1<<1)
108 #define CDNC_UART_INT_RXTRIG (1<<0)
109 #define CDNC_UART_INT_ALL 0x1FFF
111 #define CDNC_UART_BAUDGEN_REG 0x18
112 #define CDNC_UART_RX_TIMEO_REG 0x1C
113 #define CDNC_UART_RX_WATER_REG 0x20
115 #define CDNC_UART_MODEM_CTRL_REG 0x24
116 #define CDNC_UART_MODEM_CTRL_REG_FCM (1<<5) /* automatic flow control */
117 #define CDNC_UART_MODEM_CTRL_REG_RTS (1<<1)
118 #define CDNC_UART_MODEM_CTRL_REG_DTR (1<<0)
120 #define CDNC_UART_MODEM_STAT_REG 0x28
121 #define CDNC_UART_MODEM_STAT_REG_FCMS (1<<8) /* flow control mode (rw) */
122 #define CDNC_UART_MODEM_STAT_REG_DCD (1<<7)
123 #define CDNC_UART_MODEM_STAT_REG_RI (1<<6)
124 #define CDNC_UART_MODEM_STAT_REG_DSR (1<<5)
125 #define CDNC_UART_MODEM_STAT_REG_CTS (1<<4)
126 #define CDNC_UART_MODEM_STAT_REG_DDCD (1<<3) /* change in DCD (w1tc) */
127 #define CDNC_UART_MODEM_STAT_REG_TERI (1<<2) /* trail edge ring (w1tc) */
128 #define CDNC_UART_MODEM_STAT_REG_DDSR (1<<1) /* change in DSR (w1tc) */
129 #define CDNC_UART_MODEM_STAT_REG_DCTS (1<<0) /* change in CTS (w1tc) */
131 #define CDNC_UART_CHAN_STAT_REG 0x2C /* Channel status register. */
132 #define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */
133 #define CDNC_UART_CHAN_STAT_REG_TXTRIG (1<<13)
134 #define CDNC_UART_CHAN_STAT_REG_FDELT (1<<12)
135 #define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11)
136 #define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10)
137 #define CDNC_UART_CHAN_STAT_REG_TXFULL (1<<4)
138 #define CDNC_UART_CHAN_STAT_REG_TXEMPTY (1<<3)
139 #define CDNC_UART_CHAN_STAT_REG_RXEMPTY (1<<1)
140 #define CDNC_UART_CHAN_STAT_REG_RXTRIG (1<<0)
142 #define CDNC_UART_FIFO 0x30 /* Data FIFO (tx and rx) */
143 #define CDNC_UART_BAUDDIV_REG 0x34
144 #define CDNC_UART_FLOWDEL_REG 0x38
145 #define CDNC_UART_TX_WATER_REG 0x44
149 * Low-level UART interface.
151 static int cdnc_uart_probe(struct uart_bas *bas);
152 static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int);
153 static void cdnc_uart_term(struct uart_bas *bas);
154 static void cdnc_uart_putc(struct uart_bas *bas, int);
155 static int cdnc_uart_rxready(struct uart_bas *bas);
156 static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx);
158 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
160 static struct uart_ops cdnc_uart_ops = {
161 .probe = cdnc_uart_probe,
162 .init = cdnc_uart_init,
163 .term = cdnc_uart_term,
164 .putc = cdnc_uart_putc,
165 .rxready = cdnc_uart_rxready,
166 .getc = cdnc_uart_getc,
169 #define SIGCHG(c, i, s, d) \
171 i |= (i & s) ? s : s | d; \
173 i = (i & s) ? (i & ~s) | d : i; \
177 cdnc_uart_probe(struct uart_bas *bas)
184 cdnc_uart_set_baud(struct uart_bas *bas, int baudrate)
186 uint32_t baudgen, bauddiv;
187 uint32_t best_bauddiv, best_baudgen, best_error;
188 uint32_t baud_out, err;
194 /* Try all possible bauddiv values and pick best match. */
195 for (bauddiv = 4; bauddiv <= 255; bauddiv++) {
196 baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) /
197 (baudrate * (bauddiv + 1));
198 if (baudgen < 1 || baudgen > 0xffff)
201 baud_out = bas->rclk / (baudgen * (bauddiv + 1));
202 err = baud_out > baudrate ?
203 baud_out - baudrate : baudrate - baud_out;
205 if (err < best_error) {
207 best_bauddiv = bauddiv;
208 best_baudgen = baudgen;
212 if (best_bauddiv > 0) {
213 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv);
214 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen);
217 return (-1); /* out of range */
221 cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits,
222 int stopbits, int parity)
224 uint32_t mode_reg_value = 0;
228 mode_reg_value |= CDNC_UART_MODE_REG_6BIT;
231 mode_reg_value |= CDNC_UART_MODE_REG_7BIT;
235 mode_reg_value |= CDNC_UART_MODE_REG_8BIT;
240 mode_reg_value |= CDNC_UART_MODE_REG_STOP2;
243 case UART_PARITY_MARK:
244 mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK;
246 case UART_PARITY_SPACE:
247 mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE;
249 case UART_PARITY_ODD:
250 mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD;
252 case UART_PARITY_EVEN:
253 mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN;
255 case UART_PARITY_NONE:
257 mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE;
261 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value);
263 if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0)
270 cdnc_uart_hw_init(struct uart_bas *bas)
273 /* Reset RX and TX. */
274 WR4(bas, CDNC_UART_CTRL_REG,
275 CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST);
277 /* Interrupts all off. */
278 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL);
279 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL);
281 /* Clear delta bits. */
282 WR4(bas, CDNC_UART_MODEM_STAT_REG,
283 CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI |
284 CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS);
286 /* RX FIFO water level, stale timeout */
287 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2);
288 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10);
290 /* TX FIFO water level (not used.) */
291 WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2);
293 /* Bring RX and TX online. */
294 WR4(bas, CDNC_UART_CTRL_REG,
295 CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN |
296 CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK);
298 /* Set DTR and RTS. */
299 WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR |
300 CDNC_UART_MODEM_CTRL_REG_RTS);
304 * Initialize this device for use as a console.
307 cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
311 /* Initialize hardware. */
312 cdnc_uart_hw_init(bas);
314 /* Set baudrate, parameters. */
315 (void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity);
319 * Free resources now that we're no longer the console. This appears to
320 * be never called, and I'm unsure quite what to do if I am called.
323 cdnc_uart_term(struct uart_bas *bas)
330 * Put a character of console output (so we do it here polling rather than
334 cdnc_uart_putc(struct uart_bas *bas, int c)
338 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
339 CDNC_UART_CHAN_STAT_REG_TXFULL) != 0)
342 WR4(bas, CDNC_UART_FIFO, c);
344 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
345 CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0)
350 * Check for a character available.
353 cdnc_uart_rxready(struct uart_bas *bas)
356 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
357 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0);
361 * Block waiting for a character.
364 cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx)
370 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
371 CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) {
377 c = RD4(bas, CDNC_UART_FIFO);
385 /*****************************************************************************/
387 * High-level UART interface.
390 static int cdnc_uart_bus_probe(struct uart_softc *sc);
391 static int cdnc_uart_bus_attach(struct uart_softc *sc);
392 static int cdnc_uart_bus_flush(struct uart_softc *, int);
393 static int cdnc_uart_bus_getsig(struct uart_softc *);
394 static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
395 static int cdnc_uart_bus_ipend(struct uart_softc *);
396 static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int);
397 static int cdnc_uart_bus_receive(struct uart_softc *);
398 static int cdnc_uart_bus_setsig(struct uart_softc *, int);
399 static int cdnc_uart_bus_transmit(struct uart_softc *);
400 static void cdnc_uart_bus_grab(struct uart_softc *);
401 static void cdnc_uart_bus_ungrab(struct uart_softc *);
403 static kobj_method_t cdnc_uart_bus_methods[] = {
404 KOBJMETHOD(uart_probe, cdnc_uart_bus_probe),
405 KOBJMETHOD(uart_attach, cdnc_uart_bus_attach),
406 KOBJMETHOD(uart_flush, cdnc_uart_bus_flush),
407 KOBJMETHOD(uart_getsig, cdnc_uart_bus_getsig),
408 KOBJMETHOD(uart_ioctl, cdnc_uart_bus_ioctl),
409 KOBJMETHOD(uart_ipend, cdnc_uart_bus_ipend),
410 KOBJMETHOD(uart_param, cdnc_uart_bus_param),
411 KOBJMETHOD(uart_receive, cdnc_uart_bus_receive),
412 KOBJMETHOD(uart_setsig, cdnc_uart_bus_setsig),
413 KOBJMETHOD(uart_transmit, cdnc_uart_bus_transmit),
414 KOBJMETHOD(uart_grab, cdnc_uart_bus_grab),
415 KOBJMETHOD(uart_ungrab, cdnc_uart_bus_ungrab),
421 cdnc_uart_bus_probe(struct uart_softc *sc)
424 sc->sc_txfifosz = UART_FIFO_SIZE;
425 sc->sc_rxfifosz = UART_FIFO_SIZE;
429 device_set_desc(sc->sc_dev, "Cadence UART");
435 cdnc_uart_bus_attach(struct uart_softc *sc)
437 struct uart_bas *bas = &sc->sc_bas;
438 struct uart_devinfo *di;
440 if (sc->sc_sysdev != NULL) {
442 (void)cdnc_uart_set_params(bas, di->baudrate, di->databits,
443 di->stopbits, di->parity);
445 cdnc_uart_hw_init(bas);
447 (void)cdnc_uart_bus_getsig(sc);
449 /* Enable interrupts. */
450 WR4(bas, CDNC_UART_IEN_REG,
451 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
452 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
459 cdnc_uart_bus_transmit(struct uart_softc *sc)
462 struct uart_bas *bas = &sc->sc_bas;
464 uart_lock(sc->sc_hwmtx);
466 /* Clear sticky TXEMPTY status bit. */
467 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY);
469 for (i = 0; i < sc->sc_txdatasz; i++)
470 WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]);
472 /* Enable TX empty interrupt. */
473 WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY);
476 uart_unlock(sc->sc_hwmtx);
482 cdnc_uart_bus_setsig(struct uart_softc *sc, int sig)
484 struct uart_bas *bas = &sc->sc_bas;
485 uint32_t new, old, modem_ctrl;
490 if (sig & SER_DDTR) {
491 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
493 if (sig & SER_DRTS) {
494 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
496 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
497 uart_lock(sc->sc_hwmtx);
498 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) &
499 ~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS);
500 if ((new & SER_DTR) != 0)
501 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR;
502 if ((new & SER_RTS) != 0)
503 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS;
504 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
506 uart_unlock(sc->sc_hwmtx);
511 cdnc_uart_bus_receive(struct uart_softc *sc)
513 struct uart_bas *bas = &sc->sc_bas;
517 uart_lock(sc->sc_hwmtx);
519 /* Check for parity or framing errors and clear the status bits. */
520 status = RD4(bas, CDNC_UART_ISTAT_REG);
521 if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) {
522 WR4(bas, CDNC_UART_ISTAT_REG,
523 status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY));
524 if ((status & CDNC_UART_INT_PARITY) != 0)
525 c_status |= UART_STAT_PARERR;
526 if ((status & CDNC_UART_INT_FRAMING) != 0)
527 c_status |= UART_STAT_FRAMERR;
530 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
531 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) {
532 c = RD4(bas, CDNC_UART_FIFO) & 0xff;
534 /* Detect break and drop into debugger. */
535 if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 &&
536 sc->sc_sysdev != NULL &&
537 sc->sc_sysdev->type == UART_DEV_CONSOLE) {
539 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING);
542 uart_rx_put(sc, c | c_status);
545 uart_unlock(sc->sc_hwmtx);
551 cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
552 int stopbits, int parity)
555 return (cdnc_uart_set_params(&sc->sc_bas, baudrate,
556 databits, stopbits, parity));
560 cdnc_uart_bus_ipend(struct uart_softc *sc)
563 struct uart_bas *bas = &sc->sc_bas;
566 uart_lock(sc->sc_hwmtx);
568 istatus = RD4(bas, CDNC_UART_ISTAT_REG);
570 /* Clear interrupt bits. */
571 WR4(bas, CDNC_UART_ISTAT_REG, istatus &
572 (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
573 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
574 CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI));
577 if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0)
578 ipend |= SER_INT_RXREADY;
580 /* Transmit fifo empty. */
581 if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) {
582 /* disable txempty interrupt. */
583 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY);
584 ipend |= SER_INT_TXIDLE;
588 if ((istatus & CDNC_UART_INT_TXOVR) != 0)
589 ipend |= SER_INT_OVERRUN;
592 if ((istatus & CDNC_UART_INT_RXOVR) != 0)
593 ipend |= SER_INT_OVERRUN;
595 /* Modem signal change. */
596 if ((istatus & CDNC_UART_INT_DMSI) != 0) {
597 WR4(bas, CDNC_UART_MODEM_STAT_REG,
598 CDNC_UART_MODEM_STAT_REG_DDCD |
599 CDNC_UART_MODEM_STAT_REG_TERI |
600 CDNC_UART_MODEM_STAT_REG_DDSR |
601 CDNC_UART_MODEM_STAT_REG_DCTS);
602 ipend |= SER_INT_SIGCHG;
605 uart_unlock(sc->sc_hwmtx);
610 cdnc_uart_bus_flush(struct uart_softc *sc, int what)
617 cdnc_uart_bus_getsig(struct uart_softc *sc)
619 struct uart_bas *bas = &sc->sc_bas;
620 uint32_t new, old, sig;
621 uint8_t modem_status;
626 uart_lock(sc->sc_hwmtx);
627 modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG);
628 uart_unlock(sc->sc_hwmtx);
629 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR,
630 sig, SER_DSR, SER_DDSR);
631 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS,
632 sig, SER_CTS, SER_DCTS);
633 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD,
634 sig, SER_DCD, SER_DDCD);
635 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI,
636 sig, SER_RI, SER_DRI);
637 new = sig & ~SER_MASK_DELTA;
638 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
643 cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
645 struct uart_bas *bas = &sc->sc_bas;
646 uint32_t uart_ctrl, modem_ctrl;
649 uart_lock(sc->sc_hwmtx);
652 case UART_IOCTL_BREAK:
653 uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG);
655 uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK;
656 uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK;
658 uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK;
659 uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK;
661 WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl);
663 case UART_IOCTL_IFLOW:
664 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG);
666 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS;
668 modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS;
669 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
676 uart_unlock(sc->sc_hwmtx);
682 cdnc_uart_bus_grab(struct uart_softc *sc)
685 /* Enable interrupts. */
686 WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
687 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
692 cdnc_uart_bus_ungrab(struct uart_softc *sc)
695 /* Enable interrupts. */
696 WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
697 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
698 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
702 static struct uart_class uart_cdnc_class = {
704 cdnc_uart_bus_methods,
705 sizeof(struct uart_softc),
706 .uc_ops = &cdnc_uart_ops,
710 static struct ofw_compat_data compat_data[] = {
711 {"cadence,uart", (uintptr_t)&uart_cdnc_class},
712 {"cdns,uart-r1p12", (uintptr_t)&uart_cdnc_class},
713 {"xlnx,xuartps", (uintptr_t)&uart_cdnc_class},
714 {NULL, (uintptr_t)NULL},
716 UART_FDT_CLASS_AND_DEVICE(compat_data);