2 * Copyright (c) 2013 Thomas Skibo
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
31 * In the future, maybe MIO control, clock control, etc. could go here.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/resource.h>
48 #include <sys/sysctl.h>
51 #include <machine/bus.h>
52 #include <machine/resource.h>
53 #include <machine/stdarg.h>
55 #include <dev/fdt/fdt_common.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <arm/xilinx/zy7_slcr.h>
61 struct zy7_slcr_softc {
64 struct resource *mem_res;
67 static struct zy7_slcr_softc *zy7_slcr_softc_p;
68 extern void (*zynq7_cpu_reset);
70 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
71 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
72 #define ZSLCR_LOCK_INIT(sc) \
73 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
75 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
77 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
78 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
81 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
83 static char zynq_bootmode[64];
84 SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
87 static char zynq_pssid[80];
88 SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
91 static uint32_t zynq_reboot_status;
92 SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
93 0, "Zynq REBOOT_STATUS register");
96 zy7_slcr_unlock(struct zy7_slcr_softc *sc)
99 /* Unlock SLCR with magic number. */
100 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
104 zy7_slcr_lock(struct zy7_slcr_softc *sc)
107 /* Lock SLCR with magic number. */
108 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
113 zy7_slcr_cpu_reset(void)
115 struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
117 /* Unlock SLCR registers. */
120 /* This has something to do with a work-around so the fsbl will load
121 * the bitstream after soft-reboot. It's very important.
123 WR4(sc, ZY7_SLCR_REBOOT_STAT,
124 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
127 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
133 /* Assert PL resets and disable level shifters in preparation of programming
134 * the PL (FPGA) section. Called from zy7_devcfg.c.
137 zy7_slcr_preload_pl(void)
139 struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
146 /* Unlock SLCR registers. */
149 /* Assert top level output resets. */
150 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
152 /* Disable all level shifters. */
153 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
155 /* Lock SLCR registers. */
161 /* After PL configuration, enable level shifters and deassert top-level
162 * PL resets. Called from zy7_devcfg.c. Optionally, the level shifters
163 * can be left disabled but that's rare of an FPGA application. That option
164 * is controled by a sysctl in the devcfg driver.
167 zy7_slcr_postload_pl(int en_level_shifters)
169 struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
176 /* Unlock SLCR registers. */
179 if (en_level_shifters)
180 /* Enable level shifters. */
181 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
183 /* Deassert top level output resets. */
184 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
186 /* Lock SLCR registers. */
193 zy7_slcr_probe(device_t dev)
195 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
198 device_set_desc(dev, "Zynq-7000 slcr block");
203 zy7_slcr_attach(device_t dev)
205 struct zy7_slcr_softc *sc = device_get_softc(dev);
209 static char *bootdev_names[] = {
210 "JTAG", "Quad-SPI", "NOR", "(3?)",
211 "NAND", "SD Card", "(6?)", "(7?)"
214 /* Allow only one attach. */
215 if (zy7_slcr_softc_p != NULL)
222 /* Get memory resource. */
224 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
226 if (sc->mem_res == NULL) {
227 device_printf(dev, "could not allocate memory resources.\n");
231 /* Hook up cpu_reset. */
232 zy7_slcr_softc_p = sc;
233 zynq7_cpu_reset = zy7_slcr_cpu_reset;
235 /* Read info and set sysctls. */
236 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
237 snprintf(zynq_bootmode, sizeof(zynq_bootmode),
238 "0x%x: boot device: %s", bootmode,
239 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
241 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
242 snprintf(zynq_pssid, sizeof(zynq_pssid),
243 "0x%x: manufacturer: 0x%x device: 0x%x "
244 "family: 0x%x sub-family: 0x%x rev: 0x%x",
246 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
247 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
248 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
249 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
250 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
251 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
252 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
253 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
254 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
255 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
257 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
259 /* Lock SLCR registers. */
266 zy7_slcr_detach(device_t dev)
268 struct zy7_slcr_softc *sc = device_get_softc(dev);
270 bus_generic_detach(dev);
272 /* Release memory resource. */
273 if (sc->mem_res != NULL)
274 bus_release_resource(dev, SYS_RES_MEMORY,
275 rman_get_rid(sc->mem_res), sc->mem_res);
277 zy7_slcr_softc_p = NULL;
278 zynq7_cpu_reset = NULL;
280 ZSLCR_LOCK_DESTROY(sc);
285 static device_method_t zy7_slcr_methods[] = {
287 DEVMETHOD(device_probe, zy7_slcr_probe),
288 DEVMETHOD(device_attach, zy7_slcr_attach),
289 DEVMETHOD(device_detach, zy7_slcr_detach),
294 static driver_t zy7_slcr_driver = {
297 sizeof(struct zy7_slcr_softc),
299 static devclass_t zy7_slcr_devclass;
301 DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
302 MODULE_VERSION(zy7_slcr, 1);