1 /* $NetBSD: iq80321reg.h,v 1.4 2003/05/14 19:46:39 thorpej Exp $ */
4 * Copyright (c) 2002 Wasabi Systems, Inc.
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
41 #ifndef _IQ80321REG_H_
42 #define _IQ80321REG_H_
45 * Memory map and register definitions for the Intel IQ80321
50 * The memory map of the IQ80321 looks like so:
52 * ------------------------------
53 * Intel 80321 IOP Reserved
54 * FFFF E900 ------------------------------
55 * Peripheral Memory Mapped
57 * FFFF E000 ------------------------------
59 * FE80 0000 ------------------------------
61 * A000 0000 ------------------------------
63 * 9100 0000 ------------------------------
65 * 9080 0000 ------------------------------
67 * 9002 0000 ------------------------------
68 * ATU Outbound Transaction
70 * 8000 0000 ------------------------------
73 * 0000 1000 ------------------------------
74 * Initialization Boot Code
76 * 0000 0000 ------------------------------
80 * We allocate a page table for VA 0xfe400000 (4MB) and map the
81 * PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
83 #define IQ80321_IOPXS_VBASE 0xfe400000UL
84 #define IQ80321_IOW_VBASE IQ80321_IOPXS_VBASE
85 #define IQ80321_80321_VBASE (IQ80321_IOW_VBASE + \
86 VERDE_OUT_XLATE_IO_WIN_SIZE)
88 #define IQ80321_SDRAM_START 0xa0000000
90 * The IQ80321 on-board devices are mapped VA==PA during bootstrap.
91 * Conveniently, the size of the on-board register space is 1 section
94 #define IQ80321_OBIO_BASE 0xfe800000UL
95 #define IQ80321_OBIO_SIZE 0x00100000UL /* 1MB */
97 #define IQ80321_UART1 0xfe800000UL /* TI 16550 */
99 #if defined( CPU_XSCALE_80321 )
100 #define IQ80321_7SEG_MSB 0xfe840000UL
101 #define IQ80321_7SEG_LSB 0xfe850000UL
103 #define IQ80321_ROT_SWITCH 0xfe8d0000UL
105 #define IQ80321_BATTERY_STAT 0xfe8f0000UL
106 #define BATTERY_STAT_PRES (1U << 0)
107 #define BATTERY_STAT_CHRG (1U << 1)
108 #define BATTERY_STAT_DISCHRG (1U << 2)
109 #endif /* CPU_XSCALE_80321 */
111 #endif /* _IQ80321REG_H_ */