2 * Copyright (c) 2006 Sam Leffler. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
29 * Intel XScale NPE Ethernet driver.
31 * This driver handles the two ports present on the IXP425.
32 * Packet processing is done by the Network Processing Engines
33 * (NPE's) that work together with a MAC and PHY. The MAC
34 * is also mapped to the XScale cpu; the PHY is accessed via
35 * the MAC. NPE-XScale communication happens through h/w
36 * queues managed by the Q Manager block.
38 * The code here replaces the ethAcc, ethMii, and ethDB classes
39 * in the Intel Access Library (IAL) and the OS-specific driver.
41 * XXX add vlan support
42 * XXX NPE-C port doesn't work yet
44 #ifdef HAVE_KERNEL_OPTION_HEADERS
45 #include "opt_device_polling.h"
48 #include <sys/param.h>
49 #include <sys/systm.h>
51 #include <sys/kernel.h>
53 #include <sys/malloc.h>
54 #include <sys/module.h>
56 #include <sys/socket.h>
57 #include <sys/sockio.h>
58 #include <sys/sysctl.h>
59 #include <sys/endian.h>
60 #include <machine/bus.h>
62 #include <net/ethernet.h>
64 #include <net/if_arp.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_mib.h>
68 #include <net/if_types.h>
71 #include <netinet/in.h>
72 #include <netinet/in_systm.h>
73 #include <netinet/in_var.h>
74 #include <netinet/ip.h>
78 #include <net/bpfdesc.h>
80 #include <arm/xscale/ixp425/ixp425reg.h>
81 #include <arm/xscale/ixp425/ixp425var.h>
82 #include <arm/xscale/ixp425/ixp425_qmgr.h>
83 #include <arm/xscale/ixp425/ixp425_npevar.h>
85 #include <dev/mii/mii.h>
86 #include <dev/mii/miivar.h>
87 #include <arm/xscale/ixp425/if_npereg.h>
89 #include "miibus_if.h"
92 * XXX: For the main bus dma tag. Can go away if the new method to get the
93 * dma tag from the parent got MFC'd into RELENG_6.
95 extern struct ixp425_softc *ixp425_softc;
98 struct npebuf *ix_next; /* chain to next buffer */
99 void *ix_m; /* backpointer to mbuf */
100 bus_dmamap_t ix_map; /* bus dma map for associated data */
101 struct npehwbuf *ix_hw; /* associated h/w block */
102 uint32_t ix_neaddr; /* phys address of ix_hw */
107 int nbuf; /* # npebuf's allocated */
108 bus_dma_tag_t mtag; /* bus dma tag for mbuf data */
109 struct npehwbuf *hwbuf; /* NPE h/w buffers */
110 bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */
111 bus_dmamap_t buf_map;
112 bus_addr_t buf_phys; /* phys addr of buffers */
113 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */
117 /* XXX mii requires this be first; do not move! */
118 struct ifnet *sc_ifp; /* ifnet pointer */
119 struct mtx sc_mtx; /* basically a perimeter lock */
121 bus_space_tag_t sc_iot;
122 bus_space_handle_t sc_ioh; /* MAC register window */
123 device_t sc_mii; /* child miibus */
124 bus_space_handle_t sc_miih; /* MII register window */
125 struct ixpnpe_softc *sc_npe; /* NPE support */
126 int sc_debug; /* DPRINTF* control */
128 struct callout tick_ch; /* Tick callout */
129 int npe_watchdog_timer;
131 struct npebuf *tx_free; /* list of free tx buffers */
133 bus_addr_t buf_phys; /* XXX for returning a value */
134 int rx_qid; /* rx qid */
135 int rx_freeqid; /* rx free buffers qid */
136 int tx_qid; /* tx qid */
137 int tx_doneqid; /* tx completed qid */
138 struct ifmib_iso_8802_3 mibdata;
139 bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */
140 struct npestats *sc_stats;
141 bus_dmamap_t sc_stats_map;
142 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */
146 * Per-unit static configuration for IXP425. The tx and
147 * rx free Q id's are fixed by the NPE microcode. The
148 * rx Q id's are programmed to be separate to simplify
149 * multi-port processing. It may be better to handle
150 * all traffic through one Q (as done by the Intel drivers).
152 * Note that the PHY's are accessible only from MAC A
153 * on the IXP425. This and other platform-specific
154 * assumptions probably need to be handled through hints.
156 static const struct {
157 const char *desc; /* device description */
158 int npeid; /* NPE assignment */
159 uint32_t imageid; /* NPE firmware image id */
168 } npeconfig[NPE_PORTS_MAX] = {
169 { .desc = "IXP NPE-B",
171 .imageid = IXP425_NPE_B_IMAGEID,
172 .regbase = IXP425_MAC_A_HWBASE,
173 .regsize = IXP425_MAC_A_SIZE,
174 .miibase = IXP425_MAC_A_HWBASE,
175 .miisize = IXP425_MAC_A_SIZE,
181 { .desc = "IXP NPE-C",
183 .imageid = IXP425_NPE_C_IMAGEID,
184 .regbase = IXP425_MAC_B_HWBASE,
185 .regsize = IXP425_MAC_B_SIZE,
186 .miibase = IXP425_MAC_A_HWBASE,
187 .miisize = IXP425_MAC_A_SIZE,
194 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */
196 static __inline uint32_t
197 RD4(struct npe_softc *sc, bus_size_t off)
199 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
203 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
205 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
208 #define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
209 #define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
210 #define NPE_LOCK_INIT(_sc) \
211 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
212 MTX_NETWORK_LOCK, MTX_DEF)
213 #define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
214 #define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
215 #define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
217 static devclass_t npe_devclass;
219 static int npe_activate(device_t dev);
220 static void npe_deactivate(device_t dev);
221 static int npe_ifmedia_update(struct ifnet *ifp);
222 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr);
223 static void npe_setmac(struct npe_softc *sc, u_char *eaddr);
224 static void npe_getmac(struct npe_softc *sc, u_char *eaddr);
225 static void npe_txdone(int qid, void *arg);
226 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *,
228 static void npe_rxdone(int qid, void *arg);
229 static void npeinit(void *);
230 static void npestart_locked(struct ifnet *);
231 static void npestart(struct ifnet *);
232 static void npestop(struct npe_softc *);
233 static void npewatchdog(struct npe_softc *);
234 static int npeioctl(struct ifnet * ifp, u_long, caddr_t);
236 static int npe_setrxqosentry(struct npe_softc *, int classix,
237 int trafclass, int qid);
238 static int npe_updatestats(struct npe_softc *);
240 static int npe_getstats(struct npe_softc *);
241 static uint32_t npe_getimageid(struct npe_softc *);
242 static int npe_setloopback(struct npe_softc *, int ena);
245 /* NB: all tx done processing goes through one queue */
246 static int tx_doneqid = -1;
248 SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP425 NPE driver parameters");
250 static int npe_debug = 0;
251 SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug,
252 0, "IXP425 NPE network interface debug msgs");
253 TUNABLE_INT("hw.npe.npe", &npe_debug);
254 #define DPRINTF(sc, fmt, ...) do { \
255 if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \
257 #define DPRINTFn(n, sc, fmt, ...) do { \
258 if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\
260 static int npe_tickinterval = 3; /* npe_tick frequency (secs) */
261 SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval,
262 0, "periodic work interval (secs)");
263 TUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval);
265 static int npe_rxbuf = 64; /* # rx buffers to allocate */
266 SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf,
267 0, "rx buffers allocated");
268 TUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf);
269 static int npe_txbuf = 128; /* # tx buffers to allocate */
270 SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf,
271 0, "tx buffers allocated");
272 TUNABLE_INT("hw.npe.txbuf", &npe_txbuf);
275 npe_probe(device_t dev)
277 int unit = device_get_unit(dev);
279 if (unit >= NPE_PORTS_MAX) {
280 device_printf(dev, "unit %d not supported\n", unit);
283 /* XXX check feature register to see if enabled */
284 device_set_desc(dev, npeconfig[unit].desc);
289 npe_attach(device_t dev)
291 struct npe_softc *sc = device_get_softc(dev);
292 struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
293 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
294 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
295 struct ifnet *ifp = NULL;
300 sc->sc_iot = sa->sc_iot;
302 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
303 sc->sc_debug = npe_debug;
304 sc->sc_tickinterval = npe_tickinterval;
306 sc->sc_npe = ixpnpe_attach(dev);
307 if (sc->sc_npe == NULL) {
308 error = EIO; /* XXX */
312 error = npe_activate(dev);
316 npe_getmac(sc, eaddr);
318 /* NB: must be setup prior to invoking mii code */
319 sc->sc_ifp = ifp = if_alloc(IFT_ETHER);
320 if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) {
321 device_printf(dev, "Cannot find my PHY.\n");
327 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
329 ifp->if_start = npestart;
330 ifp->if_ioctl = npeioctl;
331 ifp->if_init = npeinit;
332 IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1);
333 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
334 IFQ_SET_READY(&ifp->if_snd);
335 ifp->if_linkmib = &sc->mibdata;
336 ifp->if_linkmiblen = sizeof(sc->mibdata);
337 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS;
338 #ifdef DEVICE_POLLING
339 ifp->if_capabilities |= IFCAP_POLLING;
342 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug",
343 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
344 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval",
345 CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency");
347 ether_ifattach(ifp, eaddr);
357 npe_detach(device_t dev)
359 struct npe_softc *sc = device_get_softc(dev);
360 struct ifnet *ifp = sc->sc_ifp;
362 #ifdef DEVICE_POLLING
363 if (ifp->if_capenable & IFCAP_POLLING)
364 ether_poll_deregister(ifp);
371 NPE_LOCK_DESTROY(sc);
373 if (sc->sc_npe != NULL)
374 ixpnpe_detach(sc->sc_npe);
379 * Compute and install the multicast filter.
382 npe_setmcast(struct npe_softc *sc)
384 struct ifnet *ifp = sc->sc_ifp;
385 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN];
388 if (ifp->if_flags & IFF_PROMISC) {
389 memset(mask, 0, ETHER_ADDR_LEN);
390 memset(addr, 0, ETHER_ADDR_LEN);
391 } else if (ifp->if_flags & IFF_ALLMULTI) {
392 static const uint8_t allmulti[ETHER_ADDR_LEN] =
393 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
394 memcpy(mask, allmulti, ETHER_ADDR_LEN);
395 memcpy(addr, allmulti, ETHER_ADDR_LEN);
397 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
398 struct ifmultiaddr *ifma;
401 memset(clr, 0, ETHER_ADDR_LEN);
402 memset(set, 0xff, ETHER_ADDR_LEN);
405 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
406 if (ifma->ifma_addr->sa_family != AF_LINK)
408 mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
409 for (i = 0; i < ETHER_ADDR_LEN; i++) {
416 for (i = 0; i < ETHER_ADDR_LEN; i++) {
417 mask[i] = set[i] | ~clr[i];
423 * Write the mask and address registers.
425 for (i = 0; i < ETHER_ADDR_LEN; i++) {
426 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
427 WR4(sc, NPE_MAC_ADDR(i), addr[i]);
432 npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
434 struct npe_softc *sc;
438 sc = (struct npe_softc *)arg;
439 sc->buf_phys = segs[0].ds_addr;
443 npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
444 const char *name, int nbuf, int maxseg)
448 memset(dma, 0, sizeof(dma));
453 /* DMA tag for mapped mbufs */
454 error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0,
455 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
456 MCLBYTES, maxseg, MCLBYTES, 0,
457 busdma_lock_mutex, &sc->sc_mtx, &dma->mtag);
459 device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, "
460 "error %u\n", dma->name, error);
464 /* DMA tag and map for the NPE buffers */
465 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
466 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
467 nbuf * sizeof(struct npehwbuf), 1,
468 nbuf * sizeof(struct npehwbuf), 0,
469 busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag);
471 device_printf(sc->sc_dev,
472 "unable to create %s npebuf dma tag, error %u\n",
476 /* XXX COHERENT for now */
477 if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf,
478 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
479 &dma->buf_map) != 0) {
480 device_printf(sc->sc_dev,
481 "unable to allocate memory for %s h/w buffers, error %u\n",
486 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO);
487 if (dma->buf == NULL) {
488 device_printf(sc->sc_dev,
489 "unable to allocate memory for %s s/w buffers\n",
493 if (bus_dmamap_load(dma->buf_tag, dma->buf_map,
494 dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) {
495 device_printf(sc->sc_dev,
496 "unable to map memory for %s h/w buffers, error %u\n",
500 dma->buf_phys = sc->buf_phys;
501 for (i = 0; i < dma->nbuf; i++) {
502 struct npebuf *npe = &dma->buf[i];
503 struct npehwbuf *hw = &dma->hwbuf[i];
505 /* calculate offset to shared area */
506 npe->ix_neaddr = dma->buf_phys +
507 ((uintptr_t)hw - (uintptr_t)dma->hwbuf);
508 KASSERT((npe->ix_neaddr & 0x1f) == 0,
509 ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr));
510 error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT,
513 device_printf(sc->sc_dev,
514 "unable to create dmamap for %s buffer %u, "
515 "error %u\n", dma->name, i, error);
520 bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE);
525 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma)
529 if (dma->hwbuf != NULL) {
530 for (i = 0; i < dma->nbuf; i++) {
531 struct npebuf *npe = &dma->buf[i];
532 bus_dmamap_destroy(dma->mtag, npe->ix_map);
534 bus_dmamap_unload(dma->buf_tag, dma->buf_map);
535 bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map);
536 bus_dmamap_destroy(dma->buf_tag, dma->buf_map);
538 if (dma->buf != NULL)
539 free(dma->buf, M_TEMP);
541 bus_dma_tag_destroy(dma->buf_tag);
543 bus_dma_tag_destroy(dma->mtag);
544 memset(dma, 0, sizeof(*dma));
548 npe_activate(device_t dev)
550 struct npe_softc * sc = device_get_softc(dev);
551 int unit = device_get_unit(dev);
554 /* load NPE firmware and start it running */
555 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid);
559 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase,
560 npeconfig[unit].regsize, 0, &sc->sc_ioh)) {
561 device_printf(dev, "Cannot map registers 0x%x:0x%x\n",
562 npeconfig[unit].regbase, npeconfig[unit].regsize);
566 if (npeconfig[unit].miibase != npeconfig[unit].regbase) {
568 * The PHY's are only accessible from one MAC (it appears)
569 * so for other MAC's setup an additional mapping for
570 * frobbing the PHY registers.
572 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase,
573 npeconfig[unit].miisize, 0, &sc->sc_miih)) {
575 "Cannot map MII registers 0x%x:0x%x\n",
576 npeconfig[unit].miibase, npeconfig[unit].miisize);
580 sc->sc_miih = sc->sc_ioh;
581 error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG);
584 error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1);
588 /* setup statistics block */
589 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
590 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
591 sizeof(struct npestats), 1, sizeof(struct npestats), 0,
592 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag);
594 device_printf(sc->sc_dev, "unable to create stats tag, "
595 "error %u\n", error);
598 if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats,
599 BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) {
600 device_printf(sc->sc_dev,
601 "unable to allocate memory for stats block, error %u\n",
605 if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map,
606 sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) {
607 device_printf(sc->sc_dev,
608 "unable to load memory for stats block, error %u\n",
612 sc->sc_stats_phys = sc->buf_phys;
614 /* XXX disable half-bridge LEARNING+FILTERING feature */
617 * Setup h/w rx/tx queues. There are four q's:
618 * rx inbound q of rx'd frames
619 * rx_free pool of ixpbuf's for receiving frames
620 * tx outbound q of frames to send
621 * tx_done q of tx frames that have been processed
623 * The NPE handles the actual tx/rx process and the q manager
624 * handles the queues. The driver just writes entries to the
625 * q manager mailbox's and gets callbacks when there are rx'd
626 * frames to process or tx'd frames to reap. These callbacks
627 * are controlled by the q configurations; e.g. we get a
628 * callback when tx_done has 2 or more frames to process and
629 * when the rx q has at least one frame. These setings can
630 * changed at the time the q is configured.
632 sc->rx_qid = npeconfig[unit].rx_qid;
633 ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1,
634 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc);
635 sc->rx_freeqid = npeconfig[unit].rx_freeqid;
636 ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc);
637 /* tell the NPE to direct all traffic to rx_qid */
639 for (i = 0; i < 8; i++)
641 device_printf(sc->sc_dev, "remember to fix rx q setup\n");
642 for (i = 0; i < 4; i++)
644 npe_setrxqosentry(sc, i, 0, sc->rx_qid);
646 sc->tx_qid = npeconfig[unit].tx_qid;
647 sc->tx_doneqid = npeconfig[unit].tx_doneqid;
648 ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc);
649 if (tx_doneqid == -1) {
650 ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2,
651 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc);
652 tx_doneqid = sc->tx_doneqid;
655 KASSERT(npes[npeconfig[unit].npeid] == NULL,
656 ("npe %u already setup", npeconfig[unit].npeid));
657 npes[npeconfig[unit].npeid] = sc;
663 npe_deactivate(device_t dev)
665 struct npe_softc *sc = device_get_softc(dev);
666 int unit = device_get_unit(dev);
668 npes[npeconfig[unit].npeid] = NULL;
670 /* XXX disable q's */
671 if (sc->sc_npe != NULL)
672 ixpnpe_stop(sc->sc_npe);
673 if (sc->sc_stats != NULL) {
674 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map);
675 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats,
677 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map);
679 if (sc->sc_stats_tag != NULL)
680 bus_dma_tag_destroy(sc->sc_stats_tag);
681 npe_dma_destroy(sc, &sc->txdma);
682 npe_dma_destroy(sc, &sc->rxdma);
683 bus_generic_detach(sc->sc_dev);
685 device_delete_child(sc->sc_dev, sc->sc_mii);
687 /* XXX sc_ioh and sc_miih */
689 bus_release_resource(dev, SYS_RES_IOPORT,
690 rman_get_rid(sc->mem_res), sc->mem_res);
696 * Change media according to request.
699 npe_ifmedia_update(struct ifnet *ifp)
701 struct npe_softc *sc = ifp->if_softc;
702 struct mii_data *mii;
704 mii = device_get_softc(sc->sc_mii);
707 /* XXX push state ourself? */
713 * Notify the world which media we're using.
716 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
718 struct npe_softc *sc = ifp->if_softc;
719 struct mii_data *mii;
721 mii = device_get_softc(sc->sc_mii);
724 ifmr->ifm_active = mii->mii_media_active;
725 ifmr->ifm_status = mii->mii_media_status;
730 npe_addstats(struct npe_softc *sc)
732 #define MIBADD(x) sc->mibdata.x += be32toh(ns->x)
733 struct ifnet *ifp = sc->sc_ifp;
734 struct npestats *ns = sc->sc_stats;
736 MIBADD(dot3StatsAlignmentErrors);
737 MIBADD(dot3StatsFCSErrors);
738 MIBADD(dot3StatsSingleCollisionFrames);
739 MIBADD(dot3StatsMultipleCollisionFrames);
740 MIBADD(dot3StatsDeferredTransmissions);
741 MIBADD(dot3StatsLateCollisions);
742 MIBADD(dot3StatsExcessiveCollisions);
743 MIBADD(dot3StatsInternalMacTransmitErrors);
744 MIBADD(dot3StatsCarrierSenseErrors);
745 sc->mibdata.dot3StatsFrameTooLongs +=
746 be32toh(ns->RxLargeFramesDiscards)
747 + be32toh(ns->TxLargeFrameDiscards);
748 MIBADD(dot3StatsInternalMacReceiveErrors);
749 sc->mibdata.dot3StatsMissedFrames +=
750 be32toh(ns->RxOverrunDiscards)
751 + be32toh(ns->RxUnderflowEntryDiscards);
754 be32toh(ns->dot3StatsInternalMacTransmitErrors)
755 + be32toh(ns->dot3StatsCarrierSenseErrors)
756 + be32toh(ns->TxVLANIdFilterDiscards)
758 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors)
759 + be32toh(ns->dot3StatsInternalMacReceiveErrors)
760 + be32toh(ns->RxOverrunDiscards)
761 + be32toh(ns->RxUnderflowEntryDiscards)
763 ifp->if_collisions +=
764 be32toh(ns->dot3StatsSingleCollisionFrames)
765 + be32toh(ns->dot3StatsMultipleCollisionFrames)
773 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL)
774 struct npe_softc *sc = xsc;
775 struct mii_data *mii = device_get_softc(sc->sc_mii);
778 NPE_ASSERT_LOCKED(sc);
781 * NB: to avoid sleeping with the softc lock held we
782 * split the NPE msg processing into two parts. The
783 * request for statistics is sent w/o waiting for a
784 * reply and then on the next tick we retrieve the
785 * results. This works because npe_tick is the only
786 * code that talks via the mailbox's (except at setup).
787 * This likely can be handled better.
789 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) {
790 bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map,
791 BUS_DMASYNC_POSTREAD);
799 /* schedule next poll */
800 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc);
805 npe_setmac(struct npe_softc *sc, u_char *eaddr)
807 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
808 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
809 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
810 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
811 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
812 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
817 npe_getmac(struct npe_softc *sc, u_char *eaddr)
819 /* NB: the unicast address appears to be loaded from EEPROM on reset */
820 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;
821 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;
822 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;
823 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;
824 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;
825 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;
830 struct npebuf **tail;
835 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td)
837 struct ifnet *ifp = sc->sc_ifp;
840 *td->tail = sc->tx_free;
841 sc->tx_free = td->head;
843 * We're no longer busy, so clear the busy flag and call the
844 * start routine to xmit more packets.
846 ifp->if_opackets += td->count;
847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
848 sc->npe_watchdog_timer = 0;
849 npestart_locked(ifp);
854 * Q manager callback on tx done queue. Reap mbufs
855 * and return tx buffers to the free list. Finally
856 * restart output. Note the microcode has only one
857 * txdone q wired into it so we must use the NPE ID
858 * returned with each npehwbuf to decide where to
862 npe_txdone(int qid, void *arg)
864 #define P2V(a, dma) \
865 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
866 struct npe_softc *sc0 = arg;
867 struct npe_softc *sc;
869 struct txdone *td, q[NPE_MAX];
872 /* XXX no NPE-A support */
873 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0;
874 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0;
875 /* XXX max # at a time? */
876 while (ixpqmgr_qread(qid, &entry) == 0) {
877 DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n",
878 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry));
880 sc = npes[NPE_QM_Q_NPE(entry)];
881 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma);
885 td = &q[NPE_QM_Q_NPE(entry)];
887 td->tail = &npe->ix_next;
892 npe_txdone_finish(npes[NPE_B], &q[NPE_B]);
894 npe_txdone_finish(npes[NPE_C], &q[NPE_C]);
899 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m)
901 bus_dma_segment_t segs[1];
902 struct npedma *dma = &sc->rxdma;
907 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
911 KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN,
912 ("ext_size %d", m->m_ext.ext_size));
913 m->m_pkthdr.len = m->m_len = 1536;
914 /* backload payload and align ip hdr */
915 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN));
916 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m,
923 hw->ix_ne[0].data = htobe32(segs[0].ds_addr);
924 /* NB: NPE requires length be a multiple of 64 */
925 /* NB: buffer length is shifted in word */
926 hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16);
927 hw->ix_ne[0].next = 0;
929 /* Flush the memory in the mbuf */
930 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD);
935 * RX q processing for a specific NPE. Claim entries
936 * from the hardware queue and pass the frames up the
937 * stack. Pass the rx buffers to the free list.
940 npe_rxdone(int qid, void *arg)
942 #define P2V(a, dma) \
943 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
944 struct npe_softc *sc = arg;
945 struct npedma *dma = &sc->rxdma;
948 while (ixpqmgr_qread(qid, &entry) == 0) {
949 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma);
952 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n",
953 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len);
955 * Allocate a new mbuf to replenish the rx buffer.
956 * If doing so fails we drop the rx'd frame so we
957 * can reuse the previous mbuf. When we're able to
958 * allocate a new mbuf dispatch the mbuf w/ rx'd
959 * data up the stack and replace it with the newly
962 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
964 struct mbuf *mrx = npe->ix_m;
965 struct npehwbuf *hw = npe->ix_hw;
966 struct ifnet *ifp = sc->sc_ifp;
968 /* Flush mbuf memory for rx'd data */
969 bus_dmamap_sync(dma->mtag, npe->ix_map,
970 BUS_DMASYNC_POSTREAD);
972 /* XXX flush hw buffer; works now 'cuz coherent */
973 /* set m_len etc. per rx frame size */
974 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff;
975 mrx->m_pkthdr.len = mrx->m_len;
976 mrx->m_pkthdr.rcvif = ifp;
977 mrx->m_flags |= M_HASFCS;
980 ifp->if_input(ifp, mrx);
982 /* discard frame and re-use mbuf */
985 if (npe_rxbuf_init(sc, npe, m) == 0) {
986 /* return npe buf to rx free list */
987 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
989 /* XXX should not happen */
995 #ifdef DEVICE_POLLING
997 npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
999 struct npe_softc *sc = ifp->if_softc;
1001 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1002 npe_rxdone(sc->rx_qid, sc);
1003 npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */
1006 #endif /* DEVICE_POLLING */
1009 npe_startxmit(struct npe_softc *sc)
1011 struct npedma *dma = &sc->txdma;
1014 NPE_ASSERT_LOCKED(sc);
1016 for (i = 0; i < dma->nbuf; i++) {
1017 struct npebuf *npe = &dma->buf[i];
1018 if (npe->ix_m != NULL) {
1019 /* NB: should not happen */
1020 device_printf(sc->sc_dev,
1021 "%s: free mbuf at entry %u\n", __func__, i);
1025 npe->ix_next = sc->tx_free;
1031 npe_startrecv(struct npe_softc *sc)
1033 struct npedma *dma = &sc->rxdma;
1037 NPE_ASSERT_LOCKED(sc);
1038 for (i = 0; i < dma->nbuf; i++) {
1040 npe_rxbuf_init(sc, npe, npe->ix_m);
1041 /* set npe buf on rx free list */
1042 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1047 * Reset and initialize the chip
1050 npeinit_locked(void *xsc)
1052 struct npe_softc *sc = xsc;
1053 struct ifnet *ifp = sc->sc_ifp;
1055 NPE_ASSERT_LOCKED(sc);
1056 if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/
1061 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1062 DELAY(NPE_MAC_RESET_DELAY);
1063 /* configure MAC to generate MDC clock */
1064 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1066 /* disable transmitter and reciver in the MAC */
1067 WR4(sc, NPE_MAC_RX_CNTRL1,
1068 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1069 WR4(sc, NPE_MAC_TX_CNTRL1,
1070 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1073 * Set the MAC core registers.
1075 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
1076 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
1077 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
1078 /* thresholds determined by NPE firmware FS */
1079 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
1080 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
1081 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */
1082 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
1083 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
1084 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
1085 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
1086 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */
1088 WR4(sc, NPE_MAC_TX_CNTRL1,
1089 NPE_TX_CNTRL1_RETRY /* retry failed xmits */
1090 | NPE_TX_CNTRL1_FCS_EN /* append FCS */
1091 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */
1092 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */
1093 /* XXX pad strip? */
1094 WR4(sc, NPE_MAC_RX_CNTRL1,
1095 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */
1096 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */
1097 WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1099 npe_setmac(sc, IF_LLADDR(ifp));
1105 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1106 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1107 sc->npe_watchdog_timer = 0; /* just in case */
1109 /* enable transmitter and reciver in the MAC */
1110 WR4(sc, NPE_MAC_RX_CNTRL1,
1111 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);
1112 WR4(sc, NPE_MAC_TX_CNTRL1,
1113 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);
1115 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc);
1121 struct npe_softc *sc = xsc;
1128 * Defragment an mbuf chain, returning at most maxfrags separate
1129 * mbufs+clusters. If this is not possible NULL is returned and
1130 * the original mbuf chain is left in it's present (potentially
1131 * modified) state. We use two techniques: collapsing consecutive
1132 * mbufs and replacing consecutive mbufs by a cluster.
1134 static struct mbuf *
1135 npe_defrag(struct mbuf *m0, int how, int maxfrags)
1137 struct mbuf *m, *n, *n2, **prev;
1141 * Calculate the current number of frags.
1144 for (m = m0; m != NULL; m = m->m_next)
1147 * First, try to collapse mbufs. Note that we always collapse
1148 * towards the front so we don't need to deal with moving the
1149 * pkthdr. This may be suboptimal if the first mbuf has much
1150 * less data than the following.
1158 if ((m->m_flags & M_RDONLY) == 0 &&
1159 n->m_len < M_TRAILINGSPACE(m)) {
1160 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
1162 m->m_len += n->m_len;
1163 m->m_next = n->m_next;
1165 if (--curfrags <= maxfrags)
1170 KASSERT(maxfrags > 1,
1171 ("maxfrags %u, but normal collapse failed", maxfrags));
1173 * Collapse consecutive mbufs to a cluster.
1175 prev = &m0->m_next; /* NB: not the first mbuf */
1176 while ((n = *prev) != NULL) {
1177 if ((n2 = n->m_next) != NULL &&
1178 n->m_len + n2->m_len < MCLBYTES) {
1179 m = m_getcl(how, MT_DATA, 0);
1182 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
1183 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
1185 m->m_len = n->m_len + n2->m_len;
1186 m->m_next = n2->m_next;
1190 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
1193 * Still not there, try the normal collapse
1194 * again before we allocate another cluster.
1201 * No place where we can collapse to a cluster; punt.
1202 * This can occur if, for example, you request 2 frags
1203 * but the packet requires that both be clusters (we
1204 * never reallocate the first mbuf to avoid moving the
1212 * Dequeue packets and place on the h/w transmit queue.
1215 npestart_locked(struct ifnet *ifp)
1217 struct npe_softc *sc = ifp->if_softc;
1219 struct npehwbuf *hw;
1221 struct npedma *dma = &sc->txdma;
1222 bus_dma_segment_t segs[NPE_MAXSEG];
1223 int nseg, len, error, i;
1226 NPE_ASSERT_LOCKED(sc);
1227 /* XXX can this happen? */
1228 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1231 while (sc->tx_free != NULL) {
1232 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1235 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1239 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map,
1241 if (error == EFBIG) {
1242 n = npe_defrag(m, M_DONTWAIT, NPE_MAXSEG);
1244 if_printf(ifp, "%s: too many fragments %u\n",
1250 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map,
1253 if (error != 0 || nseg == 0) {
1254 if_printf(ifp, "%s: error %u nseg %u\n",
1255 __func__, error, nseg);
1259 sc->tx_free = npe->ix_next;
1261 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE);
1264 * Tap off here if there is a bpf listener.
1270 len = m->m_pkthdr.len;
1271 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]);
1272 for (i = 0; i < nseg; i++) {
1273 hw->ix_ne[i].data = htobe32(segs[i].ds_addr);
1274 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len);
1275 hw->ix_ne[i].next = htobe32(next);
1277 len = 0; /* zero for segments > 1 */
1278 next += sizeof(hw->ix_ne[0]);
1280 hw->ix_ne[i-1].next = 0; /* zero last in chain */
1281 /* XXX flush descriptor instead of using uncached memory */
1283 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n",
1284 __func__, sc->tx_qid, npe->ix_neaddr,
1285 hw->ix_ne[0].data, hw->ix_ne[0].len);
1286 /* stick it on the tx q */
1287 /* XXX add vlan priority */
1288 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr);
1290 sc->npe_watchdog_timer = 5;
1292 if (sc->tx_free == NULL)
1293 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1297 npestart(struct ifnet *ifp)
1299 struct npe_softc *sc = ifp->if_softc;
1301 npestart_locked(ifp);
1306 npe_stopxmit(struct npe_softc *sc)
1308 struct npedma *dma = &sc->txdma;
1311 NPE_ASSERT_LOCKED(sc);
1314 for (i = 0; i < dma->nbuf; i++) {
1315 struct npebuf *npe = &dma->buf[i];
1317 if (npe->ix_m != NULL) {
1318 bus_dmamap_unload(dma->mtag, npe->ix_map);
1326 npe_stoprecv(struct npe_softc *sc)
1328 struct npedma *dma = &sc->rxdma;
1331 NPE_ASSERT_LOCKED(sc);
1334 for (i = 0; i < dma->nbuf; i++) {
1335 struct npebuf *npe = &dma->buf[i];
1337 if (npe->ix_m != NULL) {
1338 bus_dmamap_unload(dma->mtag, npe->ix_map);
1346 * Turn off interrupts, and stop the nic.
1349 npestop(struct npe_softc *sc)
1351 struct ifnet *ifp = sc->sc_ifp;
1353 /* disable transmitter and reciver in the MAC */
1354 WR4(sc, NPE_MAC_RX_CNTRL1,
1355 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1356 WR4(sc, NPE_MAC_TX_CNTRL1,
1357 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1359 sc->npe_watchdog_timer = 0;
1360 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1362 callout_stop(&sc->tick_ch);
1366 /* XXX go into loopback & drain q's? */
1367 /* XXX but beware of disabling tx above */
1370 * The MAC core rx/tx disable may leave the MAC hardware in an
1371 * unpredictable state. A hw reset is executed before resetting
1372 * all the MAC parameters to a known value.
1374 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1375 DELAY(NPE_MAC_RESET_DELAY);
1376 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1377 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1381 npewatchdog(struct npe_softc *sc)
1383 NPE_ASSERT_LOCKED(sc);
1385 if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0)
1388 device_printf(sc->sc_dev, "watchdog timeout\n");
1389 sc->sc_ifp->if_oerrors++;
1395 npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1397 struct npe_softc *sc = ifp->if_softc;
1398 struct mii_data *mii;
1399 struct ifreq *ifr = (struct ifreq *)data;
1401 #ifdef DEVICE_POLLING
1408 if ((ifp->if_flags & IFF_UP) == 0 &&
1409 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1410 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1413 /* reinitialize card on any parameter change */
1421 /* update multicast filter list. */
1430 mii = device_get_softc(sc->sc_mii);
1431 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1434 #ifdef DEVICE_POLLING
1436 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1437 if (mask & IFCAP_POLLING) {
1438 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1439 error = ether_poll_register(npe_poll, ifp);
1443 /* disable callbacks XXX txdone is shared */
1444 ixpqmgr_notify_disable(sc->rx_qid);
1445 ixpqmgr_notify_disable(sc->tx_doneqid);
1446 ifp->if_capenable |= IFCAP_POLLING;
1449 error = ether_poll_deregister(ifp);
1450 /* NB: always enable qmgr callbacks */
1452 /* enable qmgr callbacks */
1453 ixpqmgr_notify_enable(sc->rx_qid,
1454 IX_QMGR_Q_SOURCE_ID_NOT_E);
1455 ixpqmgr_notify_enable(sc->tx_doneqid,
1456 IX_QMGR_Q_SOURCE_ID_NOT_E);
1457 ifp->if_capenable &= ~IFCAP_POLLING;
1464 error = ether_ioctl(ifp, cmd, data);
1471 * Setup a traffic class -> rx queue mapping.
1474 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid)
1476 int npeid = npeconfig[device_get_unit(sc->sc_dev)].npeid;
1479 msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix;
1480 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4);
1481 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1485 * Update and reset the statistics in the NPE.
1488 npe_updatestats(struct npe_softc *sc)
1492 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL;
1493 msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1494 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */
1499 * Get the current statistics block.
1502 npe_getstats(struct npe_softc *sc)
1506 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL;
1507 msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1508 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1512 * Query the image id of the loaded firmware.
1515 npe_getimageid(struct npe_softc *sc)
1519 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL;
1521 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0;
1525 * Enable/disable loopback.
1528 npe_setloopback(struct npe_softc *sc, int ena)
1532 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0);
1534 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1539 npe_child_detached(device_t dev, device_t child)
1541 struct npe_softc *sc;
1543 sc = device_get_softc(dev);
1544 if (child == sc->sc_mii)
1549 * MII bus support routines.
1551 * NB: ixp425 has one PHY per NPE
1554 npe_mii_mdio_read(struct npe_softc *sc, int reg)
1556 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)
1559 /* NB: registers are known to be sequential */
1560 v = (MII_RD4(sc, reg+0) & 0xff) << 0;
1561 v |= (MII_RD4(sc, reg+4) & 0xff) << 8;
1562 v |= (MII_RD4(sc, reg+8) & 0xff) << 16;
1563 v |= (MII_RD4(sc, reg+12) & 0xff) << 24;
1569 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)
1571 #define MII_WR4(sc, reg, v) \
1572 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)
1574 /* NB: registers are known to be sequential */
1575 MII_WR4(sc, reg+0, cmd & 0xff);
1576 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);
1577 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);
1578 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);
1583 npe_mii_mdio_wait(struct npe_softc *sc)
1585 #define MAXTRIES 100 /* XXX */
1589 for (i = 0; i < MAXTRIES; i++) {
1590 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD);
1591 if ((v & NPE_MII_GO) == 0)
1594 return 0; /* NB: timeout */
1599 npe_miibus_readreg(device_t dev, int phy, int reg)
1601 struct npe_softc *sc = device_get_softc(dev);
1604 if (phy != device_get_unit(dev)) /* XXX */
1606 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1608 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1609 if (npe_mii_mdio_wait(sc))
1610 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
1612 v = 0xffff | NPE_MII_READ_FAIL;
1613 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff);
1618 npe_miibus_writereg(device_t dev, int phy, int reg, int data)
1620 struct npe_softc *sc = device_get_softc(dev);
1623 if (phy != device_get_unit(dev)) /* XXX */
1625 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1626 | data | NPE_MII_WRITE
1628 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1629 /* XXX complain about timeout */
1630 (void) npe_mii_mdio_wait(sc);
1634 npe_miibus_statchg(device_t dev)
1636 struct npe_softc *sc = device_get_softc(dev);
1637 struct mii_data *mii = device_get_softc(sc->sc_mii);
1640 /* sync MAC duplex state */
1641 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);
1642 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);
1643 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1644 tx1 &= ~NPE_TX_CNTRL1_DUPLEX;
1645 rx1 |= NPE_RX_CNTRL1_PAUSE_EN;
1647 tx1 |= NPE_TX_CNTRL1_DUPLEX;
1648 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN;
1650 WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1651 WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
1654 static device_method_t npe_methods[] = {
1655 /* Device interface */
1656 DEVMETHOD(device_probe, npe_probe),
1657 DEVMETHOD(device_attach, npe_attach),
1658 DEVMETHOD(device_detach, npe_detach),
1661 DEVMETHOD(bus_child_detached, npe_child_detached),
1664 DEVMETHOD(miibus_readreg, npe_miibus_readreg),
1665 DEVMETHOD(miibus_writereg, npe_miibus_writereg),
1666 DEVMETHOD(miibus_statchg, npe_miibus_statchg),
1671 static driver_t npe_driver = {
1674 sizeof(struct npe_softc),
1677 DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0);
1678 DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0);
1679 MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1);
1680 MODULE_DEPEND(npe, miibus, 1, 1, 1);
1681 MODULE_DEPEND(npe, ether, 1, 1, 1);