2 * Copyright (c) 2006 Sam Leffler. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
29 * Intel XScale NPE Ethernet driver.
31 * This driver handles the two ports present on the IXP425.
32 * Packet processing is done by the Network Processing Engines
33 * (NPE's) that work together with a MAC and PHY. The MAC
34 * is also mapped to the XScale cpu; the PHY is accessed via
35 * the MAC. NPE-XScale communication happens through h/w
36 * queues managed by the Q Manager block.
38 * The code here replaces the ethAcc, ethMii, and ethDB classes
39 * in the Intel Access Library (IAL) and the OS-specific driver.
41 * XXX add vlan support
43 #ifdef HAVE_KERNEL_OPTION_HEADERS
44 #include "opt_device_polling.h"
47 #include <sys/param.h>
48 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/module.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <sys/endian.h>
59 #include <machine/bus.h>
61 #include <net/ethernet.h>
63 #include <net/if_arp.h>
64 #include <net/if_dl.h>
65 #include <net/if_media.h>
66 #include <net/if_mib.h>
67 #include <net/if_types.h>
70 #include <netinet/in.h>
71 #include <netinet/in_systm.h>
72 #include <netinet/in_var.h>
73 #include <netinet/ip.h>
77 #include <net/bpfdesc.h>
79 #include <arm/xscale/ixp425/ixp425reg.h>
80 #include <arm/xscale/ixp425/ixp425var.h>
81 #include <arm/xscale/ixp425/ixp425_qmgr.h>
82 #include <arm/xscale/ixp425/ixp425_npevar.h>
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
86 #include <arm/xscale/ixp425/if_npereg.h>
88 #include "miibus_if.h"
91 * XXX: For the main bus dma tag. Can go away if the new method to get the
92 * dma tag from the parent got MFC'd into RELENG_6.
94 extern struct ixp425_softc *ixp425_softc;
97 struct npebuf *ix_next; /* chain to next buffer */
98 void *ix_m; /* backpointer to mbuf */
99 bus_dmamap_t ix_map; /* bus dma map for associated data */
100 struct npehwbuf *ix_hw; /* associated h/w block */
101 uint32_t ix_neaddr; /* phys address of ix_hw */
106 int nbuf; /* # npebuf's allocated */
107 bus_dma_tag_t mtag; /* bus dma tag for mbuf data */
108 struct npehwbuf *hwbuf; /* NPE h/w buffers */
109 bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */
110 bus_dmamap_t buf_map;
111 bus_addr_t buf_phys; /* phys addr of buffers */
112 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */
116 /* XXX mii requires this be first; do not move! */
117 struct ifnet *sc_ifp; /* ifnet pointer */
118 struct mtx sc_mtx; /* basically a perimeter lock */
120 bus_space_tag_t sc_iot;
121 bus_space_handle_t sc_ioh; /* MAC register window */
122 device_t sc_mii; /* child miibus */
123 bus_space_handle_t sc_miih; /* MII register window */
124 struct ixpnpe_softc *sc_npe; /* NPE support */
125 int sc_debug; /* DPRINTF* control */
127 struct callout tick_ch; /* Tick callout */
128 int npe_watchdog_timer;
130 struct npebuf *tx_free; /* list of free tx buffers */
132 bus_addr_t buf_phys; /* XXX for returning a value */
133 int rx_qid; /* rx qid */
134 int rx_freeqid; /* rx free buffers qid */
135 int tx_qid; /* tx qid */
136 int tx_doneqid; /* tx completed qid */
137 struct ifmib_iso_8802_3 mibdata;
138 bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */
139 struct npestats *sc_stats;
140 bus_dmamap_t sc_stats_map;
141 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */
145 * Per-unit static configuration for IXP425. The tx and
146 * rx free Q id's are fixed by the NPE microcode. The
147 * rx Q id's are programmed to be separate to simplify
148 * multi-port processing. It may be better to handle
149 * all traffic through one Q (as done by the Intel drivers).
151 * Note that the PHY's are accessible only from MAC A
152 * on the IXP425. This and other platform-specific
153 * assumptions probably need to be handled through hints.
155 static const struct {
156 const char *desc; /* device description */
157 int npeid; /* NPE assignment */
158 uint32_t imageid; /* NPE firmware image id */
167 } npeconfig[NPE_PORTS_MAX] = {
168 { .desc = "IXP NPE-B",
170 .imageid = IXP425_NPE_B_IMAGEID,
171 .regbase = IXP425_MAC_A_HWBASE,
172 .regsize = IXP425_MAC_A_SIZE,
173 .miibase = IXP425_MAC_A_HWBASE,
174 .miisize = IXP425_MAC_A_SIZE,
180 { .desc = "IXP NPE-C",
182 .imageid = IXP425_NPE_C_IMAGEID,
183 .regbase = IXP425_MAC_B_HWBASE,
184 .regsize = IXP425_MAC_B_SIZE,
185 .miibase = IXP425_MAC_A_HWBASE,
186 .miisize = IXP425_MAC_A_SIZE,
193 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */
195 static __inline uint32_t
196 RD4(struct npe_softc *sc, bus_size_t off)
198 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
202 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
204 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
207 #define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
208 #define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
209 #define NPE_LOCK_INIT(_sc) \
210 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
211 MTX_NETWORK_LOCK, MTX_DEF)
212 #define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
213 #define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
214 #define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
216 static devclass_t npe_devclass;
218 static int npe_activate(device_t dev);
219 static void npe_deactivate(device_t dev);
220 static int npe_ifmedia_update(struct ifnet *ifp);
221 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr);
222 static void npe_setmac(struct npe_softc *sc, u_char *eaddr);
223 static void npe_getmac(struct npe_softc *sc, u_char *eaddr);
224 static void npe_txdone(int qid, void *arg);
225 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *,
227 static void npe_rxdone(int qid, void *arg);
228 static void npeinit(void *);
229 static void npestart_locked(struct ifnet *);
230 static void npestart(struct ifnet *);
231 static void npestop(struct npe_softc *);
232 static void npewatchdog(struct npe_softc *);
233 static int npeioctl(struct ifnet * ifp, u_long, caddr_t);
235 static int npe_setrxqosentry(struct npe_softc *, int classix,
236 int trafclass, int qid);
237 static int npe_updatestats(struct npe_softc *);
239 static int npe_getstats(struct npe_softc *);
240 static uint32_t npe_getimageid(struct npe_softc *);
241 static int npe_setloopback(struct npe_softc *, int ena);
244 /* NB: all tx done processing goes through one queue */
245 static int tx_doneqid = -1;
247 SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP425 NPE driver parameters");
249 static int npe_debug = 0;
250 SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug,
251 0, "IXP425 NPE network interface debug msgs");
252 TUNABLE_INT("hw.npe.npe", &npe_debug);
253 #define DPRINTF(sc, fmt, ...) do { \
254 if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \
256 #define DPRINTFn(n, sc, fmt, ...) do { \
257 if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\
259 static int npe_tickinterval = 3; /* npe_tick frequency (secs) */
260 SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval,
261 0, "periodic work interval (secs)");
262 TUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval);
264 static int npe_rxbuf = 64; /* # rx buffers to allocate */
265 SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf,
266 0, "rx buffers allocated");
267 TUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf);
268 static int npe_txbuf = 128; /* # tx buffers to allocate */
269 SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf,
270 0, "tx buffers allocated");
271 TUNABLE_INT("hw.npe.txbuf", &npe_txbuf);
274 npe_probe(device_t dev)
276 int unit = device_get_unit(dev);
278 if (unit >= NPE_PORTS_MAX) {
279 device_printf(dev, "unit %d not supported\n", unit);
282 /* XXX check feature register to see if enabled */
283 device_set_desc(dev, npeconfig[unit].desc);
288 npe_attach(device_t dev)
290 struct npe_softc *sc = device_get_softc(dev);
291 struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
292 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
293 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
294 struct ifnet *ifp = NULL;
299 sc->sc_iot = sa->sc_iot;
301 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
302 sc->sc_debug = npe_debug;
303 sc->sc_tickinterval = npe_tickinterval;
305 sc->sc_npe = ixpnpe_attach(dev);
306 if (sc->sc_npe == NULL) {
307 error = EIO; /* XXX */
311 error = npe_activate(dev);
315 npe_getmac(sc, eaddr);
317 /* NB: must be setup prior to invoking mii code */
318 sc->sc_ifp = ifp = if_alloc(IFT_ETHER);
319 if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) {
320 device_printf(dev, "Cannot find my PHY.\n");
326 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
328 ifp->if_start = npestart;
329 ifp->if_ioctl = npeioctl;
330 ifp->if_init = npeinit;
331 IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1);
332 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
333 IFQ_SET_READY(&ifp->if_snd);
334 ifp->if_linkmib = &sc->mibdata;
335 ifp->if_linkmiblen = sizeof(sc->mibdata);
336 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS;
337 #ifdef DEVICE_POLLING
338 ifp->if_capabilities |= IFCAP_POLLING;
341 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug",
342 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
343 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval",
344 CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency");
346 ether_ifattach(ifp, eaddr);
356 npe_detach(device_t dev)
358 struct npe_softc *sc = device_get_softc(dev);
359 struct ifnet *ifp = sc->sc_ifp;
361 #ifdef DEVICE_POLLING
362 if (ifp->if_capenable & IFCAP_POLLING)
363 ether_poll_deregister(ifp);
370 NPE_LOCK_DESTROY(sc);
372 if (sc->sc_npe != NULL)
373 ixpnpe_detach(sc->sc_npe);
378 * Compute and install the multicast filter.
381 npe_setmcast(struct npe_softc *sc)
383 struct ifnet *ifp = sc->sc_ifp;
384 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN];
387 if (ifp->if_flags & IFF_PROMISC) {
388 memset(mask, 0, ETHER_ADDR_LEN);
389 memset(addr, 0, ETHER_ADDR_LEN);
390 } else if (ifp->if_flags & IFF_ALLMULTI) {
391 static const uint8_t allmulti[ETHER_ADDR_LEN] =
392 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
393 memcpy(mask, allmulti, ETHER_ADDR_LEN);
394 memcpy(addr, allmulti, ETHER_ADDR_LEN);
396 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
397 struct ifmultiaddr *ifma;
400 memset(clr, 0, ETHER_ADDR_LEN);
401 memset(set, 0xff, ETHER_ADDR_LEN);
404 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
405 if (ifma->ifma_addr->sa_family != AF_LINK)
407 mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
408 for (i = 0; i < ETHER_ADDR_LEN; i++) {
415 for (i = 0; i < ETHER_ADDR_LEN; i++) {
416 mask[i] = set[i] | ~clr[i];
422 * Write the mask and address registers.
424 for (i = 0; i < ETHER_ADDR_LEN; i++) {
425 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
426 WR4(sc, NPE_MAC_ADDR(i), addr[i]);
431 npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
433 struct npe_softc *sc;
437 sc = (struct npe_softc *)arg;
438 sc->buf_phys = segs[0].ds_addr;
442 npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
443 const char *name, int nbuf, int maxseg)
447 memset(dma, 0, sizeof(dma));
452 /* DMA tag for mapped mbufs */
453 error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0,
454 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
455 MCLBYTES, maxseg, MCLBYTES, 0,
456 busdma_lock_mutex, &sc->sc_mtx, &dma->mtag);
458 device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, "
459 "error %u\n", dma->name, error);
463 /* DMA tag and map for the NPE buffers */
464 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
465 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
466 nbuf * sizeof(struct npehwbuf), 1,
467 nbuf * sizeof(struct npehwbuf), 0,
468 busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag);
470 device_printf(sc->sc_dev,
471 "unable to create %s npebuf dma tag, error %u\n",
475 /* XXX COHERENT for now */
476 if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf,
477 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
478 &dma->buf_map) != 0) {
479 device_printf(sc->sc_dev,
480 "unable to allocate memory for %s h/w buffers, error %u\n",
485 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO);
486 if (dma->buf == NULL) {
487 device_printf(sc->sc_dev,
488 "unable to allocate memory for %s s/w buffers\n",
492 if (bus_dmamap_load(dma->buf_tag, dma->buf_map,
493 dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) {
494 device_printf(sc->sc_dev,
495 "unable to map memory for %s h/w buffers, error %u\n",
499 dma->buf_phys = sc->buf_phys;
500 for (i = 0; i < dma->nbuf; i++) {
501 struct npebuf *npe = &dma->buf[i];
502 struct npehwbuf *hw = &dma->hwbuf[i];
504 /* calculate offset to shared area */
505 npe->ix_neaddr = dma->buf_phys +
506 ((uintptr_t)hw - (uintptr_t)dma->hwbuf);
507 KASSERT((npe->ix_neaddr & 0x1f) == 0,
508 ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr));
509 error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT,
512 device_printf(sc->sc_dev,
513 "unable to create dmamap for %s buffer %u, "
514 "error %u\n", dma->name, i, error);
519 bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE);
524 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma)
528 if (dma->hwbuf != NULL) {
529 for (i = 0; i < dma->nbuf; i++) {
530 struct npebuf *npe = &dma->buf[i];
531 bus_dmamap_destroy(dma->mtag, npe->ix_map);
533 bus_dmamap_unload(dma->buf_tag, dma->buf_map);
534 bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map);
535 bus_dmamap_destroy(dma->buf_tag, dma->buf_map);
537 if (dma->buf != NULL)
538 free(dma->buf, M_TEMP);
540 bus_dma_tag_destroy(dma->buf_tag);
542 bus_dma_tag_destroy(dma->mtag);
543 memset(dma, 0, sizeof(*dma));
547 npe_activate(device_t dev)
549 struct npe_softc * sc = device_get_softc(dev);
550 int unit = device_get_unit(dev);
555 * Load NPE firmware and start it running. We assume
556 * that minor version bumps remain compatible so probe
557 * the firmware image starting with the expected version
558 * and then bump the minor version up to the max.
560 imageid = npeconfig[unit].imageid;
562 error = ixpnpe_init(sc->sc_npe, "npe_fw", imageid);
565 /* ESRCH is returned when the requested image is not present */
568 /* bump the minor version up to the max possible */
569 if (NPEIMAGE_MINOR(imageid) == 0xff)
574 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase,
575 npeconfig[unit].regsize, 0, &sc->sc_ioh)) {
576 device_printf(dev, "Cannot map registers 0x%x:0x%x\n",
577 npeconfig[unit].regbase, npeconfig[unit].regsize);
581 if (npeconfig[unit].miibase != npeconfig[unit].regbase) {
583 * The PHY's are only accessible from one MAC (it appears)
584 * so for other MAC's setup an additional mapping for
585 * frobbing the PHY registers.
587 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase,
588 npeconfig[unit].miisize, 0, &sc->sc_miih)) {
590 "Cannot map MII registers 0x%x:0x%x\n",
591 npeconfig[unit].miibase, npeconfig[unit].miisize);
595 sc->sc_miih = sc->sc_ioh;
596 error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG);
599 error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1);
603 /* setup statistics block */
604 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
605 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
606 sizeof(struct npestats), 1, sizeof(struct npestats), 0,
607 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag);
609 device_printf(sc->sc_dev, "unable to create stats tag, "
610 "error %u\n", error);
613 if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats,
614 BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) {
615 device_printf(sc->sc_dev,
616 "unable to allocate memory for stats block, error %u\n",
620 if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map,
621 sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) {
622 device_printf(sc->sc_dev,
623 "unable to load memory for stats block, error %u\n",
627 sc->sc_stats_phys = sc->buf_phys;
629 /* XXX disable half-bridge LEARNING+FILTERING feature */
632 * Setup h/w rx/tx queues. There are four q's:
633 * rx inbound q of rx'd frames
634 * rx_free pool of ixpbuf's for receiving frames
635 * tx outbound q of frames to send
636 * tx_done q of tx frames that have been processed
638 * The NPE handles the actual tx/rx process and the q manager
639 * handles the queues. The driver just writes entries to the
640 * q manager mailbox's and gets callbacks when there are rx'd
641 * frames to process or tx'd frames to reap. These callbacks
642 * are controlled by the q configurations; e.g. we get a
643 * callback when tx_done has 2 or more frames to process and
644 * when the rx q has at least one frame. These setings can
645 * changed at the time the q is configured.
647 sc->rx_qid = npeconfig[unit].rx_qid;
648 ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1,
649 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc);
650 sc->rx_freeqid = npeconfig[unit].rx_freeqid;
651 ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc);
652 /* tell the NPE to direct all traffic to rx_qid */
654 for (i = 0; i < 8; i++)
656 device_printf(sc->sc_dev, "remember to fix rx q setup\n");
657 for (i = 0; i < 4; i++)
659 npe_setrxqosentry(sc, i, 0, sc->rx_qid);
661 sc->tx_qid = npeconfig[unit].tx_qid;
662 sc->tx_doneqid = npeconfig[unit].tx_doneqid;
663 ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc);
664 if (tx_doneqid == -1) {
665 ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2,
666 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc);
667 tx_doneqid = sc->tx_doneqid;
670 KASSERT(npes[npeconfig[unit].npeid] == NULL,
671 ("npe %u already setup", npeconfig[unit].npeid));
672 npes[npeconfig[unit].npeid] = sc;
678 npe_deactivate(device_t dev)
680 struct npe_softc *sc = device_get_softc(dev);
681 int unit = device_get_unit(dev);
683 npes[npeconfig[unit].npeid] = NULL;
685 /* XXX disable q's */
686 if (sc->sc_npe != NULL)
687 ixpnpe_stop(sc->sc_npe);
688 if (sc->sc_stats != NULL) {
689 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map);
690 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats,
692 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map);
694 if (sc->sc_stats_tag != NULL)
695 bus_dma_tag_destroy(sc->sc_stats_tag);
696 npe_dma_destroy(sc, &sc->txdma);
697 npe_dma_destroy(sc, &sc->rxdma);
698 bus_generic_detach(sc->sc_dev);
700 device_delete_child(sc->sc_dev, sc->sc_mii);
702 /* XXX sc_ioh and sc_miih */
704 bus_release_resource(dev, SYS_RES_IOPORT,
705 rman_get_rid(sc->mem_res), sc->mem_res);
711 * Change media according to request.
714 npe_ifmedia_update(struct ifnet *ifp)
716 struct npe_softc *sc = ifp->if_softc;
717 struct mii_data *mii;
719 mii = device_get_softc(sc->sc_mii);
722 /* XXX push state ourself? */
728 * Notify the world which media we're using.
731 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
733 struct npe_softc *sc = ifp->if_softc;
734 struct mii_data *mii;
736 mii = device_get_softc(sc->sc_mii);
739 ifmr->ifm_active = mii->mii_media_active;
740 ifmr->ifm_status = mii->mii_media_status;
745 npe_addstats(struct npe_softc *sc)
747 #define MIBADD(x) sc->mibdata.x += be32toh(ns->x)
748 struct ifnet *ifp = sc->sc_ifp;
749 struct npestats *ns = sc->sc_stats;
751 MIBADD(dot3StatsAlignmentErrors);
752 MIBADD(dot3StatsFCSErrors);
753 MIBADD(dot3StatsSingleCollisionFrames);
754 MIBADD(dot3StatsMultipleCollisionFrames);
755 MIBADD(dot3StatsDeferredTransmissions);
756 MIBADD(dot3StatsLateCollisions);
757 MIBADD(dot3StatsExcessiveCollisions);
758 MIBADD(dot3StatsInternalMacTransmitErrors);
759 MIBADD(dot3StatsCarrierSenseErrors);
760 sc->mibdata.dot3StatsFrameTooLongs +=
761 be32toh(ns->RxLargeFramesDiscards)
762 + be32toh(ns->TxLargeFrameDiscards);
763 MIBADD(dot3StatsInternalMacReceiveErrors);
764 sc->mibdata.dot3StatsMissedFrames +=
765 be32toh(ns->RxOverrunDiscards)
766 + be32toh(ns->RxUnderflowEntryDiscards);
769 be32toh(ns->dot3StatsInternalMacTransmitErrors)
770 + be32toh(ns->dot3StatsCarrierSenseErrors)
771 + be32toh(ns->TxVLANIdFilterDiscards)
773 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors)
774 + be32toh(ns->dot3StatsInternalMacReceiveErrors)
775 + be32toh(ns->RxOverrunDiscards)
776 + be32toh(ns->RxUnderflowEntryDiscards)
778 ifp->if_collisions +=
779 be32toh(ns->dot3StatsSingleCollisionFrames)
780 + be32toh(ns->dot3StatsMultipleCollisionFrames)
788 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL)
789 struct npe_softc *sc = xsc;
790 struct mii_data *mii = device_get_softc(sc->sc_mii);
793 NPE_ASSERT_LOCKED(sc);
796 * NB: to avoid sleeping with the softc lock held we
797 * split the NPE msg processing into two parts. The
798 * request for statistics is sent w/o waiting for a
799 * reply and then on the next tick we retrieve the
800 * results. This works because npe_tick is the only
801 * code that talks via the mailbox's (except at setup).
802 * This likely can be handled better.
804 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) {
805 bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map,
806 BUS_DMASYNC_POSTREAD);
814 /* schedule next poll */
815 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc);
820 npe_setmac(struct npe_softc *sc, u_char *eaddr)
822 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
823 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
824 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
825 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
826 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
827 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
832 npe_getmac(struct npe_softc *sc, u_char *eaddr)
834 /* NB: the unicast address appears to be loaded from EEPROM on reset */
835 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;
836 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;
837 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;
838 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;
839 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;
840 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;
845 struct npebuf **tail;
850 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td)
852 struct ifnet *ifp = sc->sc_ifp;
855 *td->tail = sc->tx_free;
856 sc->tx_free = td->head;
858 * We're no longer busy, so clear the busy flag and call the
859 * start routine to xmit more packets.
861 ifp->if_opackets += td->count;
862 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
863 sc->npe_watchdog_timer = 0;
864 npestart_locked(ifp);
869 * Q manager callback on tx done queue. Reap mbufs
870 * and return tx buffers to the free list. Finally
871 * restart output. Note the microcode has only one
872 * txdone q wired into it so we must use the NPE ID
873 * returned with each npehwbuf to decide where to
877 npe_txdone(int qid, void *arg)
879 #define P2V(a, dma) \
880 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
881 struct npe_softc *sc0 = arg;
882 struct npe_softc *sc;
884 struct txdone *td, q[NPE_MAX];
887 /* XXX no NPE-A support */
888 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0;
889 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0;
890 /* XXX max # at a time? */
891 while (ixpqmgr_qread(qid, &entry) == 0) {
892 DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n",
893 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry));
895 sc = npes[NPE_QM_Q_NPE(entry)];
896 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma);
900 td = &q[NPE_QM_Q_NPE(entry)];
902 td->tail = &npe->ix_next;
907 npe_txdone_finish(npes[NPE_B], &q[NPE_B]);
909 npe_txdone_finish(npes[NPE_C], &q[NPE_C]);
914 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m)
916 bus_dma_segment_t segs[1];
917 struct npedma *dma = &sc->rxdma;
922 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
926 KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN,
927 ("ext_size %d", m->m_ext.ext_size));
928 m->m_pkthdr.len = m->m_len = 1536;
929 /* backload payload and align ip hdr */
930 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN));
931 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m,
938 hw->ix_ne[0].data = htobe32(segs[0].ds_addr);
939 /* NB: NPE requires length be a multiple of 64 */
940 /* NB: buffer length is shifted in word */
941 hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16);
942 hw->ix_ne[0].next = 0;
944 /* Flush the memory in the mbuf */
945 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD);
950 * RX q processing for a specific NPE. Claim entries
951 * from the hardware queue and pass the frames up the
952 * stack. Pass the rx buffers to the free list.
955 npe_rxdone(int qid, void *arg)
957 #define P2V(a, dma) \
958 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
959 struct npe_softc *sc = arg;
960 struct npedma *dma = &sc->rxdma;
963 while (ixpqmgr_qread(qid, &entry) == 0) {
964 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma);
967 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n",
968 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len);
970 * Allocate a new mbuf to replenish the rx buffer.
971 * If doing so fails we drop the rx'd frame so we
972 * can reuse the previous mbuf. When we're able to
973 * allocate a new mbuf dispatch the mbuf w/ rx'd
974 * data up the stack and replace it with the newly
977 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
979 struct mbuf *mrx = npe->ix_m;
980 struct npehwbuf *hw = npe->ix_hw;
981 struct ifnet *ifp = sc->sc_ifp;
983 /* Flush mbuf memory for rx'd data */
984 bus_dmamap_sync(dma->mtag, npe->ix_map,
985 BUS_DMASYNC_POSTREAD);
987 /* XXX flush hw buffer; works now 'cuz coherent */
988 /* set m_len etc. per rx frame size */
989 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff;
990 mrx->m_pkthdr.len = mrx->m_len;
991 mrx->m_pkthdr.rcvif = ifp;
992 mrx->m_flags |= M_HASFCS;
995 ifp->if_input(ifp, mrx);
997 /* discard frame and re-use mbuf */
1000 if (npe_rxbuf_init(sc, npe, m) == 0) {
1001 /* return npe buf to rx free list */
1002 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1004 /* XXX should not happen */
1010 #ifdef DEVICE_POLLING
1012 npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1014 struct npe_softc *sc = ifp->if_softc;
1016 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1017 npe_rxdone(sc->rx_qid, sc);
1018 npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */
1021 #endif /* DEVICE_POLLING */
1024 npe_startxmit(struct npe_softc *sc)
1026 struct npedma *dma = &sc->txdma;
1029 NPE_ASSERT_LOCKED(sc);
1031 for (i = 0; i < dma->nbuf; i++) {
1032 struct npebuf *npe = &dma->buf[i];
1033 if (npe->ix_m != NULL) {
1034 /* NB: should not happen */
1035 device_printf(sc->sc_dev,
1036 "%s: free mbuf at entry %u\n", __func__, i);
1040 npe->ix_next = sc->tx_free;
1046 npe_startrecv(struct npe_softc *sc)
1048 struct npedma *dma = &sc->rxdma;
1052 NPE_ASSERT_LOCKED(sc);
1053 for (i = 0; i < dma->nbuf; i++) {
1055 npe_rxbuf_init(sc, npe, npe->ix_m);
1056 /* set npe buf on rx free list */
1057 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1062 * Reset and initialize the chip
1065 npeinit_locked(void *xsc)
1067 struct npe_softc *sc = xsc;
1068 struct ifnet *ifp = sc->sc_ifp;
1070 NPE_ASSERT_LOCKED(sc);
1071 if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/
1076 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1077 DELAY(NPE_MAC_RESET_DELAY);
1078 /* configure MAC to generate MDC clock */
1079 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1081 /* disable transmitter and reciver in the MAC */
1082 WR4(sc, NPE_MAC_RX_CNTRL1,
1083 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1084 WR4(sc, NPE_MAC_TX_CNTRL1,
1085 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1088 * Set the MAC core registers.
1090 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
1091 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
1092 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
1093 /* thresholds determined by NPE firmware FS */
1094 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
1095 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
1096 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */
1097 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
1098 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
1099 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
1100 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
1101 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */
1103 WR4(sc, NPE_MAC_TX_CNTRL1,
1104 NPE_TX_CNTRL1_RETRY /* retry failed xmits */
1105 | NPE_TX_CNTRL1_FCS_EN /* append FCS */
1106 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */
1107 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */
1108 /* XXX pad strip? */
1109 WR4(sc, NPE_MAC_RX_CNTRL1,
1110 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */
1111 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */
1112 WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1114 npe_setmac(sc, IF_LLADDR(ifp));
1120 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1121 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1122 sc->npe_watchdog_timer = 0; /* just in case */
1124 /* enable transmitter and reciver in the MAC */
1125 WR4(sc, NPE_MAC_RX_CNTRL1,
1126 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);
1127 WR4(sc, NPE_MAC_TX_CNTRL1,
1128 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);
1130 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc);
1136 struct npe_softc *sc = xsc;
1143 * Defragment an mbuf chain, returning at most maxfrags separate
1144 * mbufs+clusters. If this is not possible NULL is returned and
1145 * the original mbuf chain is left in it's present (potentially
1146 * modified) state. We use two techniques: collapsing consecutive
1147 * mbufs and replacing consecutive mbufs by a cluster.
1149 static struct mbuf *
1150 npe_defrag(struct mbuf *m0, int how, int maxfrags)
1152 struct mbuf *m, *n, *n2, **prev;
1156 * Calculate the current number of frags.
1159 for (m = m0; m != NULL; m = m->m_next)
1162 * First, try to collapse mbufs. Note that we always collapse
1163 * towards the front so we don't need to deal with moving the
1164 * pkthdr. This may be suboptimal if the first mbuf has much
1165 * less data than the following.
1173 if ((m->m_flags & M_RDONLY) == 0 &&
1174 n->m_len < M_TRAILINGSPACE(m)) {
1175 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
1177 m->m_len += n->m_len;
1178 m->m_next = n->m_next;
1180 if (--curfrags <= maxfrags)
1185 KASSERT(maxfrags > 1,
1186 ("maxfrags %u, but normal collapse failed", maxfrags));
1188 * Collapse consecutive mbufs to a cluster.
1190 prev = &m0->m_next; /* NB: not the first mbuf */
1191 while ((n = *prev) != NULL) {
1192 if ((n2 = n->m_next) != NULL &&
1193 n->m_len + n2->m_len < MCLBYTES) {
1194 m = m_getcl(how, MT_DATA, 0);
1197 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
1198 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
1200 m->m_len = n->m_len + n2->m_len;
1201 m->m_next = n2->m_next;
1205 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
1208 * Still not there, try the normal collapse
1209 * again before we allocate another cluster.
1216 * No place where we can collapse to a cluster; punt.
1217 * This can occur if, for example, you request 2 frags
1218 * but the packet requires that both be clusters (we
1219 * never reallocate the first mbuf to avoid moving the
1227 * Dequeue packets and place on the h/w transmit queue.
1230 npestart_locked(struct ifnet *ifp)
1232 struct npe_softc *sc = ifp->if_softc;
1234 struct npehwbuf *hw;
1236 struct npedma *dma = &sc->txdma;
1237 bus_dma_segment_t segs[NPE_MAXSEG];
1238 int nseg, len, error, i;
1241 NPE_ASSERT_LOCKED(sc);
1242 /* XXX can this happen? */
1243 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1246 while (sc->tx_free != NULL) {
1247 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1250 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1254 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map,
1256 if (error == EFBIG) {
1257 n = npe_defrag(m, M_DONTWAIT, NPE_MAXSEG);
1259 if_printf(ifp, "%s: too many fragments %u\n",
1265 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map,
1268 if (error != 0 || nseg == 0) {
1269 if_printf(ifp, "%s: error %u nseg %u\n",
1270 __func__, error, nseg);
1274 sc->tx_free = npe->ix_next;
1276 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE);
1279 * Tap off here if there is a bpf listener.
1285 len = m->m_pkthdr.len;
1286 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]);
1287 for (i = 0; i < nseg; i++) {
1288 hw->ix_ne[i].data = htobe32(segs[i].ds_addr);
1289 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len);
1290 hw->ix_ne[i].next = htobe32(next);
1292 len = 0; /* zero for segments > 1 */
1293 next += sizeof(hw->ix_ne[0]);
1295 hw->ix_ne[i-1].next = 0; /* zero last in chain */
1296 /* XXX flush descriptor instead of using uncached memory */
1298 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n",
1299 __func__, sc->tx_qid, npe->ix_neaddr,
1300 hw->ix_ne[0].data, hw->ix_ne[0].len);
1301 /* stick it on the tx q */
1302 /* XXX add vlan priority */
1303 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr);
1305 sc->npe_watchdog_timer = 5;
1307 if (sc->tx_free == NULL)
1308 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1312 npestart(struct ifnet *ifp)
1314 struct npe_softc *sc = ifp->if_softc;
1316 npestart_locked(ifp);
1321 npe_stopxmit(struct npe_softc *sc)
1323 struct npedma *dma = &sc->txdma;
1326 NPE_ASSERT_LOCKED(sc);
1329 for (i = 0; i < dma->nbuf; i++) {
1330 struct npebuf *npe = &dma->buf[i];
1332 if (npe->ix_m != NULL) {
1333 bus_dmamap_unload(dma->mtag, npe->ix_map);
1341 npe_stoprecv(struct npe_softc *sc)
1343 struct npedma *dma = &sc->rxdma;
1346 NPE_ASSERT_LOCKED(sc);
1349 for (i = 0; i < dma->nbuf; i++) {
1350 struct npebuf *npe = &dma->buf[i];
1352 if (npe->ix_m != NULL) {
1353 bus_dmamap_unload(dma->mtag, npe->ix_map);
1361 * Turn off interrupts, and stop the nic.
1364 npestop(struct npe_softc *sc)
1366 struct ifnet *ifp = sc->sc_ifp;
1368 /* disable transmitter and reciver in the MAC */
1369 WR4(sc, NPE_MAC_RX_CNTRL1,
1370 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1371 WR4(sc, NPE_MAC_TX_CNTRL1,
1372 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1374 sc->npe_watchdog_timer = 0;
1375 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1377 callout_stop(&sc->tick_ch);
1381 /* XXX go into loopback & drain q's? */
1382 /* XXX but beware of disabling tx above */
1385 * The MAC core rx/tx disable may leave the MAC hardware in an
1386 * unpredictable state. A hw reset is executed before resetting
1387 * all the MAC parameters to a known value.
1389 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1390 DELAY(NPE_MAC_RESET_DELAY);
1391 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1392 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1396 npewatchdog(struct npe_softc *sc)
1398 NPE_ASSERT_LOCKED(sc);
1400 if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0)
1403 device_printf(sc->sc_dev, "watchdog timeout\n");
1404 sc->sc_ifp->if_oerrors++;
1410 npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1412 struct npe_softc *sc = ifp->if_softc;
1413 struct mii_data *mii;
1414 struct ifreq *ifr = (struct ifreq *)data;
1416 #ifdef DEVICE_POLLING
1423 if ((ifp->if_flags & IFF_UP) == 0 &&
1424 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1425 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1428 /* reinitialize card on any parameter change */
1436 /* update multicast filter list. */
1445 mii = device_get_softc(sc->sc_mii);
1446 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1449 #ifdef DEVICE_POLLING
1451 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1452 if (mask & IFCAP_POLLING) {
1453 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1454 error = ether_poll_register(npe_poll, ifp);
1458 /* disable callbacks XXX txdone is shared */
1459 ixpqmgr_notify_disable(sc->rx_qid);
1460 ixpqmgr_notify_disable(sc->tx_doneqid);
1461 ifp->if_capenable |= IFCAP_POLLING;
1464 error = ether_poll_deregister(ifp);
1465 /* NB: always enable qmgr callbacks */
1467 /* enable qmgr callbacks */
1468 ixpqmgr_notify_enable(sc->rx_qid,
1469 IX_QMGR_Q_SOURCE_ID_NOT_E);
1470 ixpqmgr_notify_enable(sc->tx_doneqid,
1471 IX_QMGR_Q_SOURCE_ID_NOT_E);
1472 ifp->if_capenable &= ~IFCAP_POLLING;
1479 error = ether_ioctl(ifp, cmd, data);
1486 * Setup a traffic class -> rx queue mapping.
1489 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid)
1491 int npeid = npeconfig[device_get_unit(sc->sc_dev)].npeid;
1494 msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix;
1495 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4);
1496 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1500 * Update and reset the statistics in the NPE.
1503 npe_updatestats(struct npe_softc *sc)
1507 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL;
1508 msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1509 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */
1514 * Get the current statistics block.
1517 npe_getstats(struct npe_softc *sc)
1521 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL;
1522 msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1523 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1527 * Query the image id of the loaded firmware.
1530 npe_getimageid(struct npe_softc *sc)
1534 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL;
1536 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0;
1540 * Enable/disable loopback.
1543 npe_setloopback(struct npe_softc *sc, int ena)
1547 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0);
1549 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1554 npe_child_detached(device_t dev, device_t child)
1556 struct npe_softc *sc;
1558 sc = device_get_softc(dev);
1559 if (child == sc->sc_mii)
1564 * MII bus support routines.
1566 * NB: ixp425 has one PHY per NPE
1569 npe_mii_mdio_read(struct npe_softc *sc, int reg)
1571 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)
1574 /* NB: registers are known to be sequential */
1575 v = (MII_RD4(sc, reg+0) & 0xff) << 0;
1576 v |= (MII_RD4(sc, reg+4) & 0xff) << 8;
1577 v |= (MII_RD4(sc, reg+8) & 0xff) << 16;
1578 v |= (MII_RD4(sc, reg+12) & 0xff) << 24;
1584 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)
1586 #define MII_WR4(sc, reg, v) \
1587 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)
1589 /* NB: registers are known to be sequential */
1590 MII_WR4(sc, reg+0, cmd & 0xff);
1591 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);
1592 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);
1593 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);
1598 npe_mii_mdio_wait(struct npe_softc *sc)
1600 #define MAXTRIES 100 /* XXX */
1604 for (i = 0; i < MAXTRIES; i++) {
1605 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD);
1606 if ((v & NPE_MII_GO) == 0)
1609 return 0; /* NB: timeout */
1614 npe_miibus_readreg(device_t dev, int phy, int reg)
1616 struct npe_softc *sc = device_get_softc(dev);
1619 if (phy != device_get_unit(dev)) /* XXX */
1621 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1623 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1624 if (npe_mii_mdio_wait(sc))
1625 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
1627 v = 0xffff | NPE_MII_READ_FAIL;
1628 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff);
1633 npe_miibus_writereg(device_t dev, int phy, int reg, int data)
1635 struct npe_softc *sc = device_get_softc(dev);
1638 if (phy != device_get_unit(dev)) /* XXX */
1640 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1641 | data | NPE_MII_WRITE
1643 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1644 /* XXX complain about timeout */
1645 (void) npe_mii_mdio_wait(sc);
1649 npe_miibus_statchg(device_t dev)
1651 struct npe_softc *sc = device_get_softc(dev);
1652 struct mii_data *mii = device_get_softc(sc->sc_mii);
1655 /* sync MAC duplex state */
1656 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);
1657 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);
1658 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1659 tx1 &= ~NPE_TX_CNTRL1_DUPLEX;
1660 rx1 |= NPE_RX_CNTRL1_PAUSE_EN;
1662 tx1 |= NPE_TX_CNTRL1_DUPLEX;
1663 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN;
1665 WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1666 WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
1669 static device_method_t npe_methods[] = {
1670 /* Device interface */
1671 DEVMETHOD(device_probe, npe_probe),
1672 DEVMETHOD(device_attach, npe_attach),
1673 DEVMETHOD(device_detach, npe_detach),
1676 DEVMETHOD(bus_child_detached, npe_child_detached),
1679 DEVMETHOD(miibus_readreg, npe_miibus_readreg),
1680 DEVMETHOD(miibus_writereg, npe_miibus_writereg),
1681 DEVMETHOD(miibus_statchg, npe_miibus_statchg),
1686 static driver_t npe_driver = {
1689 sizeof(struct npe_softc),
1692 DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0);
1693 DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0);
1694 MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1);
1695 MODULE_DEPEND(npe, miibus, 1, 1, 1);
1696 MODULE_DEPEND(npe, ether, 1, 1, 1);