1 /* $NetBSD: ixdp425_pci.c,v 1.6 2009/10/21 14:15:51 rmind Exp $ */
3 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
6 * Ichiro FUKUHARA <ichiro@ichiro.org>.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #define _ARM32_BUS_DMA_PRIVATE
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
43 #include <dev/pci/pcivar.h>
45 #include <machine/bus.h>
46 #include <machine/intr.h>
48 #include <arm/xscale/ixp425/ixp425reg.h>
49 #include <arm/xscale/ixp425/ixp425var.h>
50 #include <arm/xscale/ixp425/ixp425_intr.h>
51 #include <arm/xscale/ixp425/ixdp425reg.h>
54 ixp425_md_attach(device_t dev)
56 struct ixp425_softc *sc = device_get_softc(device_get_parent(dev));
57 struct ixppcib_softc *pci_sc = device_get_softc(dev);
61 /* PCI Reset Assert */
62 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
63 reg &= ~(1U << GPIO_PCI_RESET);
64 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
66 /* PCI Clock Disable */
67 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
69 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
73 * Output: PCI_CLK, PCI_RESET
74 * Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
76 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
77 reg &= ~(1U << GPIO_PCI_CLK);
78 reg &= ~(1U << GPIO_PCI_RESET);
79 reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
80 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
81 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
84 * Set GPIO interrupt type
85 * PCI_INT_A, PCI_INTB, PCI_INT_C, PCI_INT_D: Active Low
87 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));
88 reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);
89 reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);
90 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);
92 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));
93 reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);
94 reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);
95 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);
97 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));
98 reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);
99 reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);
100 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);
102 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD));
103 reg &= ~GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_MASK);
104 reg |= GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_ACT_LOW);
105 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD), reg);
108 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
109 (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
110 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
112 /* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
114 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
115 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |
116 (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT));
118 /* PCI Clock Enable */
119 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
121 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
124 * wait 100us to satisfy "minimum reset assertion time from clock stable
125 * requirement of the PCI spec
128 /* PCI Reset deassert */
129 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
130 reg |= 1U << GPIO_PCI_RESET;
131 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
132 pci_sc->sc_irq_rman.rm_type = RMAN_ARRAY;
133 pci_sc->sc_irq_rman.rm_descr = "IXP425 PCI IRQs";
134 CTASSERT(PCI_INT_D < PCI_INT_A);
135 /* XXX this overlaps the irq's setup in ixp425_attach */
136 if (rman_init(&pci_sc->sc_irq_rman) != 0 ||
137 rman_manage_region(&pci_sc->sc_irq_rman, PCI_INT_D, PCI_INT_A) != 0)
138 panic("ixp425_md_attach: failed to set up IRQ rman");
141 #define IXP425_MAX_DEV 5
142 #define IXP425_MAX_LINE 4
145 ixp425_md_route_interrupt(device_t bridge, device_t device, int pin)
147 static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] = {
148 {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
149 {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
150 {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
151 {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
152 /* NB: for optional USB controller on Gateworks Avila */
153 {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
157 dev = pci_get_slot(device);
159 device_printf(bridge, "routing pin %d for %s\n", pin,
160 device_get_nameunit(device));
161 if (pin >= 1 && pin <= IXP425_MAX_LINE &&
162 dev >= 1 && dev <= IXP425_MAX_DEV) {
163 return (ixp425_pci_table[dev - 1][pin - 1]);
165 printf("ixppcib: no mapping for %d/%d/%d\n",
166 pci_get_bus(device), dev, pci_get_function(device));