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62 #ifndef _IXP425_NPEREG_H_
63 #define _IXP425_NPEREG_H_
65 /* signature found as 1st word in a microcode image library */
66 #define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF
67 /* marks end of header in a microcode image library */
68 #define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF
71 * Intel (R) IXP400 Software NPE Image ID Definition
73 * Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart()
74 * as input of type uint32_t which has the following fields format:
76 * Field [Bit Location]
77 * -----------------------------------
80 * NPE Functionality ID [23 - 16]
81 * Major Release Number [15 - 8]
82 * Minor Release Number [7 - 0]
84 #define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \
85 (((imageId) >> 24) & 0xf)
86 #define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \
87 (((imageId) >> 28) & 0xf)
88 #define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \
89 (((imageId) >> 16) & 0xff)
90 #define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \
91 (((imageId) >> 8) & 0xff)
92 #define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \
93 (((imageId) >> 0) & 0xff)
96 * Instruction and Data Memory Size (in words) for each NPE
99 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
100 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
101 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
103 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
104 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
105 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
107 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
108 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 4096
109 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 4096
111 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 4096
112 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 4096
113 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 4096
117 #define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 /* Execution Address */
118 #define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 /* Execution Data */
119 #define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 /* Execution Control */
120 #define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C /* Execution Count */
121 #define IX_NPEDL_REG_OFFSET_AP0 0x00000010 /* Action Point 0 */
122 #define IX_NPEDL_REG_OFFSET_AP1 0x00000014 /* Action Point 1 */
123 #define IX_NPEDL_REG_OFFSET_AP2 0x00000018 /* Action Point 2 */
124 #define IX_NPEDL_REG_OFFSET_AP3 0x0000001C /* Action Point 3 */
125 #define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 /* Watchpoint FIFO */
126 #define IX_NPEDL_REG_OFFSET_WC 0x00000024 /* Watch Count */
127 #define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 /* Profile Count */
128 #define IX_NPEDL_REG_OFFSET_STAT 0x0000002C /* Messaging Status */
129 #define IX_NPEDL_REG_OFFSET_CTL 0x00000030 /* Messaging Control */
130 #define IX_NPEDL_REG_OFFSET_MBST 0x00000034 /* Mailbox Status */
131 #define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 /* Message FIFO */
134 * Reset value for Mailbox (MBST) register
135 * NOTE that if used, it should be complemented with an NPE intruction
136 * to clear the Mailbox at the NPE side as well
138 #define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
140 #define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */
141 #define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */
142 #define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */
145 * EXCTL (Execution Control) Register commands
147 #define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */
148 #define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */
149 #define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */
150 #define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */
153 * Read/write operations use address in EXAD and data in EXDATA.
155 #define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 /* Read ins memory */
156 #define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 /* Write ins memory */
157 #define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 /* Read data memory */
158 #define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 /* Write data memory */
159 #define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 /* Read ECS register */
160 #define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 /* Write ECS register */
162 #define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C /* Clear Profile Count register */
166 * EXCTL (Execution Control) Register status bit masks
168 #define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
169 #define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
170 #define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
171 #define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */
174 * Executing Context Stack (ECS) level registers
176 #define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */
177 #define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */
178 #define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */
180 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */
181 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */
182 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */
184 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 /* reg 0 @ pri 2 ctx */
185 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 /* reg 1 @ pri 2 ctx */
186 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A /* reg 2 @ pri 2 ctx */
188 #define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C /* reg 0 @ debug ctx */
189 #define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D /* reg 1 @ debug ctx */
190 #define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E /* reg 2 @ debug ctx */
192 #define IX_NPEDL_ECS_INSTRUCT_REG 0x11 /* Instruction reg */
195 * Execution Access register reset values
197 #define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
198 #define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
199 #define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
200 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
201 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
202 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
203 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
204 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
205 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
206 #define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
207 #define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
208 #define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
209 #define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
212 * Masks used to read/write particular bits in Execution Access registers
215 #define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 /* Active bit */
216 #define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 /* NextPC bits */
217 #define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 /* LDUR bits */
219 #define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 /* NextPC bits */
220 #define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
222 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */
223 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */
227 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers.
230 #define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
231 #define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
233 #define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
234 #define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
237 * NPE core & co-processor instruction templates to load into NPE Instruction
238 * Register, for read/write of NPE register file registers.
242 * Read an 8-bit NPE internal logical register
243 * and return the value in the EXDATA register (aligned to MSB).
244 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
246 #define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
249 * Read a 16-bit NPE internal logical register
250 * and return the value in the EXDATA register (aligned to MSB).
251 * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
253 #define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
256 * Read a 16-bit NPE internal logical register
257 * and return the value in the EXDATA register.
258 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
260 #define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
263 * Write an 8-bit NPE internal logical register.
264 * NPE Assembler instruction: "mov8 d0, #0"
266 #define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
269 * Write a 16-bit NPE internal logical register.
270 * NPE Assembler instruction: "mov16 d0, #0"
272 #define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
275 * Write a 16-bit NPE internal logical register.
276 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
278 #define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
281 * Reset Mailbox (MBST) register
282 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
284 #define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
288 * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
290 #define IX_NPEDL_OFFSET_INSTR_SRC 4 /* src operand */
291 #define IX_NPEDL_OFFSET_INSTR_DEST 9 /* dest operand */
292 #define IX_NPEDL_OFFSET_INSTR_COPROC 18 /* coprocessor ins */
295 * Masks used to read/write particular bits of an NPE Instruction
299 * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
300 * SRC field of immediate-mode NPE instruction
302 #define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
305 * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
306 * COPROC field of immediate-mode NPE instruction
308 #define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
311 * LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
312 * to be used in COPROC field of immediate-mode NPE instruction
314 #define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
317 * Number of left-shifts required to align most-sig 11 bits of 16-bit
318 * data value into COPROC field of immediate-mode NPE instruction
320 #define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
321 (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
324 * LDUR value used with immediate-mode NPE Instructions by the NpeDl
325 * for writing to NPE internal logical registers
327 #define IX_NPEDL_WR_INSTR_LDUR 1
330 * LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
331 * for reading from NPE internal logical registers
333 #define IX_NPEDL_RD_INSTR_LDUR 0
337 * NPE internal Context Store registers.
341 IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
342 IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
343 IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
344 IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
345 IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
350 * NPE Context Store register logical addresses
352 #define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
353 #define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
354 #define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
355 #define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
358 * NPE Context Store register reset values
362 * Reset value of STEVT NPE internal Context Store register
363 * (STEVT = off, 0x80)
365 #define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
368 * Reset value of STARTPC NPE internal Context Store register
371 #define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
374 * Reset value of REGMAP NPE internal Context Store register
375 * (REGMAP = d0->p0, d8->p2, d16->p4)
377 #define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
380 * Reset value of CINDEX NPE internal Context Store register
383 #define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
387 * Numeric range of context levels available on an NPE
389 #define IX_NPEDL_CTXT_NUM_MIN 0
390 #define IX_NPEDL_CTXT_NUM_MAX 15
394 * Number of Physical registers currently supported
395 * Initial NPE implementations will have a 32-word register file.
396 * Later implementations may have a 64-word register file.
398 #define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
401 * LSB-offset of Regmap number in Physical NPE register address, used
402 * for Physical To Logical register address mapping in the NPE
404 #define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
407 * Mask to extract a logical NPE register address from a physical
408 * register address, used for Physical To Logical address mapping
410 #define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
413 * NPE Message/Mailbox interface.
415 #define IX_NPESTAT IX_NPEDL_REG_OFFSET_STAT /* status register */
416 #define IX_NPECTL IX_NPEDL_REG_OFFSET_CTL /* control register */
417 #define IX_NPEFIFO IX_NPEDL_REG_OFFSET_FIFO /* FIFO register */
419 /* control register */
420 #define IX_NPECTL_OFE 0x00010000 /* output fifo enable */
421 #define IX_NPECTL_IFE 0x00020000 /* input fifo enable */
422 #define IX_NPECTL_OFWE 0x01000000 /* output fifo write enable */
423 #define IX_NPECTL_IFWE 0x02000000 /* input fifo write enable */
425 /* status register */
426 #define IX_NPESTAT_OFNE 0x00010000 /* output fifo not empty */
427 #define IX_NPESTAT_IFNF 0x00020000 /* input fifo not full */
428 #define IX_NPESTAT_OFNF 0x00040000 /* output fifo not full */
429 #define IX_NPESTAT_IFNE 0x00080000 /* input fifo not empty */
430 #define IX_NPESTAT_MBINT 0x00100000 /* Mailbox interrupt */
431 #define IX_NPESTAT_IFINT 0x00200000 /* input fifo interrupt */
432 #define IX_NPESTAT_OFINT 0x00400000 /* output fifo interrupt */
433 #define IX_NPESTAT_WFINT 0x00800000 /* watch fifo interrupt */
434 #endif /* _IXP425_NPEREG_H_ */