1 /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Ichiro FUKUHARA <ichiro@ichiro.org>.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Ichiro FUKUHARA.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/malloc.h>
44 #define _ARM32_BUS_DMA_PRIVATE
46 #include <sys/kernel.h>
47 #include <sys/module.h>
50 #include <dev/pci/pcivar.h>
52 #include <machine/armreg.h>
53 #include <machine/bus.h>
54 #include <machine/cpu.h>
55 #include <machine/pcb.h>
59 #include <vm/vm_extern.h>
61 #include <arm/xscale/ixp425/ixp425reg.h>
62 #include <arm/xscale/ixp425/ixp425var.h>
64 #include <dev/pci/pcib_private.h>
67 #include <dev/pci/pcireg.h>
68 extern struct ixp425_softc *ixp425_softc;
70 #define PCI_CSR_WRITE_4(sc, reg, data) \
71 bus_write_4(sc->sc_csr, reg, data)
73 #define PCI_CSR_READ_4(sc, reg) \
74 bus_read_4(sc->sc_csr, reg)
76 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
77 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
79 static device_probe_t ixppcib_probe;
80 static device_attach_t ixppcib_attach;
81 static bus_read_ivar_t ixppcib_read_ivar;
82 static bus_write_ivar_t ixppcib_write_ivar;
83 static bus_setup_intr_t ixppcib_setup_intr;
84 static bus_teardown_intr_t ixppcib_teardown_intr;
85 static bus_alloc_resource_t ixppcib_alloc_resource;
86 static bus_activate_resource_t ixppcib_activate_resource;
87 static bus_deactivate_resource_t ixppcib_deactivate_resource;
88 static bus_release_resource_t ixppcib_release_resource;
89 static pcib_maxslots_t ixppcib_maxslots;
90 static pcib_read_config_t ixppcib_read_config;
91 static pcib_write_config_t ixppcib_write_config;
92 static pcib_route_interrupt_t ixppcib_route_interrupt;
95 ixppcib_probe(device_t dev)
97 device_set_desc(dev, "IXP4XX PCI Bus");
102 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
105 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
106 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data);
110 ixppcib_attach(device_t dev)
113 struct ixppcib_softc *sc;
115 sc = device_get_softc(dev);
118 sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
119 IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
120 IXP425_PCI_SIZE, RF_ACTIVE);
121 if (sc->sc_csr == NULL)
122 panic("cannot allocate PCI CSR registers");
124 ixp425_md_attach(dev);
125 /* always setup the base, incase another OS messes w/ it */
126 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
129 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
130 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
131 IXP425_PCI_MEM_SIZE, RF_ACTIVE);
132 if (sc->sc_mem == NULL)
133 panic("cannot allocate PCI MEM space");
135 /* NB: PCI dma window is 64M so anything above must be bounced */
136 if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024,
137 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
138 NULL, NULL, &sc->sc_dmat))
139 panic("couldn't create the PCI dma tag !");
141 * Initialize the bus space tags.
143 ixp425_io_bs_init(&sc->sc_pci_iot, sc);
144 ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
148 /* Initialize memory and i/o rmans. */
149 sc->sc_io_rman.rm_type = RMAN_ARRAY;
150 sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports";
151 if (rman_init(&sc->sc_io_rman) != 0 ||
152 rman_manage_region(&sc->sc_io_rman, 0,
153 IXP425_PCI_IO_SIZE) != 0) {
154 panic("ixppcib_probe: failed to set up I/O rman");
157 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
158 sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory";
159 if (rman_init(&sc->sc_mem_rman) != 0 ||
160 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
161 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
162 panic("ixppcib_probe: failed to set up memory rman");
166 * PCI->AHB address translation
167 * begin at the physical memory start + OFFSET
169 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
170 (IXP425_AHB_OFFSET & 0xFF000000) +
171 ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) +
172 ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) +
173 ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) +
176 #define IXPPCIB_WRITE_CONF(sc, reg, val) \
177 ixp425_pci_conf_reg_write(sc, reg, val)
178 /* Write Mapping registers PCI Configuration Registers */
179 /* Base Address 0 - 3 */
180 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000);
181 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000);
182 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000);
183 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000);
186 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
189 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
191 /* Assert some PCI errors */
192 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
196 * Set up byte lane swapping between little-endian PCI
197 * and the big-endian AHB bus
199 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
201 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
205 * Enable bus mastering and I/O,memory access
207 IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
208 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
211 * Wait some more to ensure PCI devices have stabilised.
215 device_add_child(dev, "pci", -1);
216 return (bus_generic_attach(dev));
220 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
222 struct ixppcib_softc *sc;
224 sc = device_get_softc(dev);
226 case PCIB_IVAR_DOMAIN:
230 *result = sc->sc_bus;
238 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
240 struct ixppcib_softc *sc;
242 sc = device_get_softc(dev);
244 case PCIB_IVAR_DOMAIN:
255 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
256 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
260 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
261 filt, intr, arg, cookiep));
265 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
269 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
272 static struct resource *
273 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
274 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
276 struct ixppcib_softc *sc = device_get_softc(bus);
283 rmanp = &sc->sc_irq_rman;
287 rmanp = &sc->sc_io_rman;
291 rmanp = &sc->sc_mem_rman;
298 rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE,
302 rman_set_rid(rv, *rid);
303 if (flags & RF_ACTIVE) {
304 if (bus_activate_resource(child, type, *rid, rv)) {
305 rman_release_resource(rv);
314 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
317 struct ixppcib_softc *sc = device_get_softc(bus);
320 error = rman_activate_resource(r);
325 rman_set_bustag(r, &sc->sc_pci_iot);
326 rman_set_bushandle(r, rman_get_start(r));
329 rman_set_bustag(r, &sc->sc_pci_memt);
330 rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) +
331 (rman_get_start(r) - IXP425_PCI_MEM_HWBASE));
339 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
343 device_printf(bus, "%s called deactivate_resource (unexpected)\n",
344 device_get_nameunit(child));
349 ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
353 device_printf(bus, "%s called release_resource (unexpected)\n",
354 device_get_nameunit(child));
359 ixppcib_get_dma_tag(device_t bus, device_t child)
361 struct ixppcib_softc *sc = device_get_softc(bus);
363 return (sc->sc_dmat);
367 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
371 /* configuration type 0 */
372 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
373 (1U << (32 - (slot & 0x1f))) |
374 ((func & 0x7) << 8) | (reg & ~3));
376 /* configuration type 1 */
377 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
378 (bus << 16) | (slot << 11) |
379 (func << 8) | (reg & ~3) | 1);
385 ixppcib_maxslots(device_t dev)
388 return (PCI_SLOTMAX);
392 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
395 struct ixppcib_softc *sc = device_get_softc(dev);
398 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
400 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
401 ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
402 ret >>= (reg & 3) * 8;
403 ret &= 0xffffffff >> ((4 - bytes) * 8);
405 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
406 __func__, bus, slot, func, reg, bytes, ret);
408 /* check & clear PCI abort */
409 data = PCI_CSR_READ_4(sc, PCI_ISR);
410 if (data & ISR_PFE) {
411 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
417 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
420 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
421 u_int32_t val, int bytes)
423 struct ixppcib_softc *sc = device_get_softc(dev);
427 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
428 __func__, bus, slot, func, reg, bytes, val);
430 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
432 /* Byte enables are active low, so not them first */
433 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
434 (~(byteenables[bytes] << (reg & 3)) & 0xf0));
435 PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
437 /* check & clear PCI abort */
438 data = PCI_CSR_READ_4(sc, PCI_ISR);
440 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
444 ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
447 return (ixp425_md_route_interrupt(bridge, device, pin));
450 static device_method_t ixppcib_methods[] = {
451 /* Device interface */
452 DEVMETHOD(device_probe, ixppcib_probe),
453 DEVMETHOD(device_attach, ixppcib_attach),
456 DEVMETHOD(bus_read_ivar, ixppcib_read_ivar),
457 DEVMETHOD(bus_write_ivar, ixppcib_write_ivar),
458 DEVMETHOD(bus_setup_intr, ixppcib_setup_intr),
459 DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr),
460 DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource),
461 DEVMETHOD(bus_activate_resource, ixppcib_activate_resource),
462 DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource),
463 DEVMETHOD(bus_release_resource, ixppcib_release_resource),
464 DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag),
467 DEVMETHOD(pcib_maxslots, ixppcib_maxslots),
468 DEVMETHOD(pcib_read_config, ixppcib_read_config),
469 DEVMETHOD(pcib_write_config, ixppcib_write_config),
470 DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt),
471 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
476 static driver_t ixppcib_driver = {
479 sizeof(struct ixppcib_softc),
481 static devclass_t ixppcib_devclass;
483 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);