1 /* $NetBSD: ixp425_pci_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */
5 * Ichiro FUKUHARA <ichiro@ichiro.org>.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Ichiro FUKUHARA.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * bus_space PCI functions for ixp425
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/endian.h>
48 #include <machine/pcb.h>
51 #include <vm/vm_kern.h>
53 #include <vm/vm_page.h>
54 #include <vm/vm_extern.h>
56 #include <machine/bus.h>
58 #include <arm/xscale/ixp425/ixp425reg.h>
59 #include <arm/xscale/ixp425/ixp425var.h>
62 * Macros to read/write registers
64 #define CSR_READ_4(x) *(volatile uint32_t *) \
65 (IXP425_PCI_CSR_BASE + (x))
66 #define CSR_WRITE_4(x, v) *(volatile uint32_t *) \
67 (IXP425_PCI_CSR_BASE + (x)) = (v)
69 /* Proto types for all the bus_space structure functions */
70 bs_protos(ixp425_pci);
71 bs_protos(ixp425_pci_io);
72 bs_protos(ixp425_pci_mem);
74 /* special I/O functions */
75 static u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t);
76 static u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t);
77 static u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t);
79 static void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
80 static void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t);
81 static void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t);
84 static u_int8_t _pci_io_bs_r_1_s(void *, bus_space_handle_t, bus_size_t);
85 static u_int16_t _pci_io_bs_r_2_s(void *, bus_space_handle_t, bus_size_t);
86 static u_int32_t _pci_io_bs_r_4_s(void *, bus_space_handle_t, bus_size_t);
88 static void _pci_io_bs_w_1_s(void *, bus_space_handle_t, bus_size_t, u_int8_t);
89 static void _pci_io_bs_w_2_s(void *, bus_space_handle_t, bus_size_t, u_int16_t);
90 static void _pci_io_bs_w_4_s(void *, bus_space_handle_t, bus_size_t, u_int32_t);
92 static u_int8_t _pci_mem_bs_r_1(void *, bus_space_handle_t, bus_size_t);
93 static u_int16_t _pci_mem_bs_r_2(void *, bus_space_handle_t, bus_size_t);
94 static u_int32_t _pci_mem_bs_r_4(void *, bus_space_handle_t, bus_size_t);
96 static void _pci_mem_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
97 static void _pci_mem_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t);
98 static void _pci_mem_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t);
101 struct bus_space ixp425_pci_io_bs_tag_template = {
102 /* mapping/unmapping */
103 .bs_map = ixp425_pci_io_bs_map,
104 .bs_unmap = ixp425_pci_io_bs_unmap,
105 .bs_subregion = ixp425_pci_bs_subregion,
107 .bs_alloc = ixp425_pci_io_bs_alloc,
108 .bs_free = ixp425_pci_io_bs_free,
111 .bs_barrier = ixp425_pci_bs_barrier,
114 * IXP425 processor does not have PCI I/O windows
117 .bs_r_1 = _pci_io_bs_r_1,
118 .bs_r_2 = _pci_io_bs_r_2,
119 .bs_r_4 = _pci_io_bs_r_4,
122 .bs_w_1 = _pci_io_bs_w_1,
123 .bs_w_2 = _pci_io_bs_w_2,
124 .bs_w_4 = _pci_io_bs_w_4,
127 .bs_r_1_s = _pci_io_bs_r_1_s,
128 .bs_r_2_s = _pci_io_bs_r_2_s,
129 .bs_r_4_s = _pci_io_bs_r_4_s,
131 .bs_w_1_s = _pci_io_bs_w_1_s,
132 .bs_w_2_s = _pci_io_bs_w_2_s,
133 .bs_w_4_s = _pci_io_bs_w_4_s,
135 .bs_r_1_s = _pci_io_bs_r_1,
136 .bs_r_2_s = _pci_io_bs_r_2,
137 .bs_r_4_s = _pci_io_bs_r_4,
139 .bs_w_1_s = _pci_io_bs_w_1,
140 .bs_w_2_s = _pci_io_bs_w_2,
141 .bs_w_4_s = _pci_io_bs_w_4,
146 ixp425_io_bs_init(bus_space_tag_t bs, void *cookie)
148 *bs = ixp425_pci_io_bs_tag_template;
149 bs->bs_cookie = cookie;
152 struct bus_space ixp425_pci_mem_bs_tag_template = {
153 /* mapping/unmapping */
154 .bs_map = ixp425_pci_mem_bs_map,
155 .bs_unmap = ixp425_pci_mem_bs_unmap,
156 .bs_subregion = ixp425_pci_bs_subregion,
158 .bs_alloc = ixp425_pci_mem_bs_alloc,
159 .bs_free = ixp425_pci_mem_bs_free,
162 .bs_barrier = ixp425_pci_bs_barrier,
166 .bs_r_1_s = _pci_mem_bs_r_1,
167 .bs_r_2_s = _pci_mem_bs_r_2,
168 .bs_r_4_s = _pci_mem_bs_r_4,
170 .bs_r_1 = ixp425_pci_mem_bs_r_1,
171 .bs_r_2 = ixp425_pci_mem_bs_r_2,
172 .bs_r_4 = ixp425_pci_mem_bs_r_4,
175 .bs_w_1_s = _pci_mem_bs_w_1,
176 .bs_w_2_s = _pci_mem_bs_w_2,
177 .bs_w_4_s = _pci_mem_bs_w_4,
179 .bs_w_1 = ixp425_pci_mem_bs_w_1,
180 .bs_w_2 = ixp425_pci_mem_bs_w_2,
181 .bs_w_4 = ixp425_pci_mem_bs_w_4,
184 .bs_r_1 = ixp425_pci_mem_bs_r_1,
185 .bs_r_2 = ixp425_pci_mem_bs_r_2,
186 .bs_r_4 = ixp425_pci_mem_bs_r_4,
187 .bs_r_1_s = ixp425_pci_mem_bs_r_1,
188 .bs_r_2_s = ixp425_pci_mem_bs_r_2,
189 .bs_r_4_s = ixp425_pci_mem_bs_r_4,
192 .bs_w_1 = ixp425_pci_mem_bs_w_1,
193 .bs_w_2 = ixp425_pci_mem_bs_w_2,
194 .bs_w_4 = ixp425_pci_mem_bs_w_4,
195 .bs_w_1_s = ixp425_pci_mem_bs_w_1,
196 .bs_w_2_s = ixp425_pci_mem_bs_w_2,
197 .bs_w_4_s = ixp425_pci_mem_bs_w_4,
202 ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie)
204 *bs = ixp425_pci_mem_bs_tag_template;
205 bs->bs_cookie = cookie;
210 ixp425_pci_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
211 bus_size_t size, bus_space_handle_t *nbshp)
213 *nbshp = bsh + offset;
218 ixp425_pci_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
219 bus_size_t len, int flags)
226 ixp425_pci_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
227 int cacheable, bus_space_handle_t *bshp)
234 ixp425_pci_io_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size)
240 ixp425_pci_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
241 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
242 bus_addr_t *bpap, bus_space_handle_t *bshp)
244 panic("ixp425_pci_io_bs_alloc(): not implemented\n");
248 ixp425_pci_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
250 panic("ixp425_pci_io_bs_free(): not implemented\n");
253 /* special I/O functions */
254 static __inline u_int32_t
255 _bs_r(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be)
259 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
260 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
261 data = CSR_READ_4(PCI_NP_RDATA);
262 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
263 CSR_WRITE_4(PCI_ISR, ISR_PFE);
269 _pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off)
271 u_int32_t data, n, be;
274 be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
275 data = _bs_r(v, ioh, off, be);
277 return data >> (8 * n);
281 _pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off)
283 u_int32_t data, n, be;
286 be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
287 data = _bs_r(v, ioh, off, be);
289 return data >> (8 * n);
293 _pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off)
297 data = _bs_r(v, ioh, off, 0);
303 _pci_io_bs_r_1_s(void *v, bus_space_handle_t ioh, bus_size_t off)
305 u_int32_t data, n, be;
308 be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
309 data = _bs_r(v, ioh, off, be);
311 return data >> (8 * n);
315 _pci_io_bs_r_2_s(void *v, bus_space_handle_t ioh, bus_size_t off)
317 u_int32_t data, n, be;
320 be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
321 data = _bs_r(v, ioh, off, be);
323 return data >> (8 * n);
327 _pci_io_bs_r_4_s(void *v, bus_space_handle_t ioh, bus_size_t off)
331 data = _bs_r(v, ioh, off, 0);
332 return le32toh(data);
334 #endif /* __ARMEB__ */
337 _bs_w(void *v, bus_space_handle_t ioh, bus_size_t off,
338 u_int32_t be, u_int32_t data)
340 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
341 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
342 CSR_WRITE_4(PCI_NP_WDATA, data);
343 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
344 CSR_WRITE_4(PCI_ISR, ISR_PFE);
348 _pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off,
351 u_int32_t data, n, be;
354 be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
355 data = val << (8 * n);
356 _bs_w(v, ioh, off, be, data);
360 _pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off,
363 u_int32_t data, n, be;
366 be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
367 data = val << (8 * n);
368 _bs_w(v, ioh, off, be, data);
372 _pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off,
375 _bs_w(v, ioh, off, 0, val);
380 _pci_io_bs_w_1_s(void *v, bus_space_handle_t ioh, bus_size_t off,
383 u_int32_t data, n, be;
386 be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
387 data = val << (8 * n);
388 _bs_w(v, ioh, off, be, data);
392 _pci_io_bs_w_2_s(void *v, bus_space_handle_t ioh, bus_size_t off,
395 u_int32_t data, n, be;
398 be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
399 data = val << (8 * n);
400 _bs_w(v, ioh, off, be, data);
404 _pci_io_bs_w_4_s(void *v, bus_space_handle_t ioh, bus_size_t off,
407 _bs_w(v, ioh, off, 0, htole32(val));
409 #endif /* __ARMEB__ */
413 ixp425_pci_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
414 int cacheable, bus_space_handle_t *bshp)
416 vm_paddr_t pa, endpa;
418 pa = trunc_page(bpa);
419 endpa = round_page(bpa + size);
421 *bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa);
427 ixp425_pci_mem_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size)
429 vm_offset_t va, endva;
431 va = trunc_page((vm_offset_t)t);
432 endva = va + round_page(size);
434 /* Free the kernel virtual mapping. */
435 kmem_free(kernel_map, va, endva - va);
439 ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
440 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
441 bus_addr_t *bpap, bus_space_handle_t *bshp)
443 panic("ixp425_mem_bs_alloc(): not implemented\n");
447 ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
449 panic("ixp425_mem_bs_free(): not implemented\n");
454 _pci_mem_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off)
456 return ixp425_pci_mem_bs_r_1(v, ioh, off);
460 _pci_mem_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off)
462 return (ixp425_pci_mem_bs_r_2(v, ioh, off));
466 _pci_mem_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off)
470 data = ixp425_pci_mem_bs_r_4(v, ioh, off);
471 return (le32toh(data));
475 _pci_mem_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off,
478 ixp425_pci_mem_bs_w_1(v, ioh, off, val);
482 _pci_mem_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off,
485 ixp425_pci_mem_bs_w_2(v, ioh, off, val);
489 _pci_mem_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off,
492 ixp425_pci_mem_bs_w_4(v, ioh, off, htole32(val));
494 #endif /* __ARMEB__ */
496 /* End of ixp425_pci_space.c */