1 /* $NetBSD: ixp425var.h,v 1.12 2009/10/21 14:15:51 rmind Exp $ */
4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
7 * Ichiro FUKUHARA <ichiro@ichiro.org>.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include <sys/queue.h>
41 #include <machine/bus.h>
45 /* NB: cputype is setup by set_cpufuncs */
46 #define cpu_is_ixp42x() (cputype == CPU_ID_IXP425)
47 #define cpu_is_ixp43x() (cputype == CPU_ID_IXP435)
48 #define cpu_is_ixp46x() (cputype == CPU_ID_IXP465)
52 bus_space_tag_t sc_iot;
53 bus_space_handle_t sc_gpio_ioh;
54 bus_space_handle_t sc_exp_ioh;
56 u_int32_t sc_intrmask;
58 struct rman sc_irq_rman;
59 struct rman sc_mem_rman;
60 bus_dma_tag_t sc_dmat;
63 void ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type);
65 struct ixppcib_softc {
70 struct resource *sc_csr;
71 struct resource *sc_mem;
73 struct rman sc_io_rman;
74 struct rman sc_mem_rman;
75 struct rman sc_irq_rman;
77 struct bus_space sc_pci_memt;
78 struct bus_space sc_pci_iot;
79 bus_dma_tag_t sc_dmat;
82 #define EXP_BUS_WRITE_4(sc, reg, data) \
83 bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data)
84 #define EXP_BUS_READ_4(sc, reg) \
85 bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg)
87 #define GPIO_CONF_WRITE_4(sc, reg, data) \
88 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, reg, data)
89 #define GPIO_CONF_READ_4(sc, reg) \
90 bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)
91 #define IXP4XX_GPIO_LOCK() mtx_lock(&ixp425_gpio_mtx)
92 #define IXP4XX_GPIO_UNLOCK() mtx_unlock(&ixp425_gpio_mtx)
93 extern struct mtx ixp425_gpio_mtx;
95 extern struct bus_space ixp425_bs_tag;
96 extern struct bus_space ixp425_a4x_bs_tag;
98 extern struct bus_space cambria_exp_bs_tag;
99 void cambria_exp_bus_init(struct ixp425_softc *);
101 void ixp425_io_bs_init(bus_space_tag_t, void *);
102 void ixp425_mem_bs_init(bus_space_tag_t, void *);
104 uint32_t ixp425_sdram_size(void);
105 uint32_t ixp435_ddram_size(void);
106 uint32_t ixp4xx_read_feature_bits(void);
107 void ixp4xx_write_feature_bits(uint32_t);
109 int ixp425_md_route_interrupt(device_t, device_t, int);
110 void ixp425_md_attach(device_t);
112 int getvbase(uint32_t, uint32_t, uint32_t *);
118 #define IXP425_IVAR(d) ((struct ixp425_ivar *) device_get_ivars(d))
121 IXP425_IVAR_ADDR, /* base physical address */
122 IXP425_IVAR_IRQ /* irq/gpio pin assignment */
124 #endif /* _IXP425VAR_H_ */