2 * Copyright (c) 1997, 1998 Justin T. Gibbs.
3 * Copyright (c) 2015-2016 The FreeBSD Foundation
6 * Portions of this software were developed by Andrew Turner
7 * under sponsorship of the FreeBSD Foundation.
9 * Portions of this software were developed by Semihalf
10 * under sponsorship of the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification, immediately at the beginning of the file.
18 * 2. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
41 #include <sys/interrupt.h>
42 #include <sys/kernel.h>
46 #include <sys/memdesc.h>
47 #include <sys/mutex.h>
48 #include <sys/sysctl.h>
52 #include <vm/vm_extern.h>
53 #include <vm/vm_kern.h>
54 #include <vm/vm_page.h>
55 #include <vm/vm_map.h>
57 #include <machine/atomic.h>
58 #include <machine/bus.h>
59 #include <machine/md_var.h>
60 #include <arm64/include/bus_dma_impl.h>
62 #define MAX_BPAGES 4096
65 BF_COULD_BOUNCE = 0x01,
66 BF_MIN_ALLOC_COMP = 0x02,
74 struct bus_dma_tag_common common;
76 size_t alloc_alignment;
79 bus_dma_segment_t *segments;
80 struct bounce_zone *bounce_zone;
84 vm_offset_t vaddr; /* kva of bounce buffer */
85 bus_addr_t busaddr; /* Physical address */
86 vm_offset_t datavaddr; /* kva of client data */
87 vm_page_t datapage; /* physical page of client data */
88 vm_offset_t dataoffs; /* page offset of client data */
89 bus_size_t datacount; /* client data count */
90 STAILQ_ENTRY(bounce_page) links;
94 STAILQ_ENTRY(bounce_zone) links;
95 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list;
103 bus_size_t alignment;
107 struct sysctl_ctx_list sysctl_tree;
108 struct sysctl_oid *sysctl_tree_top;
111 static struct mtx bounce_lock;
112 static int total_bpages;
113 static int busdma_zonecount;
114 static STAILQ_HEAD(, bounce_zone) bounce_zone_list;
115 static void *busdma_ih;
117 static SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
118 "Busdma parameters");
119 SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0,
120 "Total bounce pages");
123 vm_offset_t vaddr; /* kva of client data */
124 bus_addr_t paddr; /* physical address */
125 vm_page_t pages; /* starting page of client data */
126 bus_size_t datacount; /* client data count */
130 struct bp_list bpages;
135 bus_dmamap_callback_t *callback;
137 STAILQ_ENTRY(bus_dmamap) links;
139 #define DMAMAP_COHERENT (1 << 0)
140 #define DMAMAP_FROM_DMAMEM (1 << 1)
141 #define DMAMAP_MBUF (1 << 2)
143 struct sync_list slist[];
146 static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist;
147 static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist;
149 static void init_bounce_pages(void *dummy);
150 static int alloc_bounce_zone(bus_dma_tag_t dmat);
151 static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages);
152 static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
154 static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map,
155 vm_offset_t vaddr, bus_addr_t addr, bus_size_t size);
156 static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage);
157 int run_filter(bus_dma_tag_t dmat, bus_addr_t paddr);
158 static bool _bus_dmamap_pagesneeded(bus_dma_tag_t dmat, bus_dmamap_t map,
159 vm_paddr_t buf, bus_size_t buflen, int *pagesneeded);
160 static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
161 pmap_t pmap, void *buf, bus_size_t buflen, int flags);
162 static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map,
163 vm_paddr_t buf, bus_size_t buflen, int flags);
164 static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
168 * Return true if the DMA should bounce because the start or end does not fall
169 * on a cacheline boundary (which would require a partial cacheline flush).
170 * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by
171 * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a
172 * strict rule that such memory cannot be accessed by the CPU while DMA is in
173 * progress (or by multiple DMA engines at once), so that it's always safe to do
174 * full cacheline flushes even if that affects memory outside the range of a
175 * given DMA operation that doesn't involve the full allocated buffer. If we're
176 * mapping an mbuf, that follows the same rules as a buffer we allocated.
179 cacheline_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
183 #define DMAMAP_CACHELINE_FLAGS \
184 (DMAMAP_FROM_DMAMEM | DMAMAP_COHERENT | DMAMAP_MBUF)
185 if ((dmat->bounce_flags & BF_COHERENT) != 0)
187 if (map != NULL && (map->flags & DMAMAP_CACHELINE_FLAGS) != 0)
189 return (((paddr | size) & (dcache_line_size - 1)) != 0);
190 #undef DMAMAP_CACHELINE_FLAGS
194 * Return true if the given address does not fall on the alignment boundary.
197 alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr)
200 return ((addr & (dmat->common.alignment - 1)) != 0);
204 might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
208 /* Memory allocated by bounce_bus_dmamem_alloc won't bounce */
209 if (map && (map->flags & DMAMAP_FROM_DMAMEM) != 0)
212 if ((dmat->bounce_flags & BF_COULD_BOUNCE) != 0)
215 if (cacheline_bounce(dmat, map, paddr, size))
218 if (alignment_bounce(dmat, paddr))
225 must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
229 if (cacheline_bounce(dmat, map, paddr, size))
232 if (alignment_bounce(dmat, paddr))
235 if ((dmat->bounce_flags & BF_COULD_BOUNCE) != 0 &&
236 bus_dma_run_filter(&dmat->common, paddr))
243 * Allocate a device specific dma_tag.
246 bounce_bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
247 bus_addr_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr,
248 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize,
249 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
250 void *lockfuncarg, bus_dma_tag_t *dmat)
252 bus_dma_tag_t newtag;
256 error = common_bus_dma_tag_create(parent != NULL ? &parent->common :
257 NULL, alignment, boundary, lowaddr, highaddr, filter, filterarg,
258 maxsize, nsegments, maxsegsz, flags, lockfunc, lockfuncarg,
259 sizeof (struct bus_dma_tag), (void **)&newtag);
263 newtag->common.impl = &bus_dma_bounce_impl;
264 newtag->map_count = 0;
265 newtag->segments = NULL;
267 if ((flags & BUS_DMA_COHERENT) != 0) {
268 newtag->bounce_flags |= BF_COHERENT;
271 if (parent != NULL) {
272 if ((newtag->common.filter != NULL ||
273 (parent->bounce_flags & BF_COULD_BOUNCE) != 0))
274 newtag->bounce_flags |= BF_COULD_BOUNCE;
276 /* Copy some flags from the parent */
277 newtag->bounce_flags |= parent->bounce_flags & BF_COHERENT;
280 if ((newtag->bounce_flags & BF_COHERENT) != 0) {
281 newtag->alloc_alignment = newtag->common.alignment;
282 newtag->alloc_size = newtag->common.maxsize;
285 * Ensure the buffer is aligned to a cacheline when allocating
286 * a non-coherent buffer. This is so we don't have any data
287 * that another CPU may be accessing around DMA buffer
288 * causing the cache to become dirty.
290 newtag->alloc_alignment = MAX(newtag->common.alignment,
292 newtag->alloc_size = roundup2(newtag->common.maxsize,
296 if (newtag->common.lowaddr < ptoa((vm_paddr_t)Maxmem) ||
297 newtag->common.alignment > 1)
298 newtag->bounce_flags |= BF_COULD_BOUNCE;
300 if ((flags & BUS_DMA_ALLOCNOW) != 0) {
301 struct bounce_zone *bz;
303 * Round size up to a full page, and add one more page because
304 * there can always be one more boundary crossing than the
305 * number of pages in a transfer.
307 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE;
310 if ((error = alloc_bounce_zone(newtag)) != 0) {
311 free(newtag, M_DEVBUF);
314 bz = newtag->bounce_zone;
316 if (ptoa(bz->total_bpages) < maxsize) {
319 pages = atop(maxsize) + 1 - bz->total_bpages;
321 /* Add pages to our bounce pool */
322 if (alloc_bounce_pages(newtag, pages) < pages)
325 /* Performed initial allocation */
326 newtag->bounce_flags |= BF_MIN_ALLOC_COMP;
331 free(newtag, M_DEVBUF);
334 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
335 __func__, newtag, (newtag != NULL ? newtag->common.flags : 0),
341 bounce_bus_dma_tag_destroy(bus_dma_tag_t dmat)
343 bus_dma_tag_t dmat_copy, parent;
350 if (dmat->map_count != 0) {
354 while (dmat != NULL) {
355 parent = (bus_dma_tag_t)dmat->common.parent;
356 atomic_subtract_int(&dmat->common.ref_count, 1);
357 if (dmat->common.ref_count == 0) {
358 if (dmat->segments != NULL)
359 free(dmat->segments, M_DEVBUF);
360 free(dmat, M_DEVBUF);
362 * Last reference count, so
363 * release our reference
364 * count on our parent.
372 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error);
377 bounce_bus_dma_id_mapped(bus_dma_tag_t dmat, vm_paddr_t buf, bus_size_t buflen)
380 if (!might_bounce(dmat, NULL, buf, buflen))
382 return (!_bus_dmamap_pagesneeded(dmat, NULL, buf, buflen, NULL));
386 alloc_dmamap(bus_dma_tag_t dmat, int flags)
391 mapsize = sizeof(*map);
392 mapsize += sizeof(struct sync_list) * dmat->common.nsegments;
393 map = malloc(mapsize, M_DEVBUF, flags | M_ZERO);
397 /* Initialize the new map */
398 STAILQ_INIT(&map->bpages);
404 * Allocate a handle for mapping from kva/uva/physical
405 * address space into bus device space.
408 bounce_bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
410 struct bounce_zone *bz;
411 int error, maxpages, pages;
415 if (dmat->segments == NULL) {
416 dmat->segments = (bus_dma_segment_t *)malloc(
417 sizeof(bus_dma_segment_t) * dmat->common.nsegments,
419 if (dmat->segments == NULL) {
420 CTR3(KTR_BUSDMA, "%s: tag %p error %d",
421 __func__, dmat, ENOMEM);
426 *mapp = alloc_dmamap(dmat, M_NOWAIT);
428 CTR3(KTR_BUSDMA, "%s: tag %p error %d",
429 __func__, dmat, ENOMEM);
434 * Bouncing might be required if the driver asks for an active
435 * exclusion region, a data alignment that is stricter than 1, and/or
436 * an active address boundary.
438 if (dmat->bounce_zone == NULL) {
439 if ((error = alloc_bounce_zone(dmat)) != 0) {
440 free(*mapp, M_DEVBUF);
444 bz = dmat->bounce_zone;
447 * Attempt to add pages to our pool on a per-instance basis up to a sane
448 * limit. Even if the tag isn't subject of bouncing due to alignment
449 * and boundary constraints, it could still auto-bounce due to
450 * cacheline alignment, which requires at most two bounce pages.
452 if (dmat->common.alignment > 1)
453 maxpages = MAX_BPAGES;
455 maxpages = MIN(MAX_BPAGES, Maxmem -
456 atop(dmat->common.lowaddr));
457 if ((dmat->bounce_flags & BF_MIN_ALLOC_COMP) == 0 ||
458 (bz->map_count > 0 && bz->total_bpages < maxpages)) {
459 pages = atop(roundup2(dmat->common.maxsize, PAGE_SIZE)) + 1;
460 pages = MIN(maxpages - bz->total_bpages, pages);
461 pages = MAX(pages, 2);
462 if (alloc_bounce_pages(dmat, pages) < pages)
464 if ((dmat->bounce_flags & BF_MIN_ALLOC_COMP) == 0) {
466 dmat->bounce_flags |= BF_MIN_ALLOC_COMP;
475 if ((dmat->bounce_flags & BF_COHERENT) != 0)
476 (*mapp)->flags |= DMAMAP_COHERENT;
478 free(*mapp, M_DEVBUF);
480 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
481 __func__, dmat, dmat->common.flags, error);
486 * Destroy a handle for mapping from kva/uva/physical
487 * address space into bus device space.
490 bounce_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map)
493 /* Check we are destroying the correct map type */
494 if ((map->flags & DMAMAP_FROM_DMAMEM) != 0)
495 panic("bounce_bus_dmamap_destroy: Invalid map freed\n");
497 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) {
498 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, EBUSY);
501 if (dmat->bounce_zone)
502 dmat->bounce_zone->map_count--;
505 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat);
510 * Allocate a piece of memory that can be efficiently mapped into
511 * bus device space based on the constraints lited in the dma tag.
512 * A dmamap to for use with dmamap_load is also allocated.
515 bounce_bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
521 if (flags & BUS_DMA_NOWAIT)
526 if (dmat->segments == NULL) {
527 dmat->segments = (bus_dma_segment_t *)malloc(
528 sizeof(bus_dma_segment_t) * dmat->common.nsegments,
530 if (dmat->segments == NULL) {
531 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
532 __func__, dmat, dmat->common.flags, ENOMEM);
536 if (flags & BUS_DMA_ZERO)
538 if (flags & BUS_DMA_NOCACHE)
539 attr = VM_MEMATTR_UNCACHEABLE;
540 else if ((flags & BUS_DMA_COHERENT) != 0 &&
541 (dmat->bounce_flags & BF_COHERENT) == 0)
543 * If we have a non-coherent tag, and are trying to allocate
544 * a coherent block of memory it needs to be uncached.
546 attr = VM_MEMATTR_UNCACHEABLE;
548 attr = VM_MEMATTR_DEFAULT;
551 * Create the map, but don't set the could bounce flag as
552 * this allocation should never bounce;
554 *mapp = alloc_dmamap(dmat, mflags);
556 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
557 __func__, dmat, dmat->common.flags, ENOMEM);
562 * Mark the map as coherent if we used uncacheable memory or the
563 * tag was already marked as coherent.
565 if (attr == VM_MEMATTR_UNCACHEABLE ||
566 (dmat->bounce_flags & BF_COHERENT) != 0)
567 (*mapp)->flags |= DMAMAP_COHERENT;
569 (*mapp)->flags |= DMAMAP_FROM_DMAMEM;
572 * Allocate the buffer from the malloc(9) allocator if...
573 * - It's small enough to fit into a single power of two sized bucket.
574 * - The alignment is less than or equal to the maximum size
575 * - The low address requirement is fulfilled.
576 * else allocate non-contiguous pages if...
577 * - The page count that could get allocated doesn't exceed
578 * nsegments also when the maximum segment size is less
580 * - The alignment constraint isn't larger than a page boundary.
581 * - There are no boundary-crossing constraints.
582 * else allocate a block of contiguous pages because one or more of the
583 * constraints is something that only the contig allocator can fulfill.
585 * NOTE: The (dmat->common.alignment <= dmat->maxsize) check
586 * below is just a quick hack. The exact alignment guarantees
587 * of malloc(9) need to be nailed down, and the code below
588 * should be rewritten to take that into account.
590 * In the meantime warn the user if malloc gets it wrong.
592 if ((dmat->alloc_size <= PAGE_SIZE) &&
593 (dmat->alloc_alignment <= dmat->alloc_size) &&
594 dmat->common.lowaddr >= ptoa((vm_paddr_t)Maxmem) &&
595 attr == VM_MEMATTR_DEFAULT) {
596 *vaddr = malloc(dmat->alloc_size, M_DEVBUF, mflags);
597 } else if (dmat->common.nsegments >=
598 howmany(dmat->alloc_size, MIN(dmat->common.maxsegsz, PAGE_SIZE)) &&
599 dmat->alloc_alignment <= PAGE_SIZE &&
600 (dmat->common.boundary % PAGE_SIZE) == 0) {
601 /* Page-based multi-segment allocations allowed */
602 *vaddr = (void *)kmem_alloc_attr(dmat->alloc_size, mflags,
603 0ul, dmat->common.lowaddr, attr);
604 dmat->bounce_flags |= BF_KMEM_ALLOC;
606 *vaddr = (void *)kmem_alloc_contig(dmat->alloc_size, mflags,
607 0ul, dmat->common.lowaddr, dmat->alloc_alignment != 0 ?
608 dmat->alloc_alignment : 1ul, dmat->common.boundary, attr);
609 dmat->bounce_flags |= BF_KMEM_ALLOC;
611 if (*vaddr == NULL) {
612 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
613 __func__, dmat, dmat->common.flags, ENOMEM);
614 free(*mapp, M_DEVBUF);
616 } else if (vtophys(*vaddr) & (dmat->alloc_alignment - 1)) {
617 printf("bus_dmamem_alloc failed to align memory properly.\n");
620 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
621 __func__, dmat, dmat->common.flags, 0);
626 * Free a piece of memory and it's allociated dmamap, that was allocated
627 * via bus_dmamem_alloc. Make the same choice for free/contigfree.
630 bounce_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map)
634 * Check the map came from bounce_bus_dmamem_alloc, so the map
635 * should be NULL and the BF_KMEM_ALLOC flag cleared if malloc()
636 * was used and set if kmem_alloc_contig() was used.
638 if ((map->flags & DMAMAP_FROM_DMAMEM) == 0)
639 panic("bus_dmamem_free: Invalid map freed\n");
640 if ((dmat->bounce_flags & BF_KMEM_ALLOC) == 0)
641 free(vaddr, M_DEVBUF);
643 kmem_free((vm_offset_t)vaddr, dmat->alloc_size);
646 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat,
651 _bus_dmamap_pagesneeded(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf,
652 bus_size_t buflen, int *pagesneeded)
659 * Count the number of bounce pages needed in order to
660 * complete this transfer
664 while (buflen != 0) {
665 sgsize = MIN(buflen, dmat->common.maxsegsz);
666 if (must_bounce(dmat, map, curaddr, sgsize)) {
668 PAGE_SIZE - (curaddr & PAGE_MASK));
669 if (pagesneeded == NULL)
677 if (pagesneeded != NULL)
678 *pagesneeded = count;
683 _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf,
684 bus_size_t buflen, int flags)
687 if (map->pagesneeded == 0) {
688 _bus_dmamap_pagesneeded(dmat, map, buf, buflen,
690 CTR1(KTR_BUSDMA, "pagesneeded= %d\n", map->pagesneeded);
695 _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, pmap_t pmap,
696 void *buf, bus_size_t buflen, int flags)
699 vm_offset_t vendaddr;
703 if (map->pagesneeded == 0) {
704 CTR4(KTR_BUSDMA, "lowaddr= %d Maxmem= %d, boundary= %d, "
705 "alignment= %d", dmat->common.lowaddr,
706 ptoa((vm_paddr_t)Maxmem),
707 dmat->common.boundary, dmat->common.alignment);
708 CTR2(KTR_BUSDMA, "map= %p, pagesneeded= %d", map,
711 * Count the number of bounce pages
712 * needed in order to complete this transfer
714 vaddr = (vm_offset_t)buf;
715 vendaddr = (vm_offset_t)buf + buflen;
717 while (vaddr < vendaddr) {
718 sg_len = PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK);
719 if (pmap == kernel_pmap)
720 paddr = pmap_kextract(vaddr);
722 paddr = pmap_extract(pmap, vaddr);
723 if (must_bounce(dmat, map, paddr,
724 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr &
725 PAGE_MASK)))) != 0) {
726 sg_len = roundup2(sg_len,
727 dmat->common.alignment);
732 CTR1(KTR_BUSDMA, "pagesneeded= %d\n", map->pagesneeded);
737 _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags)
740 /* Reserve Necessary Bounce Pages */
741 mtx_lock(&bounce_lock);
742 if (flags & BUS_DMA_NOWAIT) {
743 if (reserve_bounce_pages(dmat, map, 0) != 0) {
744 mtx_unlock(&bounce_lock);
748 if (reserve_bounce_pages(dmat, map, 1) != 0) {
749 /* Queue us for resources */
750 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links);
751 mtx_unlock(&bounce_lock);
752 return (EINPROGRESS);
755 mtx_unlock(&bounce_lock);
761 * Add a single contiguous physical range to the segment list.
764 _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr,
765 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp)
767 bus_addr_t baddr, bmask;
771 * Make sure we don't cross any boundaries.
773 bmask = ~(dmat->common.boundary - 1);
774 if (dmat->common.boundary > 0) {
775 baddr = (curaddr + dmat->common.boundary) & bmask;
776 if (sgsize > (baddr - curaddr))
777 sgsize = (baddr - curaddr);
781 * Insert chunk into a segment, coalescing with
782 * previous segment if possible.
787 segs[seg].ds_addr = curaddr;
788 segs[seg].ds_len = sgsize;
790 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len &&
791 (segs[seg].ds_len + sgsize) <= dmat->common.maxsegsz &&
792 (dmat->common.boundary == 0 ||
793 (segs[seg].ds_addr & bmask) == (curaddr & bmask)))
794 segs[seg].ds_len += sgsize;
796 if (++seg >= dmat->common.nsegments)
798 segs[seg].ds_addr = curaddr;
799 segs[seg].ds_len = sgsize;
807 * Utility function to load a physical buffer. segp contains
808 * the starting segment on entrace, and the ending segment on exit.
811 bounce_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map,
812 vm_paddr_t buf, bus_size_t buflen, int flags, bus_dma_segment_t *segs,
815 struct sync_list *sl;
817 bus_addr_t curaddr, sl_end;
821 segs = dmat->segments;
823 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) {
824 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags);
825 if (map->pagesneeded != 0) {
826 error = _bus_dmamap_reserve_pages(dmat, map, flags);
832 sl = map->slist + map->sync_count - 1;
837 sgsize = MIN(buflen, dmat->common.maxsegsz);
838 if (map->pagesneeded != 0 &&
839 must_bounce(dmat, map, curaddr, sgsize)) {
841 * The attempt to split a physically continuous buffer
842 * seems very controversial, it's unclear whether we
843 * can do this in all cases. Also, memory for bounced
844 * buffers is allocated as pages, so we cannot
845 * guarantee multipage alignment.
847 KASSERT(dmat->common.alignment <= PAGE_SIZE,
848 ("bounced buffer cannot have alignment bigger "
849 "than PAGE_SIZE: %lu", dmat->common.alignment));
850 sgsize = MIN(sgsize, PAGE_SIZE - (curaddr & PAGE_MASK));
851 curaddr = add_bounce_page(dmat, map, 0, curaddr,
853 } else if ((map->flags & DMAMAP_COHERENT) == 0) {
854 if (map->sync_count > 0)
855 sl_end = sl->paddr + sl->datacount;
857 if (map->sync_count == 0 || curaddr != sl_end) {
858 if (++map->sync_count > dmat->common.nsegments)
863 sl->pages = PHYS_TO_VM_PAGE(curaddr);
864 KASSERT(sl->pages != NULL,
865 ("%s: page at PA:0x%08lx is not in "
866 "vm_page_array", __func__, curaddr));
867 sl->datacount = sgsize;
869 sl->datacount += sgsize;
871 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
883 bus_dmamap_unload(dmat, map);
884 return (EFBIG); /* XXX better return value here? */
890 * Utility function to load a linear buffer. segp contains
891 * the starting segment on entrace, and the ending segment on exit.
894 bounce_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf,
895 bus_size_t buflen, pmap_t pmap, int flags, bus_dma_segment_t *segs,
898 struct sync_list *sl;
900 bus_addr_t curaddr, sl_pend;
901 vm_offset_t kvaddr, vaddr, sl_vend;
904 KASSERT((map->flags & DMAMAP_FROM_DMAMEM) != 0 ||
905 dmat->common.alignment <= PAGE_SIZE,
906 ("loading user buffer with alignment bigger than PAGE_SIZE is not "
910 segs = dmat->segments;
912 if (flags & BUS_DMA_LOAD_MBUF)
913 map->flags |= DMAMAP_MBUF;
915 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) {
916 _bus_dmamap_count_pages(dmat, map, pmap, buf, buflen, flags);
917 if (map->pagesneeded != 0) {
918 error = _bus_dmamap_reserve_pages(dmat, map, flags);
925 * XXX Optimally we should parse input buffer for physically
926 * continuous segments first and then pass these segment into
929 sl = map->slist + map->sync_count - 1;
930 vaddr = (vm_offset_t)buf;
936 * Get the physical address for this segment.
938 if (__predict_true(pmap == kernel_pmap)) {
939 curaddr = pmap_kextract(vaddr);
942 curaddr = pmap_extract(pmap, vaddr);
947 * Compute the segment size, and adjust counts.
949 sgsize = MIN(buflen, dmat->common.maxsegsz);
950 if ((map->flags & DMAMAP_FROM_DMAMEM) == 0)
951 sgsize = MIN(sgsize, PAGE_SIZE - (curaddr & PAGE_MASK));
953 if (map->pagesneeded != 0 &&
954 must_bounce(dmat, map, curaddr, sgsize)) {
955 /* See comment in bounce_bus_dmamap_load_phys */
956 KASSERT(dmat->common.alignment <= PAGE_SIZE,
957 ("bounced buffer cannot have alignment bigger "
958 "than PAGE_SIZE: %lu", dmat->common.alignment));
959 curaddr = add_bounce_page(dmat, map, kvaddr, curaddr,
961 } else if ((map->flags & DMAMAP_COHERENT) == 0) {
962 if (map->sync_count > 0) {
963 sl_pend = sl->paddr + sl->datacount;
964 sl_vend = sl->vaddr + sl->datacount;
967 if (map->sync_count == 0 ||
968 (kvaddr != 0 && kvaddr != sl_vend) ||
969 (curaddr != sl_pend)) {
970 if (++map->sync_count > dmat->common.nsegments)
978 sl->pages = PHYS_TO_VM_PAGE(curaddr);
979 KASSERT(sl->pages != NULL,
980 ("%s: page at PA:0x%08lx is not "
981 "in vm_page_array", __func__,
984 sl->datacount = sgsize;
986 sl->datacount += sgsize;
988 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
1000 bus_dmamap_unload(dmat, map);
1001 return (EFBIG); /* XXX better return value here? */
1007 bounce_bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map,
1008 struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg)
1013 map->callback = callback;
1014 map->callback_arg = callback_arg;
1017 static bus_dma_segment_t *
1018 bounce_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
1019 bus_dma_segment_t *segs, int nsegs, int error)
1023 segs = dmat->segments;
1028 * Release the mapping held by map.
1031 bounce_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map)
1033 struct bounce_page *bpage;
1035 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
1036 STAILQ_REMOVE_HEAD(&map->bpages, links);
1037 free_bounce_page(dmat, bpage);
1040 map->sync_count = 0;
1041 map->flags &= ~DMAMAP_MBUF;
1045 dma_preread_safe(vm_offset_t va, vm_size_t size)
1048 * Write back any partial cachelines immediately before and
1049 * after the DMA region.
1051 if (va & (dcache_line_size - 1))
1052 cpu_dcache_wb_range(va, 1);
1053 if ((va + size) & (dcache_line_size - 1))
1054 cpu_dcache_wb_range(va + size, 1);
1056 cpu_dcache_inv_range(va, size);
1060 dma_dcache_sync(struct sync_list *sl, bus_dmasync_op_t op)
1062 uint32_t len, offset;
1065 vm_offset_t va, tempva;
1068 offset = sl->paddr & PAGE_MASK;
1070 size = sl->datacount;
1073 for ( ; size != 0; size -= len, pa += len, offset = 0, ++m) {
1075 if (sl->vaddr == 0) {
1076 len = min(PAGE_SIZE - offset, size);
1077 tempva = pmap_quick_enter_page(m);
1078 va = tempva | offset;
1079 KASSERT(pa == (VM_PAGE_TO_PHYS(m) | offset),
1080 ("unexpected vm_page_t phys: 0x%16lx != 0x%16lx",
1081 VM_PAGE_TO_PHYS(m) | offset, pa));
1083 len = sl->datacount;
1088 case BUS_DMASYNC_PREWRITE:
1089 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD:
1090 cpu_dcache_wb_range(va, len);
1092 case BUS_DMASYNC_PREREAD:
1094 * An mbuf may start in the middle of a cacheline. There
1095 * will be no cpu writes to the beginning of that line
1096 * (which contains the mbuf header) while dma is in
1097 * progress. Handle that case by doing a writeback of
1098 * just the first cacheline before invalidating the
1099 * overall buffer. Any mbuf in a chain may have this
1100 * misalignment. Buffers which are not mbufs bounce if
1101 * they are not aligned to a cacheline.
1103 dma_preread_safe(va, len);
1105 case BUS_DMASYNC_POSTREAD:
1106 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
1107 cpu_dcache_inv_range(va, len);
1110 panic("unsupported combination of sync operations: "
1115 pmap_quick_remove_page(tempva);
1120 bounce_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
1121 bus_dmasync_op_t op)
1123 struct bounce_page *bpage;
1124 struct sync_list *sl, *end;
1125 vm_offset_t datavaddr, tempvaddr;
1127 if (op == BUS_DMASYNC_POSTWRITE)
1130 if ((op & BUS_DMASYNC_POSTREAD) != 0) {
1132 * Wait for any DMA operations to complete before the bcopy.
1137 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
1138 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x "
1139 "performing bounce", __func__, dmat, dmat->common.flags,
1142 if ((op & BUS_DMASYNC_PREWRITE) != 0) {
1143 while (bpage != NULL) {
1145 datavaddr = bpage->datavaddr;
1146 if (datavaddr == 0) {
1147 tempvaddr = pmap_quick_enter_page(
1149 datavaddr = tempvaddr | bpage->dataoffs;
1152 bcopy((void *)datavaddr,
1153 (void *)bpage->vaddr, bpage->datacount);
1155 pmap_quick_remove_page(tempvaddr);
1156 if ((map->flags & DMAMAP_COHERENT) == 0)
1157 cpu_dcache_wb_range(bpage->vaddr,
1159 bpage = STAILQ_NEXT(bpage, links);
1161 dmat->bounce_zone->total_bounced++;
1162 } else if ((op & BUS_DMASYNC_PREREAD) != 0) {
1163 while (bpage != NULL) {
1164 if ((map->flags & DMAMAP_COHERENT) == 0)
1165 cpu_dcache_wbinv_range(bpage->vaddr,
1167 bpage = STAILQ_NEXT(bpage, links);
1171 if ((op & BUS_DMASYNC_POSTREAD) != 0) {
1172 while (bpage != NULL) {
1173 if ((map->flags & DMAMAP_COHERENT) == 0)
1174 cpu_dcache_inv_range(bpage->vaddr,
1177 datavaddr = bpage->datavaddr;
1178 if (datavaddr == 0) {
1179 tempvaddr = pmap_quick_enter_page(
1181 datavaddr = tempvaddr | bpage->dataoffs;
1184 bcopy((void *)bpage->vaddr,
1185 (void *)datavaddr, bpage->datacount);
1188 pmap_quick_remove_page(tempvaddr);
1189 bpage = STAILQ_NEXT(bpage, links);
1191 dmat->bounce_zone->total_bounced++;
1196 * Cache maintenance for normal (non-COHERENT non-bounce) buffers.
1198 if (map->sync_count != 0) {
1199 sl = &map->slist[0];
1200 end = &map->slist[map->sync_count];
1201 CTR3(KTR_BUSDMA, "%s: tag %p op 0x%x "
1202 "performing sync", __func__, dmat, op);
1204 for ( ; sl != end; ++sl)
1205 dma_dcache_sync(sl, op);
1208 if ((op & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0) {
1210 * Wait for the bcopy to complete before any DMA operations.
1217 init_bounce_pages(void *dummy __unused)
1221 STAILQ_INIT(&bounce_zone_list);
1222 STAILQ_INIT(&bounce_map_waitinglist);
1223 STAILQ_INIT(&bounce_map_callbacklist);
1224 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF);
1226 SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL);
1228 static struct sysctl_ctx_list *
1229 busdma_sysctl_tree(struct bounce_zone *bz)
1232 return (&bz->sysctl_tree);
1235 static struct sysctl_oid *
1236 busdma_sysctl_tree_top(struct bounce_zone *bz)
1239 return (bz->sysctl_tree_top);
1243 alloc_bounce_zone(bus_dma_tag_t dmat)
1245 struct bounce_zone *bz;
1247 /* Check to see if we already have a suitable zone */
1248 STAILQ_FOREACH(bz, &bounce_zone_list, links) {
1249 if ((dmat->common.alignment <= bz->alignment) &&
1250 (dmat->common.lowaddr >= bz->lowaddr)) {
1251 dmat->bounce_zone = bz;
1256 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF,
1257 M_NOWAIT | M_ZERO)) == NULL)
1260 STAILQ_INIT(&bz->bounce_page_list);
1261 bz->free_bpages = 0;
1262 bz->reserved_bpages = 0;
1263 bz->active_bpages = 0;
1264 bz->lowaddr = dmat->common.lowaddr;
1265 bz->alignment = MAX(dmat->common.alignment, PAGE_SIZE);
1267 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount);
1269 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr);
1270 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links);
1271 dmat->bounce_zone = bz;
1273 sysctl_ctx_init(&bz->sysctl_tree);
1274 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree,
1275 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid,
1276 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
1277 if (bz->sysctl_tree_top == NULL) {
1278 sysctl_ctx_free(&bz->sysctl_tree);
1279 return (0); /* XXX error code? */
1282 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1283 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1284 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0,
1285 "Total bounce pages");
1286 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1287 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1288 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0,
1289 "Free bounce pages");
1290 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1291 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1292 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0,
1293 "Reserved bounce pages");
1294 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1295 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1296 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0,
1297 "Active bounce pages");
1298 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1299 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1300 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0,
1301 "Total bounce requests");
1302 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1303 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1304 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0,
1305 "Total bounce requests that were deferred");
1306 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz),
1307 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1308 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, "");
1309 SYSCTL_ADD_UAUTO(busdma_sysctl_tree(bz),
1310 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1311 "alignment", CTLFLAG_RD, &bz->alignment, "");
1317 alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages)
1319 struct bounce_zone *bz;
1322 bz = dmat->bounce_zone;
1324 while (numpages > 0) {
1325 struct bounce_page *bpage;
1327 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF,
1332 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF,
1333 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0);
1334 if (bpage->vaddr == 0) {
1335 free(bpage, M_DEVBUF);
1338 bpage->busaddr = pmap_kextract(bpage->vaddr);
1339 mtx_lock(&bounce_lock);
1340 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links);
1344 mtx_unlock(&bounce_lock);
1352 reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit)
1354 struct bounce_zone *bz;
1357 mtx_assert(&bounce_lock, MA_OWNED);
1358 bz = dmat->bounce_zone;
1359 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved);
1360 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages))
1361 return (map->pagesneeded - (map->pagesreserved + pages));
1362 bz->free_bpages -= pages;
1363 bz->reserved_bpages += pages;
1364 map->pagesreserved += pages;
1365 pages = map->pagesneeded - map->pagesreserved;
1371 add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr,
1372 bus_addr_t addr, bus_size_t size)
1374 struct bounce_zone *bz;
1375 struct bounce_page *bpage;
1377 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag"));
1379 bz = dmat->bounce_zone;
1380 if (map->pagesneeded == 0)
1381 panic("add_bounce_page: map doesn't need any pages");
1384 if (map->pagesreserved == 0)
1385 panic("add_bounce_page: map doesn't need any pages");
1386 map->pagesreserved--;
1388 mtx_lock(&bounce_lock);
1389 bpage = STAILQ_FIRST(&bz->bounce_page_list);
1391 panic("add_bounce_page: free page list is empty");
1393 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links);
1394 bz->reserved_bpages--;
1395 bz->active_bpages++;
1396 mtx_unlock(&bounce_lock);
1398 if (dmat->common.flags & BUS_DMA_KEEP_PG_OFFSET) {
1399 /* Page offset needs to be preserved. */
1400 bpage->vaddr |= addr & PAGE_MASK;
1401 bpage->busaddr |= addr & PAGE_MASK;
1403 bpage->datavaddr = vaddr;
1404 bpage->datapage = PHYS_TO_VM_PAGE(addr);
1405 bpage->dataoffs = addr & PAGE_MASK;
1406 bpage->datacount = size;
1407 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links);
1408 return (bpage->busaddr);
1412 free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage)
1414 struct bus_dmamap *map;
1415 struct bounce_zone *bz;
1418 bz = dmat->bounce_zone;
1419 bpage->datavaddr = 0;
1420 bpage->datacount = 0;
1421 if (dmat->common.flags & BUS_DMA_KEEP_PG_OFFSET) {
1423 * Reset the bounce page to start at offset 0. Other uses
1424 * of this bounce page may need to store a full page of
1425 * data and/or assume it starts on a page boundary.
1427 bpage->vaddr &= ~PAGE_MASK;
1428 bpage->busaddr &= ~PAGE_MASK;
1431 schedule_swi = false;
1432 mtx_lock(&bounce_lock);
1433 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links);
1435 bz->active_bpages--;
1436 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) {
1437 if (reserve_bounce_pages(map->dmat, map, 1) == 0) {
1438 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links);
1439 STAILQ_INSERT_TAIL(&bounce_map_callbacklist,
1441 bz->total_deferred++;
1442 schedule_swi = true;
1445 mtx_unlock(&bounce_lock);
1447 swi_sched(busdma_ih, 0);
1451 busdma_swi(void *dummy __unused)
1454 struct bus_dmamap *map;
1456 mtx_lock(&bounce_lock);
1457 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) {
1458 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links);
1459 mtx_unlock(&bounce_lock);
1461 (dmat->common.lockfunc)(dmat->common.lockfuncarg, BUS_DMA_LOCK);
1462 bus_dmamap_load_mem(map->dmat, map, &map->mem,
1463 map->callback, map->callback_arg, BUS_DMA_WAITOK);
1464 (dmat->common.lockfunc)(dmat->common.lockfuncarg,
1466 mtx_lock(&bounce_lock);
1468 mtx_unlock(&bounce_lock);
1472 start_busdma_swi(void *dummy __unused)
1474 if (swi_add(NULL, "busdma", busdma_swi, NULL, SWI_BUSDMA, INTR_MPSAFE,
1476 panic("died while creating busdma swi ithread");
1478 SYSINIT(start_busdma_swi, SI_SUB_SOFTINTR, SI_ORDER_ANY, start_busdma_swi,
1481 struct bus_dma_impl bus_dma_bounce_impl = {
1482 .tag_create = bounce_bus_dma_tag_create,
1483 .tag_destroy = bounce_bus_dma_tag_destroy,
1484 .id_mapped = bounce_bus_dma_id_mapped,
1485 .map_create = bounce_bus_dmamap_create,
1486 .map_destroy = bounce_bus_dmamap_destroy,
1487 .mem_alloc = bounce_bus_dmamem_alloc,
1488 .mem_free = bounce_bus_dmamem_free,
1489 .load_phys = bounce_bus_dmamap_load_phys,
1490 .load_buffer = bounce_bus_dmamap_load_buffer,
1491 .load_ma = bus_dmamap_load_ma_triv,
1492 .map_waitok = bounce_bus_dmamap_waitok,
1493 .map_complete = bounce_bus_dmamap_complete,
1494 .map_unload = bounce_bus_dmamap_unload,
1495 .map_sync = bounce_bus_dmamap_sync