sys/arm64/arm64/cpu_errata.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2018 Andrew Turner
   5  * All rights reserved.
   6  *
   7  * This software was developed by SRI International and the University of
   8  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
   9  * ("CTSRD"), as part of the DARPA CRASH research programme.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/kernel.h>
  40 #include <sys/pcpu.h>
  41
  42 #include <machine/cpu.h>
  43
  44 #include <dev/psci/smccc.h>
  45
  46 typedef void (cpu_quirk_install)(void);
  47 struct cpu_quirks {
  48         cpu_quirk_install *quirk_install;
  49         u_int           midr_mask;
  50         u_int           midr_value;
  51 };
  52
  53 static cpu_quirk_install install_psci_bp_hardening;
  54
  55 static struct cpu_quirks cpu_quirks[] = {
  56         {
  57                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  58                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A57,0,0),
  59                 .quirk_install = install_psci_bp_hardening,
  60         },
  61         {
  62                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  63                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A72,0,0),
  64                 .quirk_install = install_psci_bp_hardening,
  65         },
  66         {
  67                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  68                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A73,0,0),
  69                 .quirk_install = install_psci_bp_hardening,
  70         },
  71         {
  72                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  73                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A75,0,0),
  74                 .quirk_install = install_psci_bp_hardening,
  75         },
  76         {
  77                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  78                 .midr_value =
  79                     CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0,0),
  80                 .quirk_install = install_psci_bp_hardening,
  81         },
  82 };
  83
  84 static void
  85 install_psci_bp_hardening(void)
  86 {
  87
  88         if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_1) != SMCCC_RET_SUCCESS)
  89                 return;
  90
  91         PCPU_SET(bp_harden, smccc_arch_workaround_1);
  92 }
  93
  94 void
  95 install_cpu_errata(void)
  96 {
  97         u_int midr;
  98         size_t i;
  99
 100         midr = get_midr();
 101
 102         for (i = 0; i < nitems(cpu_quirks); i++) {
 103                 if ((midr & cpu_quirks[i].midr_mask) ==
 104                     cpu_quirks[i].midr_value) {
 105                         cpu_quirks[i].quirk_install();
 106                 }
 107         }
 108 }