sys/arm64/arm64/cpu_errata.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2018 Andrew Turner
   5  * All rights reserved.
   6  *
   7  * This software was developed by SRI International and the University of
   8  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
   9  * ("CTSRD"), as part of the DARPA CRASH research programme.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/kernel.h>
  40 #include <sys/pcpu.h>
  41 #include <sys/systm.h>
  42
  43 #include <machine/cpu.h>
  44
  45 #include <dev/psci/smccc.h>
  46
  47 typedef void (cpu_quirk_install)(void);
  48 struct cpu_quirks {
  49         cpu_quirk_install *quirk_install;
  50         u_int           midr_mask;
  51         u_int           midr_value;
  52 };
  53
  54 static enum {
  55         SSBD_FORCE_ON,
  56         SSBD_FORCE_OFF,
  57         SSBD_KERNEL,
  58 } ssbd_method = SSBD_KERNEL;
  59
  60 static cpu_quirk_install install_psci_bp_hardening;
  61 static cpu_quirk_install install_ssbd_workaround;
  62
  63 static struct cpu_quirks cpu_quirks[] = {
  64         {
  65                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  66                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A57,0,0),
  67                 .quirk_install = install_psci_bp_hardening,
  68         },
  69         {
  70                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  71                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A72,0,0),
  72                 .quirk_install = install_psci_bp_hardening,
  73         },
  74         {
  75                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  76                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A73,0,0),
  77                 .quirk_install = install_psci_bp_hardening,
  78         },
  79         {
  80                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  81                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A75,0,0),
  82                 .quirk_install = install_psci_bp_hardening,
  83         },
  84         {
  85                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  86                 .midr_value =
  87                     CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0,0),
  88                 .quirk_install = install_psci_bp_hardening,
  89         },
  90         {
  91                 .midr_mask = 0,
  92                 .midr_value = 0,
  93                 .quirk_install = install_ssbd_workaround,
  94         },
  95 };
  96
  97 static void
  98 install_psci_bp_hardening(void)
  99 {
 100
 101         if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_1) != SMCCC_RET_SUCCESS)
 102                 return;
 103
 104         PCPU_SET(bp_harden, smccc_arch_workaround_1);
 105 }
 106
 107 static void
 108 install_ssbd_workaround(void)
 109 {
 110         char *env;
 111
 112         if (PCPU_GET(cpuid) == 0) {
 113                 env = kern_getenv("kern.cfg.ssbd");
 114                 if (env != NULL) {
 115                         if (strcmp(env, "force-on") == 0) {
 116                                 ssbd_method = SSBD_FORCE_ON;
 117                         } else if (strcmp(env, "force-off") == 0) {
 118                                 ssbd_method = SSBD_FORCE_OFF;
 119                         }
 120                 }
 121         }
 122
 123         /* Enable the workaround on this CPU if it's enabled in the firmware */
 124         if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_2) != SMCCC_RET_SUCCESS)
 125                 return;
 126
 127         switch(ssbd_method) {
 128         case SSBD_FORCE_ON:
 129                 smccc_arch_workaround_2(1);
 130                 break;
 131         case SSBD_FORCE_OFF:
 132                 smccc_arch_workaround_2(0);
 133                 break;
 134         case SSBD_KERNEL:
 135         default:
 136                 PCPU_SET(ssbd, smccc_arch_workaround_2);
 137                 break;
 138         }
 139 }
 140
 141 void
 142 install_cpu_errata(void)
 143 {
 144         u_int midr;
 145         size_t i;
 146
 147         midr = get_midr();
 148
 149         for (i = 0; i < nitems(cpu_quirks); i++) {
 150                 if ((midr & cpu_quirks[i].midr_mask) ==
 151                     cpu_quirks[i].midr_value) {
 152                         cpu_quirks[i].quirk_install();
 153                 }
 154         }
 155 }