sys/arm64/arm64/cpu_errata.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2018 Andrew Turner
   5  * All rights reserved.
   6  *
   7  * This software was developed by SRI International and the University of
   8  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
   9  * ("CTSRD"), as part of the DARPA CRASH research programme.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include "opt_platform.h"
  34
  35 #include <sys/cdefs.h>
  36 #include <sys/param.h>
  37 #include <sys/kernel.h>
  38 #include <sys/pcpu.h>
  39 #include <sys/systm.h>
  40
  41 #include <machine/cpu.h>
  42
  43 #include <dev/psci/smccc.h>
  44
  45 typedef void (cpu_quirk_install)(void);
  46 struct cpu_quirks {
  47         cpu_quirk_install *quirk_install;
  48         u_int           midr_mask;
  49         u_int           midr_value;
  50 };
  51
  52 static enum {
  53         SSBD_FORCE_ON,
  54         SSBD_FORCE_OFF,
  55         SSBD_KERNEL,
  56 } ssbd_method = SSBD_KERNEL;
  57
  58 static cpu_quirk_install install_psci_bp_hardening;
  59 static cpu_quirk_install install_ssbd_workaround;
  60 static cpu_quirk_install install_thunderx_bcast_tlbi_workaround;
  61
  62 static struct cpu_quirks cpu_quirks[] = {
  63         {
  64                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  65                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A57,0,0),
  66                 .quirk_install = install_psci_bp_hardening,
  67         },
  68         {
  69                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  70                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A72,0,0),
  71                 .quirk_install = install_psci_bp_hardening,
  72         },
  73         {
  74                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  75                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A73,0,0),
  76                 .quirk_install = install_psci_bp_hardening,
  77         },
  78         {
  79                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  80                 .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A75,0,0),
  81                 .quirk_install = install_psci_bp_hardening,
  82         },
  83         {
  84                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  85                 .midr_value =
  86                     CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0,0),
  87                 .quirk_install = install_psci_bp_hardening,
  88         },
  89         {
  90                 .midr_mask = 0,
  91                 .midr_value = 0,
  92                 .quirk_install = install_ssbd_workaround,
  93         },
  94         {
  95                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
  96                 .midr_value =
  97                     CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0),
  98                 .quirk_install = install_thunderx_bcast_tlbi_workaround,
  99         },
 100         {
 101                 .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
 102                 .midr_value =
 103                     CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX_81XX, 0, 0),
 104                 .quirk_install = install_thunderx_bcast_tlbi_workaround,
 105         },
 106 };
 107
 108 static void
 109 install_psci_bp_hardening(void)
 110 {
 111
 112         if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_1) != SMCCC_RET_SUCCESS)
 113                 return;
 114
 115         PCPU_SET(bp_harden, smccc_arch_workaround_1);
 116 }
 117
 118 static void
 119 install_ssbd_workaround(void)
 120 {
 121         char *env;
 122
 123         if (PCPU_GET(cpuid) == 0) {
 124                 env = kern_getenv("kern.cfg.ssbd");
 125                 if (env != NULL) {
 126                         if (strcmp(env, "force-on") == 0) {
 127                                 ssbd_method = SSBD_FORCE_ON;
 128                         } else if (strcmp(env, "force-off") == 0) {
 129                                 ssbd_method = SSBD_FORCE_OFF;
 130                         }
 131                 }
 132         }
 133
 134         /* Enable the workaround on this CPU if it's enabled in the firmware */
 135         if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_2) != SMCCC_RET_SUCCESS)
 136                 return;
 137
 138         switch(ssbd_method) {
 139         case SSBD_FORCE_ON:
 140                 smccc_arch_workaround_2(1);
 141                 break;
 142         case SSBD_FORCE_OFF:
 143                 smccc_arch_workaround_2(0);
 144                 break;
 145         case SSBD_KERNEL:
 146         default:
 147                 PCPU_SET(ssbd, smccc_arch_workaround_2);
 148                 break;
 149         }
 150 }
 151
 152 /*
 153  * Workaround Cavium erratum 27456.
 154  *
 155  * Invalidate the local icache when changing address spaces.
 156  */
 157 static void
 158 install_thunderx_bcast_tlbi_workaround(void)
 159 {
 160         u_int midr;
 161
 162         midr = get_midr();
 163         if (CPU_PART(midr) == CPU_PART_THUNDERX_81XX)
 164                 PCPU_SET(bcast_tlbi_workaround, 1);
 165         else if (CPU_PART(midr) == CPU_PART_THUNDERX) {
 166                 if (CPU_VAR(midr) == 0) {
 167                         /* ThunderX 1.x */
 168                         PCPU_SET(bcast_tlbi_workaround, 1);
 169                 } else if (CPU_VAR(midr) == 1 && CPU_REV(midr) <= 1) {
 170                         /* ThunderX 2.0 - 2.1 */
 171                         PCPU_SET(bcast_tlbi_workaround, 1);
 172                 }
 173         }
 174 }
 175
 176 void
 177 install_cpu_errata(void)
 178 {
 179         u_int midr;
 180         size_t i;
 181
 182         midr = get_midr();
 183
 184         for (i = 0; i < nitems(cpu_quirks); i++) {
 185                 if ((midr & cpu_quirks[i].midr_mask) ==
 186                     cpu_quirks[i].midr_value) {
 187                         cpu_quirks[i].quirk_install();
 188                 }
 189         }
 190 }